CN115832134A - Light emitting diode epitaxial wafer, preparation method thereof and light emitting diode - Google Patents
Light emitting diode epitaxial wafer, preparation method thereof and light emitting diode Download PDFInfo
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Abstract
The invention discloses a light emitting diode epitaxial wafer and a preparation method thereof, wherein the light emitting diode epitaxial wafer comprises a substrate, and a nucleation layer, an intrinsic GaN layer, an N-GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-GaN layer which are sequentially arranged on the substrate; and a buffer layer is arranged between the N-GaN layer and the multi-quantum well layer, and comprises a MgN three-dimensional induction layer, a SiGaN three-dimensional layer and a filling layer which are sequentially arranged on the N-GaN layer. The invention also discloses a light emitting diode. The invention can effectively release the bottom layer stress, make the electron hole distribution of the multi-quantum well region uniform, improve the expansion capability of the electron, and improve the luminous efficiency and the antistatic capability of the light-emitting diode.
Description
Technical Field
The invention relates to the field of semiconductor photoelectric devices, in particular to a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode.
Background
In order to improve the defects of the structure, a low-temperature stress release layer is inserted between the N-type semiconductor layer and the multiple quantum wells in the conventional epitaxial wafer structure, and the stress release layer is an InGaN layer.
Disclosure of Invention
The invention aims to provide a light emitting diode epitaxial wafer and a preparation method thereof, which can effectively release bottom layer stress, make electron holes of a multi-quantum well region uniformly distributed, improve the expansion capability of electrons, and improve the light emitting efficiency and the antistatic capability of a light emitting diode.
In order to solve the technical problem, the invention discloses a light emitting diode epitaxial wafer which comprises a substrate, and a nucleation layer, an intrinsic GaN layer, an N-GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-GaN layer which are sequentially arranged on the substrate; and a buffer layer is arranged between the N-GaN layer and the multi-quantum well layer, and comprises a MgN three-dimensional induction layer, a SiGaN three-dimensional layer and a filling layer which are sequentially arranged on the N-GaN layer.
As an improvement of the scheme, the MgN three-dimensional inducing layer is Mg x N 1-x A layer, wherein x has a value in the range of 0.1-0.3;
the doping concentration of Si in the SiGaN three-dimensional layer is 1 multiplied by 10 16 -1×10 18 cm -3 ；
The doping concentration of Si in the SiGaN three-dimensional layer is less than that of Si in the N-GaN layer.
As an improvement of the scheme, the thickness of the MgN three-dimensional inducing layer is 2-5nm;
the thickness of the SiGaN three-dimensional layer is 20-50nm, and the diameter of the SiGaN three-dimensional layer is 10-30nm;
the thickness of the filling and leveling layer is 20-50nm;
the thickness of the filling and leveling layer is larger than that of the SiGaN three-dimensional layer.
As an improvement of the scheme, a BN layer is arranged between the N-GaN layer and the MgN three-dimensional induction layer;
the BN layer is B y N 1-y A layer, wherein y ranges from 0.2 to 0.4;
the thickness of the BN layer is 10-20nm;
a graphene layer is arranged between the BN layer and the MgN three-dimensional induction layer;
the thickness of the graphene layer is 20-30nm;
the filling and leveling layer is an AlGaN layer.
Correspondingly, the invention also discloses a preparation method of the light emitting diode epitaxial wafer, which is used for preparing the light emitting diode epitaxial wafer and comprises the following steps:
(1) Providing a substrate;
(2) Growing a nuclear layer, an intrinsic GaN layer, an N-GaN layer, a buffer layer, a multi-quantum well layer, an electronic barrier layer and a P-GaN layer on the substrate in sequence;
the buffer layer comprises a MgN three-dimensional inducing layer, a SiGaN three-dimensional layer and a filling layer which are sequentially arranged on the N-GaN layer.
As an improvement of the scheme, the growth temperature of the MgN three-dimensional inducing layer and the SiGaN three-dimensional layer is 750-900 ℃, and the growth pressure is 300-500Torr;
the growth temperature of the filling and leveling layer is 950-1000 ℃, and the growth pressure is 150-300Torr.
As an improvement of the scheme, the growth carrier gas of the MgN three-dimensional inducing layer and the SiGaN three-dimensional layer is hydrogen and nitrogen, wherein the volume ratio of the nitrogen to the hydrogen is N 2 ：H 2 >2：1；
The growth carrier gas of the filling layer is hydrogen and nitrogen, wherein the volume ratio N of the nitrogen to the hydrogen 2 ：H 2 ＜1：2。
As an improvement of the scheme, the buffer layer comprises a BN layer, an MgN three-dimensional inducing layer, an SiGaN three-dimensional layer and a filling layer which are sequentially arranged on the N-GaN layer;
the growth temperature of the BN layer is 1000-1050 ℃, the growth pressure is 50-150Torr, and the growth carrier gas is hydrogen.
As an improvement of the scheme, the buffer layer comprises a BN layer, a graphene layer, an MgN three-dimensional induction layer, an SiGaN three-dimensional layer and a filling layer which are sequentially arranged on the N-GaN layer;
the growth temperature of the graphene layer is 800-1000 ℃, the growth pressure is 7.5-375Torr, and the growth carrier gas is hydrogen or/and argon.
Correspondingly, the invention also discloses a light-emitting diode which comprises the light-emitting diode epitaxial wafer.
The implementation of the invention has the following beneficial effects:
1. the light emitting diode epitaxial wafer provided by the invention is characterized in that a buffer layer is arranged between the N-GaN layer and the multi-quantum well layer, and sequentially comprises an MgN three-dimensional induction layer, an SiGaN three-dimensional layer and a filling layer. The MgN three-dimensional inducing layer can induce the longitudinal growth of a follow-up SiGaN three-dimensional layer on the one hand, and on the other hand, because Mg atoms are doped as P type, a small amount of holes can be generated, partial electrons can be consumed, the phenomenon of uneven distribution of electron holes in the multi-quantum well region is improved, and the electron holes in the multi-quantum well region are uniformly distributed. Secondly, the SiGaN three-dimensional layer can effectively relieve warping and release bottom layer stress on one hand, and then the light emitting efficiency of the light emitting diode is improved; on the other hand, the electronic expansion capability can be effectively improved, and the antistatic capability of the light-emitting diode is improved.
2. According to the light emitting diode epitaxial wafer, the BN layer is arranged between the N-GaN layer and the MgN three-dimensional induction layer, and the B atoms in the BN layer are very small, so that a compact and high BN layer can be formed, and the light emitting diode epitaxial wafer can effectively block and distort dislocation extending from the bottom layer.
3. According to the light-emitting diode epitaxial wafer, the graphene layer is arranged between the BN layer and the MgN three-dimensional induction layer, the BN layer can block the graphene layer, and graphene is prevented from diffusing downwards to influence the doping of the N-type layer. On one hand, the graphene layer can increase the expansion capability of electrons; on the other hand, the graphene has a lattice guiding effect, so that the MgN layer grown on the graphene layer is more uniformly distributed, the three-dimensional island structure formed by the SiGaN three-dimensional layer grown on the MgN layer is more uniform, the three-dimensional island structure is consistent in size, and the three-dimensional islands uniformly distributed are formed, so that fewer defects are generated when the three-dimensional islands are combined to form the buffer layer.
4. According to the invention, the composite buffer layer is grown before the multi-quantum well layer grows, so that the bottom layer stress can be effectively released, the mobility of electrons is reduced, the expansion capability of electrons is increased, and the electron hole distribution of the multi-quantum well region is more balanced; and dislocation extension is effectively blocked, the lattice quality is improved, the bottom layer stress is released, the polarization effect of a multi-quantum well region can be relieved, non-radiative recombination is reduced, and the light emitting efficiency of the light emitting diode is improved. Due to the improvement of the electronic expansion capability and the improvement of the lattice quality, the antistatic capability of the light-emitting diode is greatly improved.
Drawings
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the invention;
FIG. 2 is a schematic structural diagram of an LED epitaxial wafer according to another embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an LED epitaxial wafer according to another embodiment of the present invention;
fig. 4 is a flowchart of a method for manufacturing an led epitaxial wafer according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.
Referring to fig. 1, the invention discloses a light emitting diode epitaxial wafer, which comprises a substrate 1, and a nucleation layer 2, an intrinsic GaN layer 3, an N-GaN layer 4, a buffer layer 5, a multi-quantum well layer 6, an electron blocking layer 7 and a P-GaN layer 8 which are sequentially arranged on the substrate 1.
The buffer layer 5 comprises a MgN three-dimensional inducing layer 51, a SiGaN three-dimensional layer 52 and a filling layer 53 which are sequentially arranged on the N-GaN layer 4.
Specifically, the MgN three-dimensional inducing layer 51 is Mg x N 1-x Layer, wherein the value range of x is 0.1-0.3.
Growing a MgN three-dimensional inducing layer 51 on the N-GaN layer 4, wherein on one hand, the MgN three-dimensional inducing layer 51 can induce the subsequent SiGaN three-dimensional layer 52 to grow longitudinally; on the other hand, because Mg atoms are doped as P type, a small amount of holes can be generated, partial electrons can be consumed, the phenomenon of uneven electron hole distribution of the multi-quantum well region is improved, and the electron hole distribution of the multi-quantum well region is even. Specifically, the thickness of the MgN three-dimensional inducing layer 51 is 2 to 5nm, and when the thickness is less than 2nm, the formation of the SiGaN three-dimensional layer 52 is difficult to induce effectively; when the thickness thereof is more than 5nm, the uniformity in size of the formed three-dimensional layer is deteriorated. Illustratively, the thickness of the MgN three-dimensional inducing layer 51 is 2.1nm, 2.5nm, 3.0nm, 3.4nm, 4.0nm, 4.3nm, or 4.5nm, but is not limited thereto.
Growing a SiGaN three-dimensional layer 52 on the MgN three-dimensional inducing layer 51, and forming the SiGaN three-dimensional layer 52 with a three-dimensional island structure under the guidance of the MgN seed crystal, so that the formed three-dimensional island structures have consistent sizes and are uniformly distributed; the three-dimensional island structure of the SiGaN three-dimensional layer 52 can effectively release stress accumulated by the N-type semiconductor layer in three dimensions, effectively relieve warping, release bottom layer stress and further improve the light emitting efficiency of the light emitting diode. The doping element in the gan three-dimensional layer 52 is Si, but is not limited thereto. The Si doping concentration in the SiGaN three-dimensional layer 52 is 1 × 10 16 -1×10 18 cm -3 Which is lower than the doping concentration of Si (5X 10) in the N-GaN layer 4 18 -1×10 19 cm -3 ). SiGaN with low doping concentration has strong electronic expansion capability, and the layer is designed into a three-dimensional structure, so that the electronic expansion area is effectively increased in space, and the electronic expansion capability is greatly improved. Namely, the three-dimensional layer 52 of SiGaN can effectively improve the electron expansion capability and improve the antistatic capability of the light emitting diode. Illustratively, the doping concentration of Si in the SiGaN three-dimensional layer 52 is 1.2 × 10 16 cm -3 、1.4×10 16 cm -3 、2.2×10 16 cm -3 、5×10 16 cm -3 Or 2X 10 17 cm -3 But is not limited thereto.
Specifically, the thickness of the SiGaN three-dimensional layer 52 is 20-50nm, and when the thickness is less than 20nm, the size of the formed three-dimensional island structure is too small, so that the luminous efficiency and the antistatic capability are difficult to effectively improve; when the thickness is larger than 50nm, the formed three-dimensional island structure is inconsistent in size, and the luminous efficiency and the antistatic capability are difficult to effectively improve. Illustratively, the thickness of the SiGaN three-dimensional layer 52 is 21nm, 25nm, 30nm, 34nm, 40nm, 43nm, or 45nm, but is not limited thereto. The diameter of the SiGaN three-dimensional layer 52 is 10-30nm. Illustratively, the diameter of the SiGaN three-dimensional layer 52 is 12nm, 14.5nm, 20nm, 23.5nm, 25nm, 28.8nm, or 29nm, but is not limited thereto.
In some embodiments of the present invention, the filling-up layer 53 is an AlGaN layer or a GaN layer, and preferably, the filling-up layer 53 is an AlGaN layer, and the AlGaN layer is Al z Ga 1-z And N layers, wherein the value range of z is 0.02-0.1. On one hand, because Al atoms are small and covalent bonds between the Al atoms and N atoms are strong in the filling layer 53, the lattice stability is greatly increased, so that the lattice quality of the filling layer 53 is improved, and dislocation defects generated after the filling layer 53 grows are fewer; on the other hand, the energy level of the filling layer 53 is very high, which plays a role of electron limitation, and can significantly reduce the electron mobility, so that the electron hole distribution in the multiple quantum well is more uniform, thereby improving the light emitting efficiency and the antistatic capability.
Specifically, the thickness of the filling-up layer 53 is 20-50nm, and when the thickness is less than 20nm, the filling-up layer 53 is difficult to play a role in improving the lattice quality and stability; when the thickness is greater than 50nm, the lattice quality of the subsequent layers of the whole epitaxial structure is reduced. Illustratively, the thickness of the fill-up layer 53 is 21.5nm, 25.5nm, 31nm, 34.5nm, 41nm, 43.5nm, or 46nm, but is not limited thereto.
Furthermore, the thickness of the filling layer 53 is larger than that of the SiGaN three-dimensional layer 52, so that the surface of the epitaxial layer is in a flat two-dimensional state after the filling layer 53 grows.
Preferably, referring to fig. 2, in an embodiment of the present invention, a BN layer is disposed between the N-GaN layer and the MgN three-dimensional inducing layer; BN layer B y N 1-y And (b) a layer, wherein y has a value in the range of 0.2-0.4.
Wherein, after the N-GaN layer 4 is grown, the BN layer 54 is grown first, and since the B atoms in the BN layer 54 are very small, the dense and high BN layer 54 can be formed, which effectively blocks and distorts the dislocations extending from the bottom layer. Specifically, the thickness of the BN layer 54 is 10 to 20nm, and when the thickness is less than 10nm, the BN layer 54 is difficult to effectively block and distort dislocations extending from the underlayer; when the thickness thereof is more than 20nm, cracks are easily generated, and the luminous efficiency and the antistatic ability are rather lowered. Illustratively, the thickness of the BN layer 54 is 10nm, 11nm, 12nm, 13.5nm, 15nm, 17nm, or 18.5nm, but is not limited thereto.
Preferably, referring to fig. 3, in an embodiment of the present invention, a graphene layer is disposed between the BN layer and the MgN three-dimensional inducing layer.
The graphene layer 55 is grown on the BN layer 54, and the BN layer can block the graphene layer, so that the graphene is prevented from diffusing downwards, and the doping effect of an N-type layer is influenced. The graphene layer 55 can increase the electron expansion capability; on the other hand, the MgN three-dimensional inducing layer 51 growing on the graphene layer 55 can be distributed more uniformly by utilizing the lattice guiding effect of the graphene, so that the three-dimensional island structure formed by the SiGaN three-dimensional layer 52 growing on the MgN three-dimensional inducing layer 51 is more uniform, the three-dimensional island structure is consistent in size, and the three-dimensional islands distributed uniformly are formed, so that fewer defects are generated when the buffer layer 5 is formed by combining. Specifically, the thickness of the graphene layer 55 is 20-30nm, and when the thickness is less than 20nm, the graphene layer 55 is difficult to play a role in lattice guidance, and the uniformity of the three-dimensional island structure is difficult to effectively improve; when the thickness is more than 30nm, the material is wasted. Illustratively, the thickness of graphene layer 55 is 21nm, 22nm, 24.5nm, 25nm, 27nm, 28.5nm, or 29nm, but is not limited thereto.
Preferably, in the present invention, the buffer layer 5 has a total thickness of 70 to 160nm, and exemplary is 72nm, 85nm, 95nm, 108nm, 112nm, 125nm, 132nm, 134nm or 148nm, but is not limited thereto.
The substrate 1 may be a sapphire substrate, a silicon substrate, or a silicon carbide substrate, but is not limited thereto.
The nucleation layer 2 may be, but not limited to, an AlN layer and/or an AlGaN layer. Preferably, the nucleation layer 2 is an AlN layer, which can be used to provide seed crystals, relieve lattice mismatch between the substrate and the epitaxial layer, and improve the lattice quality of the epitaxial wafer. Specifically, the thickness of the nucleation layer 2 is 20 to 100nm, and exemplary is 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 60nm, 75nm, or 95nm, but is not limited thereto.
The thickness of the intrinsic GaN layer 3 is 300-800nm, such as 320nm, 400nm, 520nm, 650nm, 700nm, 750nm or 780nm, but not limited thereto.
The doping element of the N-GaN layer 4 is Si, but not limited thereto. The doping concentration of the N-GaN layer 4 is 5X 10 18 -1×10 19 cm -3 The thickness is 1-3 μm.
The multiple quantum well layer 6 is a periodic structure formed by a plurality of InGaN well layers and a plurality of GaN barrier layers, and the period number of the multiple quantum well layer is 3-15. The thickness of the single InGaN well layer is 2-5nm, and the thickness of the single GaN barrier layer is 6-15nm.
Wherein the electron blocking layer 7 is a plurality of Al a Ga 1-a N layer and a plurality of In b Ga 1-b The N layers form a periodic structure, and the period number of the periodic structure is 3-15. Wherein, the value range of a is 0.05-0.2, and the value range of b is 0.1-0.5. The thickness of the electron blocking layer 7 is 20 to 100nm, and is illustratively 22nm, 35nm, 45nm, 75nm, or 90nm, but is not limited thereto.
The doping element in the P-GaN layer 8 is Mg, but not limited thereto. The doping concentration of Mg in the P-GaN layer 8 is 5 x 10 17 -1×10 20 cm -3 . Specifically, the thickness of the P-GaN layer 8 is 200-300nm. Exemplary are 215nm, 230nm, 245nm, 250nm or 285nm, but not limited thereto.
In conclusion, the composite buffer layer is grown before the multi-quantum well layer grows, so that the bottom layer stress can be effectively released, the mobility of electrons is reduced, the expansion capability of the electrons is improved, and the electron hole distribution of the multi-quantum well region is more balanced; and dislocation extension is effectively blocked, the lattice quality is improved, the bottom layer stress is released, the polarization effect of a multi-quantum well region can be relieved, non-radiative recombination is reduced, and the light emitting efficiency of the light emitting diode is improved. Due to the improvement of the electronic expansion capability and the improvement of the lattice quality, the antistatic capability of the light-emitting diode is greatly improved.
Correspondingly, referring to fig. 4, the present application also discloses a method for preparing an led epitaxial wafer, which is used for preparing the led epitaxial wafer, and includes the following steps:
s1: providing a substrate;
specifically, the substrate is a sapphire substrate, a silicon substrate, or a silicon carbide substrate, but is not limited thereto. A sapphire substrate is preferred.
Preferably, in one embodiment of the present invention, the substrate is annealed. Specifically, the substrate is loaded into MOCVD, the temperature of the reaction chamber is controlled to be 1000-1200 ℃, the pressure of the reaction chamber is controlled to be 200-600Torr, and the reaction temperature is controlled to be H 2 And (3) annealing the substrate at high temperature for 5-8min in the atmosphere. Through the annealing treatment, particles and oxides on the surface of the substrate can be effectively cleaned.
S2: growing a nuclear layer, an intrinsic GaN layer, an N-GaN layer, a buffer layer, a multi-quantum well layer, an electronic barrier layer and a P-GaN layer on a substrate in sequence;
specifically, step S2 includes:
s21: growing a nucleation layer on the substrate;
preferably, in one embodiment of the invention, the substrate is loaded into MOCVD, the temperature of the reaction chamber is controlled to be 500-700 ℃, the pressure of the reaction chamber is controlled to be 200-400Torr, and N is introduced 2 And H 2 As carrier gas, introducing NH 3 As an N source, TMGa was used as a Ga source, TMAl was used as an Al source, and AlGaN was grown as a nucleation layer.
S22: growing an intrinsic GaN layer on the nucleation layer;
preferably, in one embodiment of the present invention, the epitaxial wafer obtained in S21 is loaded into MOCVD, the reaction chamber is controlled at 1100-1150 deg.C and the pressure in the reaction chamber is controlled at 100-500Torr, and N is introduced into the reaction chamber 2 And H 2 As carrier gas, introducing TMGa as Ga source and NH 3 And as an N source, growing to obtain an intrinsic GaN layer.
S23: growing an N-GaN layer on the intrinsic GaN layer;
preferably, in one embodiment of the present invention, the epitaxial wafer obtained in S22 is loaded into MOCVD, the temperature of the reaction chamber is controlled to 1100-1150 ℃, the pressure of the reaction chamber is controlled to 100-500Torr, and N is introduced 2 And H 2 As carrier gas, introducing TMGa as Ga source and NH 3 As a source of N, siH 4 And growing to obtain the N-GaN layer as a silicon source.
S24: growing a buffer layer on the N-GaN layer;
specifically, step S24 includes:
s241: growing an MgN three-dimensional induction layer on the N-GaN layer;
preferably, in one embodiment of the present invention, the epitaxial wafer obtained in S23 is loaded into MOCVD, the temperature of the reaction chamber is controlled to 750-900 ℃, the pressure of the reaction chamber is controlled to 300-500Torr, and H is introduced 2 And N 2 As carrier gas, introducing NH 3 As N source, cp 2 And (4) growing to obtain the MgN three-dimensional induction layer by taking Mg as an Mg source.
S242: growing a SiGaN three-dimensional layer on the MgN three-dimensional induction layer;
preferably, in one embodiment of the present invention, the epitaxial wafer obtained in S241 is loaded into MOCVD, the temperature of the reaction chamber is controlled to be 750-900 ℃, the pressure of the reaction chamber is controlled to be 300-500Torr, and H is introduced 2 And N 2 As carrier gas, introducing NH 3 As a source of N, siH 4 And (3) as a silicon source, TMGa is used as a Ga source, and the SiGaN three-dimensional layer is grown.
The SiGaN three-dimensional layer has lower growth temperature, so that stress release and warping relief are facilitated, and stress accumulation in a multi-quantum well region is avoided, so that electron and hole wave function separation of the multi-quantum well region is avoided, and the luminous efficiency of the light-emitting diode is influenced.
N entered in step S241 and step S242 2 And H 2 In a volume ratio of N 2 ：H 2 >2:1, preferably, N 2 And H 2 Is N 2 ：H 2 = (2-8): 1. simultaneously, the growth temperature of the step S241 and the step S242 is 750-900 ℃, and N is controlled to be introduced 2 And H 2 The volume and the growth temperature of the MgN three-dimensional layer are more beneficial to growing the SiGaN three-dimensional layer with a three-dimensional structure on the MgN three-dimensional inducing layer.
S243: growing a filling and leveling layer on the SiGaN three-dimensional layer;
wherein the filling layer is Al z Ga 1-z And N layers.
Preferably, in one embodiment of the present invention, the epitaxial wafer obtained in step S242 is loaded into MOCVD, and the temperature of the reaction chamber is controlled to 950 ℃ -1At 000 deg.C, the pressure in the reaction chamber is 150-300Torr, and N is introduced 2 And H 2 As carrier gas, introducing NH 3 Growing Al with TMGa as Ga source and TMAl as Al source as N source z Ga 1-z And N layers.
Wherein N is introduced in the step 2 And H 2 In a volume ratio of N 2 ：H 2 < 1:2, preferably, N is introduced 2 And H 2 Is N 2 ：H 2 =1: (2-8) by controlling the introduction of N 2 And H 2 The flow rate is more beneficial to obtaining the epitaxial layer with better lattice quality.
S25: growing a multi-quantum well layer on the buffer layer;
preferably, in one embodiment of the present invention, the epitaxial wafer obtained in S243 is loaded into MOCVD, the temperature of the reaction chamber is controlled to 700-800 ℃, the pressure of the reaction chamber is controlled to 100-500Torr, and N is introduced 2 As carrier gas, NH is introduced 3 As an N source, TEGa is used as a Ga source, TMIn is used as an In source, and an InGaN well layer is grown; then the temperature of the reaction chamber is increased to 800-900 ℃, TMIn is closed, and H is introduced 2 And N 2 Carrying gas to grow a GaN barrier layer; this was repeated for 3 to 15 cycles to form a multiple quantum well layer.
S26: growing an electron barrier layer on the multi-quantum well layer;
preferably, in one embodiment of the present invention, the epitaxial wafer obtained in S25 is loaded into MOCVD, the temperature of the reaction chamber is controlled to 900-1000 ℃, the pressure of the reaction chamber is controlled to 100-500Torr, and NH is introduced 3 As an N source, TMGa as Ga source and TMAl as Al source to grow Al a Ga 1-a And N layers. Then closing the Al source, continuously introducing the Ga source, introducing TMIn as an In source to grow In b Ga 1-b And repeating the N layers for 3-15 periods to form the electron blocking layer.
S27: growing a P-GaN layer on the electron blocking layer;
preferably, in one embodiment of the present invention, the epitaxial wafer obtained in S26 is loaded into MOCVD, the temperature of the reaction chamber is controlled to 800-1000 ℃, the pressure of the reaction chamber is controlled to 100-300Torr, and NH is introduced 3 As N source, TMGa as Ga source, cp 2 And Mg is used as a P-type dopant to grow a P-GaN layer.
Preferably, in an embodiment of the present invention, the step S241 includes:
s241a: growing a BN layer on the N-GaN layer;
it should be noted that this step uses only pure H 2 As a carrier gas, the BN layer grown is smoother and more compact, and the barrier effect on the graphene layer is strong.
Preferably, in one embodiment of the present invention, the epitaxial wafer obtained in S23 is loaded into MOCVD, the temperature of the reaction chamber is controlled to 1000-1050 ℃, the pressure of the reaction chamber is controlled to 50-150Torr, and H is introduced 2 As carrier gas, without introducing N 2 Introduction of NH 3 And as an N source, TMB is used as a B source, and a BN layer is grown.
S241b: growing a MgN three-dimensional induction layer on the BN layer;
preferably, in one embodiment of the present invention, the epitaxial wafer obtained in S241a is loaded into MOCVD, the temperature of the reaction chamber is controlled to be 750-900 ℃, the pressure of the reaction chamber is controlled to be 300-500Torr, and H is introduced 2 And N 2 As carrier gas, introducing NH 3 As N source, cp 2 And growing the Mg serving as an Mg source to obtain the MgN three-dimensional inducing layer.
Preferably, in an embodiment of the present invention, the step S241 includes:
s241a: growing a BN layer on the N-GaN layer;
wherein this step uses only pure H 2 As a carrier gas, the BN layer grown is smoother and more compact, and the barrier effect on the graphene layer is strong.
Preferably, in one embodiment of the present invention, the epitaxial wafer obtained in S23 is loaded into MOCVD, the temperature of the reaction chamber is controlled to 1000-1050 ℃, the pressure of the reaction chamber is controlled to 50-150Torr, and H is introduced 2 As carrier gas, without introducing N 2 Introduction of NH 3 And as an N source, TMB is used as a B source, and a BN layer is grown.
S241b: growing a graphene layer on the BN layer;
preferably, in one embodiment of the present invention, the epitaxial wafer obtained in step S241a is loaded into CVD, and the temperature of the reaction chamber is controlled to be 800-1The pressure of the reaction chamber is 7.5 to 375Torr at 000 ℃, and H is introduced 2 And Ar as carrier gas, introducing CH of 200-1000sccm 4 And as a C source, growing to obtain the graphene layer.
S241c: growing a MgN three-dimensional inducing layer on the graphene layer;
preferably, in one embodiment of the present invention, the epitaxial wafer obtained in step S241b is loaded into MOCVD, the temperature of the reaction chamber is controlled to be 750 to 900 ℃, the pressure of the reaction chamber is controlled to be 300to 500Torr, and H is introduced 2 And N 2 As carrier gas, introducing NH 3 As N source, cp 2 And growing the Mg serving as an Mg source to obtain the MgN three-dimensional inducing layer.
The invention is further illustrated by the following specific examples:
example 1
The embodiment provides a light emitting diode epitaxial wafer, and referring to fig. 1, the light emitting diode epitaxial wafer comprises a substrate 1, and a nucleation layer 2, an intrinsic GaN layer 3, an N-GaN layer 4, a buffer layer 5, a multi-quantum well layer 6, an electron blocking layer 7 and a P-GaN layer 8 which are sequentially arranged on the substrate 1.
The substrate 1 is a sapphire substrate, the nucleation layer 2 is an AlGaN layer with the thickness of 30nm, and the intrinsic GaN layer 3 is 400nm. The doping concentration of Si in the N-GaN layer 4 was 8.5X 10 18 cm -3 The thickness thereof was 2 μm.
The buffer layer 5 comprises a MgN three-dimensional inducing layer 51, a SiGaN three-dimensional layer 52 and a filling layer 53 which are sequentially arranged on the N-GaN layer 4. The MgN three-dimensional inducing layer 51 is Mg x N 1-x Layer, x is 0.2; the filling layer 53 is Al z Ga 1-z N layer, z is 0.05.
Wherein, the thickness of the MgN three-dimensional inducing layer 51 is 4nm; the thickness of the three-dimensional layer 52 of SiGaN was 30nm, and the doping concentration of Si in the three-dimensional layer of SiGaN was 2.5X 10 16 cm -3 (ii) a The thickness of the fill-level layer 53 was 40nm.
The multiple quantum well layer 6 is a periodic superlattice structure formed by alternately laminating InGaN well layers and GaN barrier layers, and the period number of the periodic superlattice structure is 10. The thickness of the single InGaN well layer is 3nm, and the thickness of the single GaN barrier layer is 10nm.
Wherein the electron blocking layer 7 is Al a Ga 1-a N layer and In b Ga 1-b N layers are alternately stacked to form a periodic superlattice structure, and the period number is 8. Wherein a is 0.1 and b is 0.35. Single Al a Ga 1-a The thickness of the N layer was 6nm, single In b Ga 1-b The thickness of the N layer was 6nm, and the total thickness of the electron blocking layer 7 was 74nm.
Wherein the doping concentration of Mg in the P-GaN layer 8 is 6.5 multiplied by 10 18 cm -3 And the thickness is 4nm.
The preparation method of the light emitting diode epitaxial wafer in the embodiment comprises the following steps:
(1) Providing a substrate;
specifically, the substrate was loaded into MOCVD, the temperature of the reaction chamber was controlled at 1100 ℃, the pressure of the reaction chamber was controlled at 450Torr, and the substrate was subjected to high-temperature annealing for 8min under an H2 atmosphere.
(2) Growing a nucleation layer on the substrate;
specifically, the temperature of the reaction chamber is controlled to be 550 ℃, the pressure of the reaction chamber is controlled to be 250Torr, and N is introduced 2 And H 2 As carrier gas, introducing NH 3 As an N source, TMGa was used as a Ga source, TMAl was used as an Al source, and AlGaN was grown as a nucleation layer.
(3) Growing an intrinsic GaN layer on the nucleation layer;
specifically, the reaction chamber was controlled at 1150 ℃ and the pressure in the reaction chamber was controlled at 400Torr, and N was introduced 2 And H 2 As carrier gas, introducing TMGa as Ga source and NH 3 And as an N source, growing to obtain an intrinsic GaN layer.
(4) Growing an N-GaN layer on the intrinsic GaN layer;
specifically, the temperature of the reaction chamber is controlled to be 1140 ℃, the pressure of the reaction chamber is controlled to be 400Torr, and N is introduced 2 And H 2 As carrier gas, introducing TMGa as Ga source and NH 3 As a source of N, siH 4 And growing to obtain the N-GaN layer as a silicon source.
(5) Growing a MgN three-dimensional inducing layer on the N-GaN layer;
specifically, the temperature of the reaction chamber is controlled at 800 ℃, the pressure of the reaction chamber is controlled at 400Torr, and H is introduced 2 And N 2 As carrier gas, introducing NH 3 As N source, cp 2 And growing the Mg serving as an Mg source to obtain the MgN three-dimensional inducing layer.
Wherein N is introduced 2 And H 2 In a volume ratio of N 2 ：H 2 =3：1。
(6) Growing a SiGaN three-dimensional layer on the MgN three-dimensional inducing layer;
specifically, the temperature of the reaction chamber was controlled to 850 ℃ and the pressure in the reaction chamber was controlled to 350Torr, and H was introduced thereinto 2 And N 2 As carrier gas, introducing NH 3 As a source of N, siH 4 And (3) as a silicon source, and growing to obtain the SiGaN three-dimensional layer by taking TMGa as a Ga source.
Wherein N is introduced 2 And H 2 In a volume ratio of N 2 ：H 2 =3：1。
(7) Growing Al on SiGaN three-dimensional layer z Ga 1-z N layers;
specifically, the temperature of the reaction chamber is controlled to be 960 ℃, the pressure of the reaction chamber is controlled to be 200Torr, and N is introduced 2 And H 2 As carrier gas, introducing NH 3 Growing Al with TMGa as Ga source and TMAl as Al source as N source z Ga 1-z And N layers.
Wherein N is introduced 2 And H 2 In a volume ratio of N 2 ：H 2 =1：3。
(8) Growing a multi-quantum well layer on the buffer layer;
specifically, the temperature of the reaction chamber is controlled at 750 ℃, the pressure of the reaction chamber is controlled at 300Torr, and N is introduced 2 As carrier gas, NH is introduced 3 As an N source, TEGa is used as a Ga source, TMIn is used as an In source, and an InGaN well layer is grown; the temperature of the reaction chamber is then raised to 850 ℃, TMIn is switched off and H is passed in 2 And N 2 Carrying gas to grow a GaN barrier layer; this was repeated for 10 cycles to form a multiquantum well layer.
(9) Growing an electron barrier layer on the multi-quantum well layer;
specifically, the temperature of the reaction chamber is controlled to be 950 ℃, the pressure of the reaction chamber is controlled to be 300Torr, NH3 is introduced to be used as an N source, TMGa is used as a Ga source, TMAl is used as an Al source, and Al is grown a Ga 1-a And N layers. Then closing the Al source, continuously introducing the Ga source, introducing TMIn as an In source to grow In b Ga 1-b N layers, repeating the above steps for 8 periods to form an electron barrierAnd (3) a layer.
(10) Growing a P-GaN layer on the electron blocking layer;
specifically, the temperature of the reaction chamber is controlled to be 900 ℃, the pressure of the reaction chamber is controlled to be 250Torr, and NH is introduced 3 As an N source, TMGa as a Ga source and CP2Mg as a P-type dopant, a P-GaN layer was grown.
Example 2
The embodiment provides a light emitting diode epitaxial wafer, and referring to fig. 2, the light emitting diode epitaxial wafer comprises a substrate 1, and a nucleation layer 2, an intrinsic GaN layer 3, an N-GaN layer 4, a buffer layer 5, a multi-quantum well layer 6, an electron blocking layer 7 and a P-GaN layer 8 which are sequentially arranged on the substrate 1.
The substrate 1 is a sapphire substrate, the nucleation layer 2 is an AlGaN layer with the thickness of 30nm, and the intrinsic GaN layer 3 is 400nm. The doping concentration of Si in the N-GaN layer 4 was 8.5X 10 18 cm -3 The thickness was 2 μm.
The buffer layer 5 comprises a BN layer 54, a MgN three-dimensional inducing layer 51, a SiGaN three-dimensional layer 52 and a filling layer 53 which are sequentially arranged on the N-GaN layer 4. BN layer 54 is B y N 1-y Layer, y is 0.3; the MgN three-dimensional inducing layer 51 is Mg x N 1-x Layer, x is 0.2; the filling layer 53 is Al z Ga 1-z N layer, z is 0.05.
Wherein the thickness of the BN layer 54 is 15nm; the thickness of the MgN three-dimensional inducing layer 51 is 4nm; the thickness of the three-dimensional layer 52 of SiGaN was 30nm, and the doping concentration of Si in the three-dimensional layer of SiGaN was 2.5X 10 16 cm -3 (ii) a The thickness of the fill-level layer 53 was 40nm.
The multiple quantum well layer 6 is a periodic superlattice structure formed by alternately laminating InGaN well layers and GaN barrier layers, and the period number of the periodic superlattice structure is 10. The thickness of the single InGaN well layer is 3nm, and the thickness of the single GaN barrier layer is 10nm.
Wherein the electron blocking layer 7 is Al a Ga 1-a N layer and In b Ga 1-b N layers are alternately stacked to form a periodic superlattice structure, and the period number is 8. Wherein a is 0.1 and b is 0.35. Single Al a Ga 1-a The thickness of the N layer was 6nm, single In b Ga 1-b The thickness of the N layer was 6nm and the total thickness of the electron blocking layer 7 was 96nm.
Wherein the doping concentration of Mg in the P-GaN layer 8 is 6.5 multiplied by 10 18 cm -3 And the thickness is 4nm.
The preparation method of the light emitting diode epitaxial wafer in the embodiment comprises the following steps:
(1) Providing a substrate;
specifically, the substrate was loaded into MOCVD, the temperature of the reaction chamber was controlled at 1100 ℃, the pressure of the reaction chamber was controlled at 450Torr, and the substrate was subjected to high-temperature annealing for 8min under an H2 atmosphere.
(2) Growing a nucleation layer on a substrate;
specifically, the temperature of the reaction chamber is controlled to be 550 ℃, the pressure of the reaction chamber is controlled to be 250Torr, and N is introduced 2 And H 2 As carrier gas, introducing NH 3 As an N source, TMGa was used as a Ga source, TMAl was used as an Al source, and AlGaN was grown as a nucleation layer.
(3) Growing an intrinsic GaN layer on the nucleation layer;
specifically, the reaction chamber was controlled at 1150 ℃ and the pressure in the reaction chamber was controlled at 400Torr, and N was introduced 2 And H 2 As carrier gas, introducing TMGa as Ga source and NH 3 And as an N source, growing to obtain an intrinsic GaN layer.
(4) Growing an N-GaN layer on the intrinsic GaN layer;
specifically, the temperature of the reaction chamber is controlled to be 1140 ℃, the pressure of the reaction chamber is controlled to be 400Torr, and N is introduced 2 And H 2 As carrier gas, introducing TMGa as Ga source and NH 3 As a source of N, siH 4 And as a silicon source, growing to obtain an N-GaN layer.
(5) Growing a BN layer on the N-GaN layer;
specifically, the temperature of the reaction chamber was controlled to 1020 ℃ and the pressure in the reaction chamber was controlled to 80Torr, and H was introduced thereinto 2 As carrier gas, introducing NH 3 And as an N source, TMB is used as a B source, and a BN layer is grown.
(6) Growing an MgN three-dimensional inducing layer on the BN layer;
specifically, the temperature of the reaction chamber was controlled at 800 ℃ and the pressure in the reaction chamber was controlled at 400Torr, and H was introduced thereinto 2 And N 2 As carrier gas, introducing NH 3 As N source, cp 2 And (4) growing to obtain the MgN three-dimensional induction layer by taking Mg as an Mg source.
Wherein N is introduced 2 And H 2 In a volume ratio of N 2 ：H 2 =3：1。
(7) Growing a SiGaN three-dimensional layer on the MgN three-dimensional inducing layer;
specifically, the temperature of the reaction chamber was controlled to 850 ℃ and the pressure in the reaction chamber was controlled to 350Torr, and H was introduced thereinto 2 And N 2 As carrier gas, introducing NH 3 As a source of N, siH 4 And (3) as a silicon source, and growing to obtain the SiGaN three-dimensional layer by taking TMGa as a Ga source.
Wherein N is introduced 2 And H 2 Is N 2 ：H 2 =3：1。
(8) Growing Al on SiGaN three-dimensional layer z Ga 1-z N layers;
specifically, the temperature of the reaction chamber is controlled to be 960 ℃, the pressure of the reaction chamber is controlled to be 200Torr, and N is introduced 2 And H 2 As carrier gas, introducing NH 3 Growing Al with TMGa as Ga source and TMAl as Al source as N source z Ga 1-z And N layers.
Wherein N is introduced 2 And H 2 In a volume ratio of N 2 ：H 2 =1：3。
(9) Growing a multi-quantum well layer on the buffer layer;
specifically, the temperature of the reaction chamber is controlled to be 750 ℃, the pressure of the reaction chamber is controlled to be 300Torr, and N is introduced 2 As carrier gas, NH is introduced 3 As an N source, TEGa is used as a Ga source, TMIn is used as an In source, and an InGaN well layer is grown; the temperature of the reaction chamber is then raised to 850 ℃, TMIn is switched off and H is passed in 2 And N 2 Carrying gas to grow a GaN barrier layer; this was repeated for 10 cycles to form a multiple quantum well layer.
(10) Growing an electron barrier layer on the multi-quantum well layer;
specifically, the temperature of the reaction chamber is controlled to be 950 ℃, the pressure of the reaction chamber is controlled to be 300Torr, NH3 is introduced to be used as an N source, TMGa is used as a Ga source, TMAl is used as an Al source, and Al is grown a Ga 1-a And N layers. Then closing the Al source, continuously introducing the Ga source, introducing TMIn as an In source to grow In b Ga 1-b And repeating the N layers for 8 periods to form an electron blocking layer.
(11) Growing a P-GaN layer on the electron blocking layer;
specifically, the temperature of the reaction chamber is controlled to be 900 ℃, the pressure of the reaction chamber is controlled to be 250Torr, and NH is introduced 3 As N source, TMGa as Ga source, cp 2 And Mg is used as a P-type dopant to grow a P-GaN layer.
Example 3
The embodiment provides a light emitting diode epitaxial wafer, and referring to fig. 3, the light emitting diode epitaxial wafer comprises a substrate 1, and a nucleation layer 2, an intrinsic GaN layer 3, an N-GaN layer 4, a buffer layer 5, a multi-quantum well layer 6, an electron blocking layer 7 and a P-GaN layer 8 which are sequentially arranged on the substrate 1.
The substrate 1 is a sapphire substrate, the nucleation layer 2 is an AlGaN layer with the thickness of 30nm, and the intrinsic GaN layer 3 is 400nm. The doping concentration of Si in the N-GaN layer 4 was 8.5X 10 18 cm -3 The thickness was 2 μm.
The buffer layer 5 comprises a BN layer 54, a graphene layer 55, an MgN three-dimensional induction layer 51, an SiGaN three-dimensional layer 52 and a filling layer 53 which are sequentially arranged on the N-GaN layer 4. BN layer 54 is B y N 1-y Layer, y is 0.3; the MgN three-dimensional inducing layer 51 is Mg x N 1-x Layer, x is 0.2; the filling layer 53 is Al z Ga 1-z N layer, z is 0.05.
Wherein the thickness of the BN layer 54 is 15nm; the thickness of the graphene layer 55 is 25nm; the thickness of the MgN three-dimensional inducing layer 51 is 4nm; the thickness of the three-dimensional layer 52 of SiGaN was 30nm, and the doping concentration of Si in the three-dimensional layer of SiGaN was 2.5X 10 16 cm -3 (ii) a The thickness of the fill-level layer 53 was 40nm.
The multiple quantum well layer 6 is a periodic superlattice structure formed by alternately laminating InGaN well layers and GaN barrier layers, and the period number of the periodic superlattice structure is 10. The thickness of the single InGaN well layer is 3nm, and the thickness of the single GaN barrier layer is 10nm.
Wherein the electron blocking layer 7 is Al a Ga 1-a N layer and In b Ga 1-b N layers are alternately stacked to form a periodic superlattice structure, and the period number is 8. Wherein a is 0.1 and b is 0.35. Single Al a Ga 1-a The thickness of the N layer was 6nm, single In b Ga 1-b The thickness of the N layer is 6nm and the total thickness of the electron blocking layer 7The degree was 96nm.
Wherein the doping concentration of Mg in the P-GaN layer 8 is 6.5 multiplied by 10 18 cm -3 And the thickness is 4nm.
The preparation method of the light emitting diode epitaxial wafer in the embodiment comprises the following steps:
(1) Providing a substrate;
specifically, the substrate was loaded into MOCVD, the temperature of the reaction chamber was controlled at 1100 ℃, the pressure of the reaction chamber was controlled at 450Torr, and the substrate was subjected to high-temperature annealing for 8min under an H2 atmosphere.
(2) Growing a nucleation layer on the substrate;
specifically, the temperature of the reaction chamber is controlled to be 550 ℃, the pressure of the reaction chamber is controlled to be 250Torr, and N is introduced 2 And H 2 As carrier gas, introducing NH 3 As an N source, TMGa was used as a Ga source, TMAl was used as an Al source, and AlGaN was grown as a nucleation layer.
(3) Growing an intrinsic GaN layer on the nucleation layer;
specifically, the reaction chamber was controlled at 1150 ℃ and a pressure of 400Torr, and N was introduced into the reaction chamber 2 And H 2 As carrier gas, introducing TMGa as Ga source and NH 3 And as an N source, growing to obtain an intrinsic GaN layer.
(4) Growing an N-GaN layer on the intrinsic GaN layer;
specifically, the temperature of the reaction chamber is controlled to be 1140 ℃, the pressure of the reaction chamber is controlled to be 400Torr, and N is introduced 2 And H 2 As carrier gas, introducing TMGa as Ga source and NH 3 As a source of N, siH 4 And growing to obtain the N-GaN layer as a silicon source.
(5) Growing a BN layer on the N-GaN layer;
specifically, the temperature of the reaction chamber was controlled to 1020 ℃ and the pressure in the reaction chamber was controlled to 80Torr, and H was introduced thereinto 2 As carrier gas, introducing NH 3 And (4) as an N source, TMB as a B source, and growing to obtain the BN layer.
(6) Growing a graphene layer on the BN layer;
specifically, the epitaxial wafer obtained in the step (5) is loaded into CVD, the temperature of a reaction chamber is controlled to be 900 ℃, the pressure of the reaction chamber is controlled to be 100Torr, and H is introduced 2 And Ar as carrier gas, into which CH of 800sccm is introduced 4 As C source, growing to obtain graphiteAn alkene layer.
(7) Growing a MgN three-dimensional inducing layer on the graphene layer;
specifically, the epitaxial wafer obtained in the step (6) is loaded into MOCVD, the temperature of a reaction chamber is controlled to be 800 ℃, the pressure of the reaction chamber is controlled to be 400Torr, and H is introduced 2 And N 2 As carrier gas, introducing NH 3 As N source, cp 2 And growing the Mg serving as an Mg source to obtain the MgN three-dimensional inducing layer.
Wherein N is introduced 2 And H 2 In a volume ratio of N 2 ：H 2 =3：1。
(8) Growing a SiGaN three-dimensional layer on the MgN three-dimensional inducing layer;
specifically, the temperature of the reaction chamber is controlled to be 850 ℃, the pressure of the reaction chamber is controlled to be 350Torr, and H is introduced 2 And N 2 As carrier gas, introducing NH 3 As a source of N, siH 4 And (3) as a silicon source, and growing to obtain the SiGaN three-dimensional layer by taking TMGa as a Ga source.
Wherein N is introduced 2 And H 2 In a volume ratio of N 2 ：H 2 =3：1。
(9) Growing Al on SiGaN three-dimensional layer z Ga 1-z N layers;
specifically, the temperature of the reaction chamber is controlled to be 960 ℃, the pressure of the reaction chamber is controlled to be 200Torr, and N is introduced 2 And H 2 As carrier gas, introducing NH 3 Growing Al with TMGa as Ga source and TMAl as Al source as N source z Ga 1-z And N layers.
Wherein N is introduced 2 And H 2 In a volume ratio of N 2 ：H 2 =1：3。
(10) Growing a multi-quantum well layer on the buffer layer;
specifically, the temperature of the reaction chamber is controlled at 750 ℃, the pressure of the reaction chamber is controlled at 300Torr, and N is introduced 2 As carrier gas, NH is introduced 3 As an N source, TEGa is used as a Ga source, TMIn is used as an In source, and an InGaN well layer is grown; the temperature of the reaction chamber is then raised to 850 ℃, TMIn is switched off and H is passed in 2 And N 2 Carrying gas to grow a GaN barrier layer; this was repeated for 10 cycles to form a multiple quantum well layer.
(11) Growing an electron barrier layer on the multi-quantum well layer;
specifically, the temperature of the reaction chamber is controlled to be 950 ℃, the pressure of the reaction chamber is controlled to be 300Torr, NH3 is introduced to be used as an N source, TMGa is used as a Ga source, TMAl is used as an Al source, and Al is grown a Ga 1-a And N layers. Then closing the Al source, continuously introducing the Ga source, introducing TMIn serving as an In source to grow In b Ga 1-b And repeating the N layers for 8 periods to form an electron blocking layer.
(12) Growing a P-GaN layer on the electron blocking layer;
specifically, the temperature of the reaction chamber is controlled to be 900 ℃, the pressure of the reaction chamber is controlled to be 250Torr, and NH is introduced 3 As N source, TMGa as Ga source, cp 2 And Mg is used as a P-type dopant to grow a P-GaN layer.
Comparative example 1
This comparative example is different from example 1 in that a stress relaxation layer is provided between the N-GaN layer and the multiple quantum well layer, and the stress relaxation layer is an InGaN layer.
Correspondingly, the method of the stress release layer is as follows: controlling the temperature of the reaction chamber to be 800 ℃, the pressure of the reaction chamber to be 250Torr, and introducing N 2 And H 2 As carrier gas, introducing NH 3 As an N source, TMGa as a Ga source and TMIn as an In source, an InGaN layer was grown.
Processing the light-emitting diode epitaxial wafers obtained in the embodiments 1-3 and the comparative example 1 into a 10X 24mil LED chip with a vertical structure, and testing the antistatic ability and the light-emitting brightness of the LED chip;
the specific test method of the chip comprises the following steps:
(1) Brightness: testing the luminous intensity of the obtained chip when the current of 120mA is introduced;
(2) And (3) testing the antistatic property: the antistatic performance of the base chip is tested by using an electrostatic instrument under an HBM (human body discharge model) model, and the test chip can bear the reverse 6000V electrostatic passing proportion.
The specific test results are as follows:
it can be seen from the table that, when the buffer layer is introduced into the epitaxial structure, the light-emitting efficiency and the antistatic capability of the epitaxial wafer are effectively improved.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A light emitting diode epitaxial wafer comprises a substrate, and a nucleation layer, an intrinsic GaN layer, an N-GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-GaN layer which are sequentially arranged on the substrate; the buffer layer is arranged between the N-GaN layer and the multi-quantum well layer and comprises an MgN three-dimensional induction layer, an SiGaN three-dimensional layer and a filling layer which are sequentially arranged on the N-GaN layer.
2. The light emitting diode epitaxial wafer of claim 1, wherein the MgN three-dimensional inducing layer is Mg x N 1-x A layer, wherein x has a value in the range of 0.1-0.3;
the doping concentration of Si in the SiGaN three-dimensional layer is 1 multiplied by 10 16 -1×10 18 cm -3 ；
The doping concentration of Si in the SiGaN three-dimensional layer is less than that of Si in the N-GaN layer.
3. The light-emitting diode epitaxial wafer according to claim 1 or 2, wherein the thickness of the MgN three-dimensional induction layer is 2 to 5nm;
the thickness of the SiGaN three-dimensional layer is 20-50nm, and the diameter of the SiGaN three-dimensional layer is 10-30nm;
the thickness of the filling and leveling layer is 20-50nm;
the thickness of the filling and leveling layer is larger than that of the SiGaN three-dimensional layer.
4. The light-emitting diode epitaxial wafer according to claim 1, wherein a BN layer is provided between the N-GaN layer and the MgN three-dimensional inducing layer;
the BN layer is B y N 1-y A layer, wherein y ranges from 0.2 to 0.4;
the thickness of the BN layer is 10-20nm;
a graphene layer is arranged between the BN layer and the MgN three-dimensional induction layer;
the thickness of the graphene layer is 20-30nm;
the filling and leveling layer is an AlGaN layer.
5. A method for preparing a light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer as claimed in any one of claims 1 to 4, and comprises the following steps:
(1) Providing a substrate;
(2) Growing a nuclear layer, an intrinsic GaN layer, an N-GaN layer, a buffer layer, a multi-quantum well layer, an electronic barrier layer and a P-GaN layer on the substrate in sequence;
the buffer layer comprises a MgN three-dimensional inducing layer, a SiGaN three-dimensional layer and a filling layer which are sequentially arranged on the N-GaN layer.
6. The method for preparing a light emitting diode epitaxial wafer according to claim 5, wherein the growth temperature of the MgN three-dimensional inducing layer and the SiGaN three-dimensional layer is 750-900 ℃, and the growth pressure is 300-500Torr;
the growth temperature of the filling and leveling layer is 950-1000 ℃, and the growth pressure is 150-300Torr.
7. The method for preparing an epitaxial wafer of a light emitting diode according to claim 5, wherein the growth carrier gases of the MgN three-dimensional induction layer and the SiGaN three-dimensional layer are hydrogen and nitrogen, wherein the volume ratio of the nitrogen to the hydrogen is N 2 ：H 2 >2：1；
The growth carrier gas of the filling layer is hydrogen and nitrogen, wherein the volume ratio of the nitrogen to the hydrogen is N 2 ：H 2 ＜1：2。
8. The method for preparing the light-emitting diode epitaxial wafer as claimed in claim 5, wherein the buffer layer comprises a BN layer, a MgN three-dimensional inducing layer, a SiGaN three-dimensional layer and a filling layer which are sequentially arranged on the N-GaN layer;
the growth temperature of the BN layer is 1000-1050 ℃, the growth pressure is 50-150Torr, and the growth carrier gas is hydrogen.
9. The method for preparing the light-emitting diode epitaxial wafer as claimed in claim 5, wherein the buffer layer comprises a BN layer, a graphene layer, a MgN three-dimensional inducing layer, a SiGaN three-dimensional layer and a filling layer which are sequentially arranged on the N-GaN layer;
the growth temperature of the graphene layer is 800-1000 ℃, the growth pressure is 7.5-375Torr, and the growth carrier gas is hydrogen or/and argon.
10. A light emitting diode comprising the light emitting diode epitaxial wafer of any one of claims 1~4.
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