CN115810609B - Fuse trimming structure, manufacturing method thereof and integrated circuit - Google Patents
Fuse trimming structure, manufacturing method thereof and integrated circuit Download PDFInfo
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- CN115810609B CN115810609B CN202211569477.2A CN202211569477A CN115810609B CN 115810609 B CN115810609 B CN 115810609B CN 202211569477 A CN202211569477 A CN 202211569477A CN 115810609 B CN115810609 B CN 115810609B
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- 238000009966 trimming Methods 0.000 title claims abstract 17
- 238000004519 manufacturing process Methods 0.000 title claims 3
- 239000000758 substrate Substances 0.000 claims abstract 28
- 238000002360 preparation method Methods 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims 3
- 238000005137 deposition process Methods 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 claims 1
- 238000001259 photo etching Methods 0.000 claims 1
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Abstract
The application discloses a fuse trimming structure, a preparation method thereof and an integrated circuit, and relates to the technical field of integrated circuit chip trimming. The fuse trimming structure comprises an N-type substrate, a first insulating layer positioned on the N-type substrate, a fuse layer positioned on the first insulating layer and a second insulating layer positioned on the fuse layer; the fuse layer is provided with a first bonding pad and a second bonding pad which are arranged at intervals, and the second insulating layer is provided with a first window exposing the first bonding pad and a second window exposing the second bonding pad; the fuse trimming structure further comprises a P-type region located between the first insulating layer and the N-type substrate, and the P-type region and the N-type substrate jointly form a PN junction conducted along the direction of the second insulating layer towards the first insulating layer. The fuse trimming structure can solve the problem that the first insulating layer is damaged easily when the fuse is blown, so that leakage current generated by the fuse trimming structure can be avoided, and the reliability of the IC can be improved.
Description
Technical Field
The application relates to the technical field of integrated circuit chip trimming, in particular to a fuse trimming structure, a manufacturing method thereof and an integrated circuit.
Background
Along with the increasing requirement of high performance indexes of integrated circuits, the requirement of high precision is increasingly obvious for chip design, especially for high-precision high-speed digital-to-analog converters, analog-to-digital converters, reference source circuits and the like, the capacitance and resistance values of chips produced by a process factory have certain process errors due to unavoidable factors such as process errors and the like, and the errors can directly influence the performance indexes of the circuits. In order to solve the problem of the process errors, the correction technology is required to be used for correction before the chip is normally used, so that the circuit parameters are more accurate and have better consistency.
Fuse Trimming (Fuse Trimming) is a method of changing the state of a circuit by applying a voltage to blow a wire (typically a Fuse) in the circuit when a large current passes through the circuit. At present, fuse trimming technology is widely applied to integrated circuits, and is commonly used for improving circuit precision, changing frequency, adjusting resistance and other parameter settings before delivery, so as to achieve the purposes of changing circuit characteristics and improving production yield. The conventional fuse trimming structure generally uses a voltage source (or a current source) to blow a fuse, so as to change the state of a circuit to achieve the trimming purpose. Because the manufacturing process fluctuates and the blowing current cannot be controlled accurately, a larger blowing current is generally used to ensure that the fuse is completely blown. However, the introduction of a large current has the unavoidable negative effect that the introduction of a large current causes the destruction of the insulating layer under the fuse while ensuring that the fuse is completely blown. And damage to the insulating layer will cause leakage current to occur between the VCC under the substrate through the substrate and the insulating layer and the two conductive terminals connected to the fuse pads. On one hand, the generation of leakage current will adversely affect the trimming accuracy; on the other hand, after long-term use, the fuse trimming structure generating leakage current will increase leakage current, and even cause IC failure in serious cases.
Disclosure of Invention
The application provides a fuse trimming structure, a preparation method thereof and an integrated circuit, which can solve the problem that a first insulating layer is easily damaged when a fuse is blown, so that leakage current generated by the fuse trimming structure can be avoided, and the reliability of an Integrated Circuit (IC) can be improved.
In order to solve the technical problems, the application adopts the following technical scheme:
the application provides a fuse trimming structure, which comprises an N-type substrate, a first insulating layer positioned on the N-type substrate, a fuse layer positioned on the first insulating layer and a second insulating layer positioned on the fuse layer, wherein the first insulating layer is arranged on the N-type substrate; the fuse layer is provided with a first bonding pad and a second bonding pad which are arranged at intervals, and the second insulating layer is provided with a first window exposing the first bonding pad and a second window exposing the second bonding pad; the fuse trimming structure further comprises a P-type region located between the first insulating layer and the N-type substrate, and the P-type region and the N-type substrate jointly form a PN junction conducted along the direction of the second insulating layer towards the first insulating layer. The fuse trimming structure can solve the problem that the first insulating layer is damaged easily when the fuse is blown, so that leakage current generated by the fuse trimming structure can be avoided, and the reliability of the IC can be improved.
In one possible embodiment, the orthographic projection width of the P-type region on the N-type substrate is greater than a first width, which is a distance between orthographic projections of the first pad and the second pad on the N-type substrate.
In one possible embodiment, the orthographic projection of the P-type region onto the N-type substrate coincides with the N-type substrate.
In one possible embodiment, the material of the fuse layer is polysilicon. Compared with the existing metal fuse, the polysilicon fuse can be blown under the action of relatively low blowing current, so that the fuse trimming structure adopting the polysilicon fuse is more suitable for being arranged at the internal position of the integrated circuit chip.
In one possible embodiment, the fuse layer includes a first portion and two second portions at opposite ends of the first portion, the two second portions corresponding to the first pad and the second pad, respectively; wherein the thickness of the first portion is less than the thickness of the second portion. The fuse wire layer is arranged in a mode of thin middle and thick two sides, so that on one hand, the fuse wire is easier to blow; on the other hand, the problem that the first insulating film is damaged by a large fusing current can be improved to some extent.
In one possible embodiment, the first insulating layer includes an insulating layer body and two insulating layer ends located at opposite ends of the insulating layer body, the two insulating layer ends corresponding to the first bonding pad and the second bonding pad, respectively; wherein, the thickness of the end parts of the two insulating layers is larger than that of the insulating layer main body. In this way, the possibility that the first insulating film is broken can be further reduced.
The application also provides a preparation method of the fuse trimming structure, which comprises the following steps: providing an N-type substrate; forming a P-type region on the N-type substrate, wherein the P-type region and the N-type substrate jointly form a PN junction; forming a first insulating layer on the P-type region, wherein the first insulating layer covers the P-type region; forming a fuse layer on the first insulating layer, wherein the fuse layer is provided with a first bonding pad and a second bonding pad which are spaced, and the fuse layer and the N-type substrate are electrically isolated through the first insulating layer; forming a second insulating layer on the fuse layer to cover the fuse layer; and opening a first window exposing the first bonding pad and a second window exposing the second bonding pad on the second insulating layer through a photoetching process. The fuse trimming structure prepared by the preparation method of the fuse trimming structure can solve the problem that the first insulating layer is easily damaged when the fuse is blown, so that leakage current generated by the fuse trimming structure can be avoided, and the reliability of an Integrated Circuit (IC) can be improved.
In one possible embodiment, forming a P-type region on an N-type substrate, the P-type region and the N-type substrate together forming a PN junction, comprises: and forming a P-type region in the N-type substrate through an ion implantation process, wherein the upper surface of the P-type region is flush with the upper surface of the N-type substrate, and the P-type region and the N-type substrate jointly form a PN junction.
In one possible embodiment, forming a P-type region on an N-type substrate, the P-type region and the N-type substrate together forming a PN junction, comprises: and forming a P-type region on the N-type substrate through a deposition process or a sputtering process, wherein the P-type region covers the upper surface of the N-type substrate, and the P-type region and the N-type substrate jointly form a PN junction.
The application also provides an integrated circuit which comprises the fuse trimming structure. The integrated circuit adopting the fuse trimming structure can avoid the influence on trimming precision caused by leakage current generated by the fuse trimming structure, and can improve the reliability of the IC.
The fuse trimming structure provided by the application has the beneficial effects that:
the application provides a fuse trimming structure which comprises an N-type substrate, a first insulating layer positioned on the N-type substrate, a fuse layer positioned on the first insulating layer and a second insulating layer positioned on the fuse layer, wherein the first insulating layer is arranged on the N-type substrate; the fuse layer is provided with a first bonding pad and a second bonding pad which are arranged at intervals, and the second insulating layer is provided with a first window exposing the first bonding pad and a second window exposing the second bonding pad; the fuse trimming structure further comprises a P-type region located between the first insulating layer and the N-type substrate, and the P-type region and the N-type substrate jointly form a PN junction conducted along the direction of the second insulating layer towards the first insulating layer. The P-type region is formed between the first insulating layer and the N-type substrate of the fuse trimming structure, so that the N-type substrate and the P-type region jointly construct the PN junction conducted along the second insulating layer towards the first insulating layer. In this way, even if a large blowing current is applied to the fuse layer in order to effectively blow the fuse layer, so that the first insulating layer under the fuse layer is damaged, the existence of the PN junction prevents the VCC of the N-type substrate from generating a leakage current in the direction of PAD or GND. By adopting the fuse trimming structure provided by the application, leakage current can be effectively reduced, and the reliability of the IC can be improved.
Drawings
The application is further described with reference to the accompanying drawings:
FIG. 1 is a schematic diagram of trimming principle provided by the fuse trimming structure of the present application;
FIG. 2 is a schematic diagram of a fuse trimming structure according to the present application;
FIG. 3 is a second schematic diagram of the fuse trimming structure according to the present application;
FIG. 4 is a schematic diagram of a fuse trimming structure according to the present application when a fuse layer is blown;
fig. 5 is a flow chart of a method for manufacturing a fuse trimming structure according to the present application.
Reference numerals: a 10-N type substrate; 20-a first insulating layer; 30-a fuse layer; 40-a second insulating layer; 41-a first window; 42-a second window; 51-a first bonding pad; 52-second bonding pads; 60-P type region.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application.
As described in detail in the embodiments of the present application, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the chip manufacturing process, the parameters of the production chip and the expected values of the design simulation are greatly deviated due to the influence of factors such as process deviation, circuit mismatch, different chip production batches and the like, and great difficulty is brought to the design of an analog circuit with higher parameter requirements. Therefore, the designer may add trimming circuits to the chip when designing the circuit. After the chip is manufactured by a process line, the chip is firstly required to be tested, and parameters which do not meet the circuit requirements are subjected to one-time permanent programming by utilizing a trimming circuit, so that the parameter adjustment of the circuit is completed, and the circuit parameters are closer to a preset value, thereby meeting the design requirements.
The trimming principle of the fuse trimming structure provided by the application can be illustrated by the following simple example. Assuming that a resistor network as shown in fig. 1 exists inside the chip, the designer needs to obtain an accurate resistor, and the actual production may be larger or smaller. The fuse corresponds to a switch, and is changed by selectively blowing or not blowing individual fusesThe state of the switch is changed to change the resistance (R 1 、R 2 And R is 3 ) So that the final total resistance (resistance in integrated circuit and R AB ) The accurate resistance meeting the design requirement is achieved. Of course, the above adjustment of the resistance value by the fuse trimming technology provided by the present application is only an example, and the fuse trimming structure is not limited to trimming the resistance value of the integrated circuit, but also trimming the current, or even replacing a defective component or supplementing a replacement component by adding the fuse trimming structure in the integrated circuit.
In the existing fuse trimming technology, in order to ensure that a fuse can be effectively blown and reduce the failure rate of fuse cutting, a larger blowing voltage is usually required to be applied to the fuse. However, while increasing the blowing voltage and thus the blowing current introduced into the fuse, there is a high probability that the insulating layer located under the fuse will be broken. The insulating layer below the fuse is damaged, so that on one hand, the invasion of substances such as moisture becomes more obvious (the substances such as the moisture can invade from the side wall of the damaged insulating layer and further extend inwards); on the other hand, after the insulating layer under the fuse is broken, a leakage current is generated between VCC under the substrate and two conductive terminals connected to the fuse pad after passing through the substrate and the insulating layer. The generation of leakage current will act on the semiconductor device reversely to affect the trimming accuracy of the fuse, and the accumulation of leakage current will cause the reliability of the IC to be greatly reduced.
Therefore, the present application specifically proposes a new fuse trimming structure, which forms a PN junction between the insulating layer (i.e., the first insulating layer 20) under the fuse layer 30 and the N-type substrate 10, which is conducted in the direction from the first insulating layer 20 to the N-type substrate 10, so that even if a larger current is applied to the fuse layer 30 while the fuse layer 30 is being blown, the first insulating layer 20 under the fuse layer 30 is damaged, and then, due to the existence of the inverted PN junction, the conduction of VCC of the N-type substrate 10 to two conductive terminals (i.e., PAD and GND) connected to the bonding PAD of the fuse layer 30 is still prevented, and therefore, the fuse trimming structure provided by the present application can effectively reduce the leakage current of the fuse trimming structure, and further improve the reliability of the IC.
The detailed description of the fuse trimming structure, the preparation method thereof and the specific situation of the integrated circuit will be provided below.
Embodiment one:
referring to fig. 1 and 2, the fuse trimming structure provided by the present application includes an N-type substrate 10, a first insulating layer 20 disposed on the N-type substrate 10, a fuse layer 30 disposed on the first insulating layer 20, and a second insulating layer 40 disposed on the fuse layer 30; the fuse layer 30 is provided with a first bonding pad 51 and a second bonding pad 52 which are arranged at intervals, and the second insulating layer 40 is provided with a first window 41 exposing the first bonding pad 51 and a second window 42 exposing the second bonding pad 52; the fuse trimming structure further includes a P-type region 60 between the first insulating layer 20 and the N-type substrate 10, the P-type region 60 and the N-type substrate 10 together forming a PN junction that is turned on in a direction of the second insulating layer 40 toward the first insulating layer 20. The fuse trimming structure can solve the problem that the first insulating layer 20 is easily damaged when the fuse layer 30 is blown, thereby avoiding leakage current generated by the fuse trimming structure and further improving the reliability of the IC.
The specific material of the N-type substrate 10 is not limited in the present application, and a person skilled in the art can select a suitable substrate material according to needs, so long as the substrate material is N-type. Of course, the N-type nature of the N-type substrate 10 may be obtained by doping the substrate.
The first insulating layer 20 is located on the upper surface of the N-type substrate 10, and the first insulating layer 20 is disposed to electrically isolate the fuse layer 30 from the substrate layer, as will be appreciated by those skilled in the art in view of the structure level provided by the present application. The thickness and material of the first insulating layer 20 are not particularly limited in the present application, and may be selected by those skilled in the art.
The fuse layer 30 is located above the first insulating layer 20, and the fuse layer 30 is a core of a fuse trimming structure, where the fuse trimming structure is mainly trimmed by blowing or not blowing the fuse layer 30. The working principle of the fuse trimming structure is described in detail in the foregoing, so that the description is omitted here.
Alternatively, in one possible embodiment, the material of fuse layer 30 is polysilicon. Thus, one of the advantages of the polysilicon fuse layer 30 over the prior art is that it can be blown at a lower blowing current, and based on this advantage, the fuse trimming structure using the polysilicon fuse can be disposed at an internal location of the integrated circuit. The application adopts the fuse layer 30 made of polysilicon material, which can properly reduce the fusing current when fusing the fuse layer 30, thus reducing the leakage current to a certain extent and improving the reliability of the IC.
In addition, the first pad 51 and the second pad 52 are provided on the fuse layer 30 at intervals, so that when the fuse trimming structure is connected to the integrated circuit, the first pad 51 and the second pad 52 can be connected to two conductive terminals of an external power source. In short, by providing the first PAD 51 and the second PAD 52, the first PAD 51 and the second PAD 52 can be connected to the PAD terminal and the GND terminal, thereby facilitating the passage of the blowing current to the fuse layer 30.
The second insulating layer 40 is formed on a side of the fuse layer 30 facing away from the first insulating layer 20, i.e., an upper surface of the fuse layer 30. The second insulating layer 40 is disposed, so that the fuse trimming structure is prevented from being invaded by impurities such as water vapor.
Two windows, namely a first window 41 and a second window 42, are arranged on the second insulating layer 40, and the first window 41 and the first bonding pad 51 are oppositely arranged and used for exposing the first bonding pad 51; the second window 42 is disposed opposite to the second pad 52, so as to expose the second pad 52, as shown in fig. 1. In this way, the switching on of the fuse layer 30 and the external power supply can be facilitated.
The present application further provides a P-type region 60 between the first insulating layer 20 and the N-type substrate 10 such that a PN junction conducting in the direction of the second insulating layer 40 toward the first insulating layer 20 can be formed between the P-type region 60 and the N-type substrate 10. In this way, even if the fuse trimming structure causes the first insulating layer 20 to be damaged due to the large blowing current being applied to the fuse layer 30, the leakage current generated in the VCC direction of the N-type substrate 10 toward the PAD or GND is prevented due to the PN junction, so that the reliability of the IC can be improved.
It should be noted that the material of the P-type region 60 is not limited in the present application, and a person skilled in the art may select a suitable material or perform doping of a suitable ion by himself, so long as a PN junction that is conducted along the direction of the second insulating layer 40 toward the first insulating layer 20 is formed between the P-type region 60 and the N-type substrate 10.
In summary, the fuse trimming structure provided by the present application includes an N-type substrate 10, a first insulating layer 20 disposed on the N-type substrate 10, a fuse layer 30 disposed on the first insulating layer 20, and a second insulating layer 40 disposed on the fuse layer 30; the fuse layer 30 is provided with a first bonding pad 51 and a second bonding pad 52 which are arranged at intervals, and the second insulating layer 40 is provided with a first window 41 exposing the first bonding pad 51 and a second window 42 exposing the second bonding pad 52; the fuse trimming structure further includes a P-type region 60 between the first insulating layer 20 and the N-type substrate 10, the P-type region 60 and the N-type substrate 10 together forming a PN junction that is turned on in a direction of the second insulating layer 40 toward the first insulating layer 20. The present application forms the P-type region 60 between the first insulating layer 20 and the N-type substrate 10 of the fuse trimming structure, so that the N-type substrate 10 and the P-type region 60 together construct a PN junction that is conducted along the second insulating layer 40 toward the first insulating layer 20. In this way, even if a large blowing current is applied to the fuse layer 30 in order to effectively blow the fuse layer 30, so that the first insulating layer 20 located under the fuse layer 30 is damaged, the existence of the PN junction prevents the VCC of the N-type substrate 10 from generating a leakage current in the direction of PAD or GND. By adopting the fuse trimming structure provided by the application, leakage current can be effectively reduced, and the reliability of the IC can be improved.
In one possible embodiment, referring to fig. 2, the orthographic projection width of the p-type region 60 on the N-type substrate 10 is greater than a first width, which is a distance between orthographic projections of the first pad 51 and the second pad 52 on the N-type substrate 10.
That is, the width of the P-type region 60 is larger than the first width, and the width direction corresponds to the horizontal direction in fig. 2. Since heat is easily accumulated at the first and second pads 51 and 52 of the fuse layer 30 when the fuse layer 30 is blown, the fuse layer 30 at the positions corresponding to the first and second pads 51 and 52 is easily blown and the relative positions of the first insulating layer 20 corresponding to the first and second pads 51 and 52 are also most easily damaged when the fuse layer 30 is blown. Therefore, in order for the PN junction to effectively prevent the VCC of the N-type substrate 10 from generating leakage current in the direction of PAD or GND, the width of the P-type region 60 needs to be greater than the first width.
Further, in order to make the effect of preventing the VCC of the N-type substrate 10 from generating the leakage current toward the PAD or GND better, the front projection width of the P-type region 60 on the N-type substrate 10 may be larger than the front projection width of the fuse layer 30 on the N-type substrate 10.
In another possible embodiment, referring to fig. 3, the front projection of the p-type region 60 on the N-type substrate 10 coincides with the N-type substrate 10. In this way, the PN junction formed between the P-type region 60 and the N-type substrate 10 can better prevent the VCC of the N-type substrate 10 from generating leakage current in the direction of PAD or GND.
It should be noted that the formation of the P-type region 60 is not limited in this application, and the formation of the P-type region 60 may be performed by ion doping or deposition or sputtering, for example. For example, when the width of the P-type region 60 is greater than the first width but less than the width of the N-type substrate 10, the P-type region 60 may be formed by performing P-type ion implantation on the upper surface of the N-type substrate 10; when the front projection of the P-type region 60 on the N-type substrate 10 coincides with the N-type substrate 10, the P-type region 60 may be formed by deposition or sputtering on the N-type substrate 10.
In one possible embodiment, fuse layer 30 includes a first portion and two second portions at opposite ends of the first portion, the two second portions corresponding to first pad 51 and second pad 52, respectively; wherein the thickness of the first portion is less than the thickness of the second portion.
The first portion is a middle region of the fuse layer 30, and the two second portions are left and right regions of the fuse layer 30, respectively. It should be understood that the orientations shown in the left and right regions are merely for ease of understanding and are illustrated by way of example in fig. 2 and 3 and are not limiting of the application.
In the present embodiment, the two second portions correspond to the first pad 51 and the second pad 52, respectively, that is, the two second portions are the area under the first pad 51 and the area under the second pad 52, respectively.
The thickness of the first portion is set smaller than that of the second portion in the present application, on the one hand, because the thickness of the first portion is small, so that the fuse layer 30 can be easily blown from the first portion, as shown in fig. 4; on the other hand, the thickness of the second portion is large, so that when the fuse layer 30 is blown, the situation that the positions of the fuse layer 30 corresponding to the first pad 51 and the second pad 52 are quickly blown due to the fact that heat is easily accumulated at the positions of the first pad 51 and the second pad 52 of the fuse layer 30 can be effectively avoided, and therefore the positions of the first insulating layer 20 which are most easily damaged can be protected to a certain extent (because the positions of the first insulating layer 20 corresponding to the first pad 51 and the second pad 52 are easily damaged, the thickness of the fuse layer 30 at the positions is increased, and the risk that the first insulating layer 20 is damaged can be reduced to a certain extent).
To further reduce the risk of damage to the first insulating layer 20, in one possible embodiment, the first insulating layer 20 includes an insulating layer body and two insulating layer ends at opposite ends of the insulating layer body, the two insulating layer ends corresponding to the first and second pads 51 and 52, respectively; wherein, the thickness of the end parts of the two insulating layers is larger than that of the insulating layer main body.
It should be understood that the insulating layer body is the middle region of the first insulating layer 20, and the two insulating layer ends are the position where the first insulating layer 20 is located below the first pad 51 and the position where the first insulating layer 20 is located below the second pad 52.
The thickness of the two insulating layer ends is greater than the thickness of the insulating layer body, so that the risk of the first insulating layer 20 being damaged can be effectively reduced by increasing the thickness of the insulating layer ends.
As described above, the present application forms the P-type region 60 between the first insulating layer 20 and the N-type substrate 10 of the fuse trimming structure, so that the N-type substrate 10 and the P-type region 60 together construct a PN junction that is turned on in the direction of the second insulating layer 40 toward the first insulating layer 20. And the material of the fuse layer 30 is selected to be polysilicon, the fuse layer 30 is set to be thin at the middle and thick at two sides, and the first insulating layer 20 is set to be thick at two sides, so that firstly, due to the selected polysilicon material of the fuse layer 30, the fuse layer 30 can be easily blown by using smaller blowing current as much as possible, even if the first insulating layer 20 under the fuse layer 30 is damaged in the blowing process, the existence of the PN junction can prevent the VCC of the N-type substrate 10 from generating leakage current towards the PAD or GND. Therefore, by adopting the fuse trimming structure provided by the application, leakage current can be effectively reduced, and the reliability of the IC can be improved.
Embodiment two:
referring to fig. 5, the present application further provides a method for preparing a fuse trimming structure, which includes the following steps:
s100, an N-type substrate 10 is provided.
The material and thickness of the N-type substrate 10 are not limited in the present application, and may be selected by those skilled in the art.
S200, forming a P-type region 60 on the N-type substrate 10, wherein the P-type region 60 and the N-type substrate 10 jointly form a PN junction.
The P-type region 60 may be formed by ion implantation of the N-type substrate 10, or may be formed by depositing or sputtering a corresponding material on the N-type substrate 10, and the present application is not particularly limited.
S300, forming a first insulating layer 20 on the P-type region 60, wherein the first insulating layer 20 covers the P-type region 60.
S400, forming a fuse layer 30 on the first insulating layer 20, wherein the fuse layer 30 has a first pad 51 and a second pad 52 spaced apart from each other, and the fuse layer 30 and the N-type substrate 10 are electrically isolated by the first insulating layer 20.
S500, a second insulating layer 40 is formed on the fuse layer 30 to cover the fuse layer 30.
That is, the first insulating layer 20, the fuse layer 30, and the second insulating layer 40 are sequentially formed on the P-type region 60.
It should be noted that, for the material, thickness, structural form, etc. of the N-type substrate 10, the P-type region 60, the first insulating layer 20, the fuse layer 30, and the second insulating layer 40, reference may be made to the related description of the structural parts of the fuse trimming structure, and for avoiding repeated description, the same parts will not be repeated in this embodiment.
S600, a first window 41 exposing the first pad 51 and a second window 42 exposing the second pad 52 are opened on the second insulating layer 40 through a photolithography process.
Since the photolithography process is well known to those skilled in the art, the detailed steps of forming the first window 41 exposing the first pad 51 and the second window 42 exposing the second pad 52 on the second insulating layer 40 by using the photolithography process will not be described in detail.
The fuse structure prepared by the preparation method of the fuse trimming structure provided by the embodiment can prevent the VCC of the N-type substrate 10 from generating leakage current towards the PAD or GND due to the existence of the PN junction, so that the reliability of the IC can be improved.
In a possible embodiment, the step S200 forms the P-type region 60 on the N-type substrate 10, where the P-type region 60 and the N-type substrate 10 together form a PN junction, and includes:
a P-type region 60 is formed in the N-type substrate 10 by an ion implantation process, the upper surface of the P-type region 60 is flush with the upper surface of the N-type substrate 10, and the P-type region 60 and the N-type substrate 10 together form a PN junction, as shown in fig. 2.
The ion type of the implantation is not limited to the above, and may be any type as long as it is P-type ions and can form a PN junction with the N-type substrate 10, which is conducted from the second insulating layer 40 to the first insulating layer 20.
In another possible embodiment, the step S200 forms the P-type region 60 on the N-type substrate 10, where the P-type region 60 and the N-type substrate 10 together form a PN junction, and includes:
a P-type region 60 is formed on the N-type substrate 10 by a deposition process or a sputtering process, the P-type region 60 covers the upper surface of the N-type substrate 10, and the P-type region 60 and the N-type substrate 10 together form a PN junction, as shown in fig. 3.
Embodiment III:
the application also provides an integrated circuit which comprises the fuse trimming structure. Since the specific hierarchical structure and the beneficial effects of the fuse trimming structure are described in detail above, the present application is not repeated here. The integrated circuit obtained by adopting the fuse trimming structure provided by the application can prevent the fuse trimming structure from generating leakage current due to the existence of the PN junction in the fuse trimming structure, thereby improving the reliability of the IC.
While the application has been described with reference to several particular embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the application. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the application without departing from the essential scope thereof. Therefore, it is intended that the application not be limited to the particular embodiment disclosed, but that the application will include all embodiments falling within the scope of the appended claims.
Claims (9)
1. The fuse trimming structure is characterized by comprising an N-type substrate, a first insulating layer positioned on the N-type substrate, a fuse layer positioned on the first insulating layer and a second insulating layer positioned on the fuse layer; the fuse wire layer is provided with a first bonding pad and a second bonding pad which are arranged at intervals, and the second insulating layer is provided with a first window exposing the first bonding pad and a second window exposing the second bonding pad; the fuse trimming structure further comprises a P-type region positioned between the first insulating layer and the N-type substrate, wherein the P-type region and the N-type substrate jointly form a PN junction conducted along the direction of the second insulating layer towards the first insulating layer; the orthographic projection width of the P-type region on the N-type substrate is larger than a first width, and the first width is the distance between orthographic projections of the first bonding pad and the second bonding pad on the N-type substrate.
2. The fuse trimming structure of claim 1, wherein an orthographic projection of the P-type region on the N-type substrate coincides with the N-type substrate.
3. The fuse trimming structure of claim 1, wherein the fuse layer is made of polysilicon.
4. The fuse trimming structure of claim 1, wherein the fuse layer comprises a first portion and two second portions at opposite ends of the first portion, the two second portions corresponding to the first pad and the second pad, respectively; wherein the thickness of the first portion is less than the thickness of the second portion.
5. The fuse trimming structure of claim 1 or 4, wherein the first insulating layer comprises an insulating layer body and two insulating layer ends at opposite ends of the insulating layer body, the two insulating layer ends corresponding to the first bonding pad and the second bonding pad, respectively; the thickness of the end parts of the two insulating layers is larger than that of the insulating layer main body.
6. The preparation method of the fuse trimming structure is characterized by comprising the following steps of:
providing an N-type substrate;
forming a P-type region on the N-type substrate, wherein the P-type region and the N-type substrate jointly form a PN junction;
forming a first insulating layer on the P-type region, wherein the first insulating layer covers the P-type region;
forming a fuse layer on the first insulating layer, wherein the fuse layer is provided with a first bonding pad and a second bonding pad which are spaced, and the fuse layer and the N-type substrate are electrically isolated through the first insulating layer; the orthographic projection width of the P-type region on the N-type substrate is larger than a first width, and the first width is the distance between orthographic projections of the first bonding pad and the second bonding pad on the N-type substrate;
forming a second insulating layer on the fuse layer to cover the fuse layer;
and opening a first window exposing the first bonding pad and a second window exposing the second bonding pad on the second insulating layer through a photoetching process.
7. The method of manufacturing a fuse trimming structure of claim 6, wherein forming a P-type region on the N-type substrate, the P-type region and the N-type substrate together forming a PN junction comprises:
and forming a P-type region in the N-type substrate through an ion implantation process, wherein the upper surface of the P-type region is flush with the upper surface of the N-type substrate, and the P-type region and the N-type substrate jointly form a PN junction.
8. The method of manufacturing a fuse trimming structure of claim 6, wherein forming a P-type region on the N-type substrate, the P-type region and the N-type substrate together forming a PN junction comprises:
and forming a P-type region on the N-type substrate through a deposition process or a sputtering process, wherein the P-type region covers the upper surface of the N-type substrate, and the P-type region and the N-type substrate jointly form a PN junction.
9. An integrated circuit comprising the fuse trimming structure of any one of claims 1 to 5.
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| CN202211569477.2A CN115810609B (en) | 2022-12-08 | 2022-12-08 | Fuse trimming structure, manufacturing method thereof and integrated circuit |
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| JPH0541481A (en) * | 1991-08-06 | 1993-02-19 | Nec Corp | Semiconductor integrated circuit |
| CN1226084A (en) * | 1998-02-12 | 1999-08-18 | 日本电气株式会社 | Semiconductor device and manufacturing method thereof |
| CN101170099A (en) * | 2007-11-30 | 2008-04-30 | 上海宏力半导体制造有限公司 | Multicrystalline silicon compounds electric fuse silk part |
| CN109244061A (en) * | 2018-09-03 | 2019-01-18 | 上海华虹宏力半导体制造有限公司 | Electrically programmable fuse structure and forming method thereof |
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2022
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0541481A (en) * | 1991-08-06 | 1993-02-19 | Nec Corp | Semiconductor integrated circuit |
| CN1226084A (en) * | 1998-02-12 | 1999-08-18 | 日本电气株式会社 | Semiconductor device and manufacturing method thereof |
| CN101170099A (en) * | 2007-11-30 | 2008-04-30 | 上海宏力半导体制造有限公司 | Multicrystalline silicon compounds electric fuse silk part |
| CN109244061A (en) * | 2018-09-03 | 2019-01-18 | 上海华虹宏力半导体制造有限公司 | Electrically programmable fuse structure and forming method thereof |
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| CN115810609A (en) | 2023-03-17 |
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