CN114725060A - Electrically programmable fuse structure based on CMOS (complementary Metal oxide semiconductor) process and preparation method thereof - Google Patents
Electrically programmable fuse structure based on CMOS (complementary Metal oxide semiconductor) process and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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Abstract
The invention provides an electrically programmable fuse structure based on a CMOS (complementary metal oxide semiconductor) process and a preparation method thereof, wherein the electrically programmable fuse structure comprises the following components from bottom to top: a semiconductor substrate, an intrinsic polysilicon layer and a metal silicide layer; sequentially comprises the following steps from front to back: the fuse structure anode, the fuse structure body and the fuse structure cathode; the width of the fuse structure body is smaller than the width of the fuse structure anode and the width of the fuse structure cathode. The electrically programmable fuse structure can realize the programming process as long as the metal silicide layer is fused, thereby effectively reducing the adverse effect caused by over programming, hardly influencing the initial resistance value and the requirement on the initial programming current, and maximally improving the usability and the reliability of the fuse structure; in addition, sputtering is not easy to generate, pollution is caused, and miniaturization integration is easy to realize; finally, the structure can be completely compatible with the existing CMOS process, has high robustness and is beneficial to large-scale production.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to an electrically programmable fuse structure based on a CMOS (complementary metal oxide semiconductor) process and a preparation method thereof.
Background
With the miniaturization and complexity of semiconductor processes, semiconductor devices become more susceptible to various defects or impurities, and the failure of a single wire, diode, or transistor, etc., often results in defects across the entire chip. To solve this problem, some fuses are formed in the integrated circuit to ensure high reliability of the integrated circuit.
In the prior art, an Electrically Programmable Fuse (eFuse) is a device commonly used in a semiconductor integrated circuit, and is widely applied to a one-time programming storage technology inside a chip, and can be used for recording configuration information of the chip or repairing a defective element inevitable in the integrated circuit due to a semiconductor process. When the chip fails, the eFuse circuit in the chip can repair the defects of the chip, and when the chip runs wrongly, the eFuse circuit can realize automatic diagnosis of the chip, so that the yield of the chip is improved. A characteristic of eFuse circuits is that the bits stored by default are logic "0" s, the desired bit can be programmed from a logic "0" to a logic "1", once written to a logic "1", it cannot be rewritten to a logic "0", but bits that are not written to a logic "0" can also be programmed to a logic "1".
The current eFuse circuits are mainly divided into metal fuses based on fusing metal and polysilicon fuses based on P-type heavy doping. The metal fuse is fused in a thermal mode, and the P-type heavily doped polysilicon fuse fuses the resistor based on an Electron Mobility (EM) principle. The metal fuse wire is mainly fused by heat, so a window needs to be opened on the surface of a chip, and the metal fuse wire can be blown by providing larger heat by higher current, so that the large heat can cause environmental pollution to cause pollution of other devices, and the integration is not easy to realize miniaturization; after the P-type heavily doped polysilicon fuse is programmed, there is a risk of over-programming, which brings a risk of thermal trapping and contamination.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an electrically programmable fuse structure based on CMOS process and a method for manufacturing the same, which are used to solve the problems that a metal fuse in an eFuse circuit in the prior art needs a higher current to provide a larger amount of heat to be blown, the large amount of heat causes environmental pollution, causes pollution to other devices, is not easy to integrate and miniaturize, and after a P-type heavily doped polysilicon fuse is programmed, there is a risk of over-programming, which causes heat trapping and pollution.
To achieve the above and other related objects, the present invention provides an electrically programmable fuse structure based on a CMOS process, which comprises, from bottom to top: a semiconductor substrate, an intrinsic polysilicon layer and a metal silicide layer;
the electrically programmable fuse structure based on the CMOS process sequentially comprises the following components from front to back: the fuse structure comprises a fuse structure anode, a fuse structure body and a fuse structure cathode; the width of the fuse structure body is smaller than the width of the fuse structure anode and the width of the fuse structure cathode.
Optionally, the CMOS process based electrically programmable fuse structure further comprises:
an insulating protective layer covering the metal silicide layer;
and the contact holes are positioned in the anode of the fuse structure and the cathode of the fuse structure, penetrate through the insulating protective layer and the metal silicide layer and are electrically connected with the intrinsic polycrystalline silicon layer.
Further, the insulating protection layer is a nitride layer; the material of the contact hole comprises tungsten.
Optionally, the CMOS process based electrically programmable fuse structure further comprises:
the well layer and the shallow trench isolation are positioned on the semiconductor substrate;
the intrinsic polycrystalline silicon layer is positioned on the surface of the shallow trench isolation, the shallow trench isolation is U-shaped, and the intrinsic polycrystalline silicon layer and the metal silicide layer are surrounded.
Further, the material of the shallow trench isolation comprises silicon oxide; the semiconductor substrate is a P-type doped semiconductor substrate; the well layer is doped N-type or doped P-type.
Optionally, the metal in the metal silicide layer comprises tungsten, titanium, chromium, or nickel.
Optionally, the CMOS process based electrically programmable fuse structure is a wine glass type; the thickness of the metal silicide layer is between 18A and 22A, and the thickness of the intrinsic polycrystalline silicon layer is between 1000A and 1030A.
The invention also provides a preparation method of the electrically programmable fuse structure based on the CMOS process, which is used for preparing the electrically programmable fuse structure based on the CMOS process, and the preparation method comprises the following steps:
providing a semiconductor substrate;
forming an intrinsic polycrystalline silicon layer on the semiconductor substrate;
forming a metal silicide layer on the surface of the intrinsic polycrystalline silicon layer so as to form the electric programmable fuse structure based on the CMOS process; the CMOS process-based electrically programmable fuse structure sequentially comprises the following steps from front to back: the fuse structure comprises a fuse structure anode, a fuse structure body and a fuse structure cathode; the width of the fuse structure body is smaller than the width of the fuse structure anode and the width of the fuse structure cathode.
Optionally, the CMOS process-based electrically programmable fuse structure further comprises an insulating protection layer and a contact hole; the method for forming the insulating protection layer comprises the following steps: depositing the insulating protection layer on the metal silicide layer; the method for forming the contact hole comprises the following steps: forming blind holes penetrating through the insulating protection layer and the metal silicide layer on the anode of the fuse structure and the cathode of the fuse structure; and filling metal materials in the blind holes to form the contact holes.
Optionally, the CMOS process-based electrically programmable fuse structure further includes a well layer and shallow trench isolation; the well layer is formed on the surface of the semiconductor substrate; the intrinsic polycrystalline silicon layer is positioned on the surface of the shallow trench isolation, the shallow trench isolation is U-shaped, and the intrinsic polycrystalline silicon layer and the metal silicide layer are surrounded.
As described above, according to the electrically programmable fuse structure based on the CMOS process and the method for manufacturing the electrically programmable fuse structure of the present invention, the programming process can be realized as long as the fuse structure fuses the metal silicide layer, thereby effectively reducing adverse effects caused by over-programming, hardly affecting the initial resistance value and the requirement for the initial programming current, and maximally improving the usability and reliability of the fuse structure; in addition, sputtering is not easy to generate, pollution is caused, and miniaturization integration is easy to realize; finally, the structure can be completely compatible with the existing CMOS process, has high robustness and is beneficial to large-scale production.
Drawings
Fig. 1 is a schematic cross-sectional view of a programmable fuse structure based on CMOS process according to the present invention.
Fig. 2 shows a circuit layout of an intrinsic polysilicon layer of a programmable fuse structure based on a CMOS process of the present invention.
Fig. 3 is a circuit diagram of an intrinsic polysilicon layer of a programmable fuse structure based on CMOS process according to the present invention.
Fig. 4 shows a circuit layout of a fuse metal layer of a conventional metal blown programmable fuse structure.
Fig. 5 shows a circuit layout of a P-type heavily doped polysilicon layer of a prior programmable fuse structure based on P-type heavily doped polysilicon.
Fig. 6 is a circuit diagram of a conventional programmable fuse structure based on heavily P-doped polysilicon.
Description of the element reference numerals
The fuse structure comprises a semiconductor substrate 10, an intrinsic polycrystalline silicon layer 11, a metal silicide layer 12, an insulating protective layer 13, a contact hole 14, a well layer 15, a shallow trench isolation 16, a metal silicide resistor 17, an intrinsic polycrystalline silicon resistor 18, a fuse structure anode 20, a fuse structure body 21, a fuse structure cathode 22, a fuse metal layer 31, a heavily doped polycrystalline silicon layer 32P type and a heavily doped polycrystalline silicon resistor 33P type.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 6. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation can be arbitrarily changed according to actual needs, and the layout of the components may be more complicated.
Note that where used, the designations left, right, front, back, top, bottom, positive, negative, clockwise, and counterclockwise are used for convenience only and do not imply any particular fixed orientation. In fact, they are used to reflect the relative position and/or orientation between the various parts of the object. The terms "above …," "below …," "between …," and "on …" as used herein refer to the relative position of this layer with respect to the other layers. Likewise, for example, a layer deposited or placed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Further, a layer deposited or placed between layers may be directly in contact with the layers or may have one or more intervening layers.
Example one
As shown in fig. 1 to 3, the present embodiment provides an electrically programmable fuse structure based on a CMOS process, and as shown in fig. 1, the electrically programmable fuse structure includes, from bottom to top: a semiconductor substrate 10, an intrinsic polycrystalline silicon layer 11, and a metal silicide layer 12; as shown in fig. 2, the electrically programmable fuse structure comprises, in order from front to back: a fuse structure anode 20, a fuse structure body 21 and a fuse structure cathode 22; wherein the width of the fuse structure body 21 is smaller than the fuse structure anode 20 and the fuse structure cathode 22.
Here, the area and width of the anode 20 and the cathode 22 of the fuse structure are generally larger than those of the body 21 of the fuse structure because the anode 20 and the cathode 22 of the fuse structure are, on one hand, for leading out the electrodes of the body 21 of the fuse structure and, on the other hand, for forming effective heat dissipation, the melting point of the whole electrically programmable fuse structure is generated somewhere in the body 21 of the fuse structure. In addition, the metal silicide layer 12 needs to be blown during the programming process, so the width thereof is designed to be thinner than the intrinsic polysilicon layer 11, and the specific width is set according to the actual requirement, which is not limited too.
As described in the background, the current electrically programmable fuse structure is mainly divided into a metal fuse structure based on a fuse metal and a polysilicon fuse structure based on P-type heavy doping. As shown in fig. 4, in the metal fuse structure based on the fuse metal, during programming, a higher current needs to be applied between the anode 20 of the fuse structure and the cathode 22 of the fuse structure to provide a larger amount of heat to blow the fuse metal layer 31 in the region of the fuse structure body 21, the process has high requirements on programming equipment, and the high-temperature metal is easily vaporized and volatilized to generate sputtering and pollute other devices; in addition, windows need to be opened on the surface of the chip to realize programming, so that the cost is high. The metal fuse structure is not easy to integrate and miniaturize.
As shown in fig. 5 and fig. 6, a P-type heavily doped polysilicon fuse structure is based on the principle that a fuse is blown by an instantaneous current according to the Electro-Migration (Electro-Migration) principle, specifically, during programming, under the action of a higher current density between the fuse structure anode 20 and the fuse structure cathode 22, metal atoms in a metal silicide layer migrate along the direction of electron movement (i.e., from the fuse structure cathode 22 toward the fuse structure anode 20), and the electromigration increases with the continuous increase of the current density, and the fuse structure cathode 22 forms a hole due to the shortage of atoms, which causes an open circuit, even though the metal silicide layer resistor 17 (as shown in fig. 6) is blown; in addition, since the P-type heavily doped polysilicon layer has a small resistance, it is also required to perform fuse. Therefore, during the process of fusing the metal silicide resistor 17 and the P-type heavily doped polysilicon resistor 33, two times of fusing are required, which may cause over-programming and thermal trapping and contamination risks.
The present embodiment provides an electrically programmable fuse structure, which also enables the fuse to be blown by a transient current based on the Electro-Migration (Electro-Migration) principle, specifically, when a current is applied between the anode 20 of the fuse structure and the cathode 22 of the fuse structure during programming, the metal atoms in the metal silicide layer 12 will migrate along the direction of electron movement (i.e. from the cathode 22 of the fuse structure toward the anode 20 of the fuse structure), and the Electro-Migration will increase with the continuous increase of the current density, and the cathode 22 of the fuse structure will form a hole due to the shortage of atoms, resulting in an open circuit, even if the metal silicide layer resistor 17 (as shown in fig. 3) is blown, since the intrinsic resistance of the polysilicon layer 11 under the metal silicide layer 12 is very high relative to the metal silicide layer 12, similar to the open circuit phenomenon, that is, before programming, the resistance of the whole fuse structure is determined by the metal silicide resistor 17, after programming, the resistance value of the whole fuse structure is determined by the intrinsic polycrystalline silicon layer 11, and the resistance of the intrinsic polycrystalline silicon layer 11 below the metal silicide layer 12 is very high relative to the metal silicide layer 12, so that the resistance of the fuse structure is kept in a higher numerical value range after programming, therefore, the fuse structure of the embodiment can realize the programming process as long as the fuse structure realizes the fusing of the metal silicide layer, thereby effectively reducing the adverse effect caused by over-programming, hardly influencing the initial resistance value and the requirement on the initial programming current, and maximally improving the usability and reliability of the fuse structure; in addition, sputtering is not easy to generate, pollution is caused, and miniaturization integration is easy to realize; finally, the structure can be completely compatible with the existing CMOS process, has high robustness and is beneficial to large-scale production.
As an example, the semiconductor substrate 10 may be a semiconductor wafer such as a silicon wafer. But may also include elemental semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. The elemental semiconductor material may be, but is not limited to, monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond, among others. The compound semiconductor material may be, but is not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium telluride. The alloy semiconductor material may be, but is not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP.
As shown in fig. 1, the electrically programmable fuse structure of the present embodiment further includes, as an example: an insulating protective layer 13 covering the metal silicide layer 12; and a contact hole 14 in the fuse structure anode 20 and the fuse structure cathode 22, penetrating the insulating protection layer 13 and the metal silicide layer 12 and electrically connected to the intrinsic polysilicon layer 11. The insulating protection layer 13 is used to protect the fuse structure, and the material of the insulating protection layer is selected from an electrically insulating material, such as an oxide or a nitride, where the oxide may be silicon dioxide, and the nitride may be silicon nitride. In this embodiment, the insulating protection layer 13 is selected to be a nitride layer. The contact hole 14 is used to electrically lead out the fuse structure anode 20 and the fuse structure cathode 22, as can be seen from fig. 1 and 2, the fuse structure anode 20 and the fuse structure cathode 22 may each include more than one contact hole 14, and the contact hole 14 is filled with a conductive material and electrically connected to the intrinsic polysilicon layer 11 to realize electrode lead-out. The conductive material filled in the contact hole 14 is generally a tungsten metal material with stronger hole-filling capability, and preferably, a TiW layer is deposited in the hole before filling the tungsten metal, so as to improve the adhesion property of the tungsten metal to be subsequently filled.
As shown in fig. 1, the electrically programmable fuse structure of the present embodiment further includes, as an example: a well layer 15 and shallow trench isolation 16 on the semiconductor substrate 10; the intrinsic polysilicon layer 11 is located on the surface of the shallow trench isolation 16, and the shallow trench isolation 16 is U-shaped, enclosing the intrinsic polysilicon layer 11 and the metal silicide layer 12. The well layer 15 may be formed by doping the surface of the semiconductor substrate 10, or may be formed by deposition on the surface of the semiconductor substrate 10. Generally, the semiconductor substrate 10 is selected to be a P-type doped semiconductor substrate, and the well layer 15 may be doped N-type or P-type. The material of the shallow trench isolation 16 is selected to be a material with better insulating property, such as silicon oxide.
As an example, the metal in the metal silicide layer 12 may be selected to be a metal suitable for preparing a fuse structure, such as tungsten, titanium, chromium, or nickel.
As shown in fig. 2, the electrically programmable fuse structure of the present embodiment may be designed in shape according to specific situations, for example, may be an "H" shape or a wine glass shape. In this embodiment, the preferred embodiment is a wine cup type, wherein the anode 20 of the fuse structure is the upper end with the largest area of the cup body, the cathode 22 of the fuse structure is the lower end with the smaller area of the cup body, and the body 21 of the fuse structure is the middle part with the smallest area of the cup body. With this shape, metal accumulation more occurs at the anode end at the time of fusing.
As an example, the metal silicide layer 12 has a thickness between 18A-22A, the intrinsic polysilicon layer 11 has a thickness between 1000A-1030A, and the insulating protective layer has a thickness between 270A-330A.
It should be noted that fig. 3 and fig. 6 are general circuit diagrams of the fuse structure, in which the inductance and the capacitance are electrical connection modes when the fuse structure is applied to a high frequency domain.
Example two
The present embodiment provides a method for manufacturing an electrically programmable fuse structure based on a CMOS process, and the method can be used to manufacture the electrically programmable fuse structure based on a CMOS process according to the first embodiment. However, the electrically programmable fuse structure based on the CMOS process in the first embodiment is not limited to be manufactured by the manufacturing method of this embodiment, and other suitable manufacturing methods are also possible. For the electrically programmable fuse structure based on the CMOS process, please refer to embodiment one, which will not be described in detail below.
As shown in fig. 1 and 2, the preparation method comprises the following steps:
providing a semiconductor substrate 10;
forming an intrinsic polysilicon layer 11 on the semiconductor substrate 10;
forming a metal silicide layer 12 on the surface of the intrinsic polysilicon layer 11, thereby forming the CMOS process-based electrically programmable fuse structure; the CMOS process-based electrically programmable fuse structure sequentially comprises the following steps from front to back: a fuse structure anode 20, a fuse structure body 21 and a fuse structure cathode 22; wherein the width of the fuse structure body 21 is smaller than the fuse structure anode 20 and the fuse structure cathode 22.
Forming an intrinsic polycrystalline silicon layer 11 on the semiconductor substrate 10 includes forming an intrinsic polycrystalline silicon layer material layer; the intrinsic polysilicon material layer is then patterned to obtain an intrinsic polysilicon layer 11 of a desired shape for the fuse structure. The process mainly comprises the following steps: photoetching patterning process and etching process. Similarly, the metal silicide layer 12 may be formed on the surface of the intrinsic polycrystalline silicon layer 11 using the same method.
As shown in fig. 1, the CMOS process-based electrically programmable fuse structure further includes an insulating protection layer 13 and a contact hole 14, as an example; the method of forming the insulating protective layer 13 includes: depositing the insulating protection layer 13 on the metal silicide layer; the method for forming the contact hole 14 comprises the following steps: forming blind holes penetrating through the insulating protection layer 13 and the metal silicide layer 12 on the fuse structure anode 20 and the fuse structure cathode 22; and filling the blind holes with metal materials to form the contact holes 14. The insulating protection layer 13 is formed after the metal silicide layer 12 is formed, and then the contact hole 14 is formed after the insulating protection layer 13 is formed.
As shown in fig. 1, the electrically programmable fuse structure based on CMOS process further includes a well layer 15 and shallow trench isolation 16 as an example; the well layer 15 is formed on the surface of the semiconductor substrate 10; the intrinsic polysilicon layer 11 is located on the surface of the shallow trench isolation 16, and the shallow trench isolation 16 is U-shaped, enclosing the intrinsic polysilicon layer 11 and the metal silicide layer 12. Before forming the intrinsic polysilicon layer 11, a well layer 15 is formed on the surface of the semiconductor substrate 10, and then the shallow trench isolation 16 is formed on the well layer 15.
Thus, embodiments of a CMOS process based electrically programmable fuse structure and method of making the same that avoid over-programming have been described. Although the present disclosure has been described with respect to specific exemplary embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the disclosure. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.
In summary, according to the electrically programmable fuse structure based on the CMOS process and the method for manufacturing the electrically programmable fuse structure of the present invention, the fuse structure can realize the programming process only by fusing the metal silicide layer, thereby effectively reducing the adverse effects caused by over-programming, hardly affecting the initial resistance and the requirement for the initial programming current, and maximally improving the usability and reliability of the fuse structure; in addition, sputtering is not easy to generate, pollution is caused, and miniaturization integration is easy to realize; finally, the structure can be completely compatible with the existing CMOS process, has high robustness and is beneficial to large-scale production. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. An electrically programmable fuse structure based on a CMOS process is characterized in that the electrically programmable fuse structure based on the CMOS process comprises the following components from bottom to top: a semiconductor substrate, an intrinsic polysilicon layer and a metal silicide layer;
the electrically programmable fuse structure based on the CMOS process sequentially comprises the following components from front to back: the fuse structure comprises a fuse structure anode, a fuse structure body and a fuse structure cathode; the width of the fuse structure body is smaller than the width of the fuse structure anode and the width of the fuse structure cathode.
2. The CMOS process based electrically programmable fuse structure of claim 1, further comprising:
an insulating protective layer covering the metal silicide layer;
and the contact holes are positioned in the anode of the fuse structure and the cathode of the fuse structure, penetrate through the insulating protective layer and the metal silicide layer and are electrically connected with the intrinsic polycrystalline silicon layer.
3. The CMOS process based electrically programmable fuse structure of claim 2, wherein: the insulating protective layer is a nitride layer; the material of the contact hole comprises tungsten.
4. The CMOS process based electrically programmable fuse structure of claim 1, further comprising:
the well layer and the shallow trench isolation are positioned on the semiconductor substrate;
the intrinsic polycrystalline silicon layer is positioned on the surface of the shallow trench isolation, the shallow trench isolation is U-shaped, and the intrinsic polycrystalline silicon layer and the metal silicide layer are surrounded.
5. The CMOS process based electrically programmable fuse structure of claim 4, wherein: the material of the shallow trench isolation comprises silicon oxide; the semiconductor substrate is a P-type doped semiconductor substrate; the well layer is doped N-type or doped P-type.
6. The CMOS process based electrically programmable fuse structure of claim 1, wherein: the metal in the metal silicide layer comprises tungsten, titanium, chromium or nickel.
7. The CMOS process based electrically programmable fuse structure of claim 1, wherein: the electrically programmable fuse structure based on the CMOS process is in a wine glass shape; the thickness of the metal silicide layer is between 18A and 22A, and the thickness of the intrinsic polycrystalline silicon layer is between 1000A and 1030A.
8. A preparation method of an electrically programmable fuse structure based on a CMOS process, which is used for preparing the electrically programmable fuse structure based on the CMOS process as claimed in any one of claims 1 to 7, and which comprises the following steps:
providing a semiconductor substrate;
forming an intrinsic polycrystalline silicon layer on the semiconductor substrate;
forming a metal silicide layer on the surface of the intrinsic polycrystalline silicon layer so as to form the electric programmable fuse structure based on the CMOS process; the CMOS process-based electrically programmable fuse structure sequentially comprises the following steps from front to back: the fuse structure comprises a fuse structure anode, a fuse structure body and a fuse structure cathode; the width of the fuse structure body is smaller than the width of the fuse structure anode and the width of the fuse structure cathode.
9. The method of claim 8, wherein the electrically programmable fuse structure further comprises an insulating protection layer and a contact hole; the method for forming the insulating protection layer comprises the following steps: depositing the insulating protection layer on the metal silicide layer; the method for forming the contact hole comprises the following steps: forming blind holes penetrating through the insulating protection layer and the metal silicide layer on the anode of the fuse structure and the cathode of the fuse structure; and filling metal materials in the blind holes to form the contact holes.
10. The method according to claim 8, wherein the electrically programmable fuse structure further comprises a well layer and shallow trench isolation; the well layer is formed on the surface of the semiconductor substrate; the intrinsic polycrystalline silicon layer is positioned on the surface of the shallow trench isolation, the shallow trench isolation is U-shaped, and the intrinsic polycrystalline silicon layer and the metal silicide layer are surrounded.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118571860A (en) * | 2024-08-01 | 2024-08-30 | 杭州积海半导体有限公司 | Fuse device and forming method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6337507B1 (en) * | 1995-09-29 | 2002-01-08 | Intel Corporation | Silicide agglomeration fuse device with notches to enhance programmability |
| CN103855127A (en) * | 2012-12-04 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Programmable polycrystalline silicon diode fuse wire device structure and manufacturing method |
| CN105826238A (en) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Electrically programmable fuse structure and formation method thereof |
| CN109037190A (en) * | 2018-07-27 | 2018-12-18 | 上海华力集成电路制造有限公司 | A kind of electric fuse structure and its manufacturing method |
-
2022
- 2022-06-09 CN CN202210644279.1A patent/CN114725060A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6337507B1 (en) * | 1995-09-29 | 2002-01-08 | Intel Corporation | Silicide agglomeration fuse device with notches to enhance programmability |
| CN103855127A (en) * | 2012-12-04 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Programmable polycrystalline silicon diode fuse wire device structure and manufacturing method |
| CN105826238A (en) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Electrically programmable fuse structure and formation method thereof |
| CN109037190A (en) * | 2018-07-27 | 2018-12-18 | 上海华力集成电路制造有限公司 | A kind of electric fuse structure and its manufacturing method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118571860A (en) * | 2024-08-01 | 2024-08-30 | 杭州积海半导体有限公司 | Fuse device and forming method |
| CN118571860B (en) * | 2024-08-01 | 2024-11-22 | 杭州积海半导体有限公司 | Fuse device and forming method |
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