CN115802763A - Memory with ultra-thin memory cells - Google Patents

Abstract

The invention proposes a memory with an ultra-thin memory element, the memory film (30) of which contains an OTS (Ovonic Threshold Switching) film (30A) and does not contain a separate phase change material (PCM, ie Phase-Change Material) film. In one embodiment, the total thickness T of the memory film (30) is not greater than 60 nm. In another embodiment, the storage film (30) does not contain a separate programming film. Ultra-thin memory includes three-dimensional horizontal memory and three-dimensional vertical memory.

Description

Memories with ultra-thin memory cells

technical field

The present application relates to the field of integrated circuits, in particular, to a memory with ultra-thin storage elements.

Background technique

The storage element area of the cross point memory is small (4F ² ), which can realize three-dimensional stacking. As shown in Figure 1, the storage unit 00 contains the first address line 01, the second address line 02, and the storage film 06 between them (the storage film 06 includes all the first address line 01 and the second address line 02 film). The memory film 06 generally includes a selector film 03 and a programmable film 04 . Among them, the gating film 03 is used to avoid interference between adjacent storage elements, and it has two volatile states (low resistance state and high resistance state, representing "ON" and "OFF"respectively); programming film 04 Used to store information state, it has at least two non-volatile states (low resistance state and high resistance state, representing "1" and "0" respectively). Here, "volatile" means that after power-off, the low-impedance state is no longer maintained and returns to a high-impedance state (of course, after power-off, the high-impedance state is still a high-impedance state); "non-volatile" is It means that after power-off, the low-impedance state and high-impedance state continue to be maintained. In the memory cell 00, the width (dimension) of the address lines 01 and 02 is F. F is also the storage element size. The total thickness T of the storage film 06 is the distance between the upper surface 01P of the first address line and the lower surface 02P of the second address line. In general (for example, the storage 06 only contains the gate film 03 and the programming film 04), T= _TS + _TM . Wherein, the thickness of the gate film 03 is T _S , and the thickness of the programming film 04 is _TM . In many cases, T _S and T _M do not decrease with F scaling. When F is scaled down to a smaller node (such as 10nm), the thickness-to-width ratio (T:F) of the storage element will be larger, resulting in increased process difficulty.

Interleaved array memories have been used as three-dimensional once-programmable memories (3D-OTP) and three-dimensional multiple-time-programmable memories (3D-MTP). The representative product of 3D-OTP is 3-D OTP produced by Matrix Semiconductor Corporation (Figure 2A); the representative product of 3D-MTP is 3D-XPoint produced by Intel Corporation (Figure 2B). Both products face the challenge of "excessive thickness-to-width ratio (T:F)", which makes it difficult to upgrade the products.

2A is a cross-sectional view of a 3-D OTP memory cell 00, the memory film 06 of which contains a gate film 03 and a programming film 04. Wherein, the gate film 03 is a diode film. During programming, in order to avoid the large leakage current generated by the reverse biased diode, the diode needs to have a large reverse breakdown voltage, so its thickness T _S is relatively large, as ~300nm; the programming film 04 is an antifuse (antifuse) film, which uses silicon dioxide, and the thickness _TM is very small, generally less than 10nm; because the thickness TM of the antifuse film ₀₄ is much smaller than the thickness T _S of the diode film 03 , the thickness T of the storage film 06 is mainly determined by the thickness T _S of the diode film 03. In FIG. 2A , the memory element size F is 130nm, and the thickness-to-width ratio (T _S :F) of the diode 03 is 2.3:1, which is acceptable. However, since the thickness T _S of the diode 03 does not decrease as F shrinks. This results in that the aspect ratio of the diode 03 is too large after F is scaled down: if scaled to F=10nm node, the aspect ratio will reach 30:1, which is difficult to realize in the process.

FIG. 2B is a cross-sectional view of a 3D-XPoint memory cell 00 , and its memory film 06 also includes a gate film 03 and a programming film 04 . Among them, the gate film 03 is an OTS (Ovonic Threshold Switch) film, which presents the Ovshinsky phenomenon, that is, it changes from a non-conductive state to a conductive state or vice versa under the action of an electric field; the programming film 04 contains a phase change material (PCM), which Can be non-volatilely switched between crystalline (low resistance state) and amorphous (high resistance state). In FIG. 2B, the memory element size F is 20nm; the thickness T _S of the OTS film 03 (including the surrounding interface isolation material) is ~50nm, and the thickness T _M of the PCM film 04 (including the surrounding interface isolation material) is ~70nm, Therefore, the total thickness T of the memory film 06 is ~120 nm. Correspondingly, the thickness-to-width ratio of the storage film 06 is 6:1, which is acceptable at the F=20nm node, but the space for further scaling is limited. For example, at the F=10nm node, the aspect ratio will increase to 12:1. It is also challenging to realize such a large aspect ratio in the process.

In summary, for 3-D OTP (Figure 2A), although its programming film (antifuse film) 04 is very thin (<10nm), its gating film (diode film) 03 is very thick (~300nm), As a result, it faces the challenge of "excessive thickness-to-width ratio". On the other hand, for 3D-XPoint, although the thickness T _S (~50nm) of its gate film 03 (using OTS film) has greatly improved compared to 3-D OTP (using diode film as gate film) (from ~ 300nm is reduced to ~50nm), but due to the large thickness _TM (~70nm) of its programming film (PCM film) 04, 3D-XPoint still faces the challenge of "too large aspect ratio". How to reduce the total thickness T of the memory film 06 is of great significance to the scalability and manufacturability of the memory cell 00 .

Contents of the invention

The main object of the present invention is to provide a memory with a small thickness-to-width ratio (T:F) of the memory film.

Another object of the present invention is to provide a memory with an ultra-thin (T<60nm) memory film.

Another object of the invention is to provide a memory that is easy to manufacture.

Another object of the present invention is to provide a memory that is easy to shrink.

Another object of the present invention is to provide a memory with a simple structure (1S structure instead of 1S1R structure).

In order to achieve these objects, the present invention proposes a memory with an ultra-thin memory film (abbreviated as "ultra-thin memory"), which combines the thickness TM of the antifuse film 04 in the 3-D OTP (Fig. 2A) _is very thin ( Generally <10nm) and the thickness T _S of the OTS film 03 in 3D-XPoint (Fig. 2B) is relatively thin (generally ≤50nm), realizing an ultra-thin storage film. Its storage film 06 adopts OTS film as gate film 03, adopts antifuse film as programming film 04 (in the embodiment of Fig. 7 even does not need antifuse film), total thickness T is not more than 60nm, the width of address line F is also not greater than 60nm. Even if F is shrunk to 10nm, the thickness-to-width ratio (T:F) of the storage film 06 is only 6:1, which is easy to manufacture. Note that the storage film 06 does not contain a separate PCM film in order not to increase its total thickness T. Given that its programming film 04 is an antifuse film, the ultra-thin memory is a one-time programming memory.

Correspondingly, the present invention proposes a memory with an ultra-thin storage unit, which is characterized in that it includes: an ultra-thin storage unit (0X), and the ultra-thin storage unit (0X) includes: a first address line (10) and a first address line (10) Two address lines (20), the second address line (20) intersects with the first address line (10); arranged between the first address line (10) and the second address line (20) The storage film (30) between; the storage film (30) includes: one layer of OTS film (30A) and one layer of antifuse film (30B), and the storage film (30) does not contain a separate PCM film; the The total thickness of the storage film (30) is less than or equal to 60nm, and the width of the first address line (10) or the second address line (20) is less than or equal to 60nm.

In order to further reduce the total thickness T of the storage film, simplify the structure of the storage unit, and make the storage unit easier to shrink and manufacture, the present invention also proposes a kind of ultra-thin one-time programming memory based on the OTS film (abbreviated as "OTS/OTP memory") . It is based on the forming (or firing) properties of the OTS film. As shown in Figure 5, most of the OTS films exhibit a forming characteristic - when the current-voltage (IV) scan is performed on the OTS film, the first (the first time, referring to the first time after the OTS film is formed) flip curve includes: OTS The membrane is turned on at V _form during forward scanning (0→1→2), and disconnected at V _hold during reverse scanning (3→4→5); subsequent (2nd, 3rd...) The reversal curve includes: conduction at V _th during forward scanning (6→7→8), and reverse scanning is also (3→4→5). Note that the V _th of each of the subsequent (2nd, 3rd...) flips is basically close, while the V _form of the first (1st) flip is larger than the V _th of the subsequent (2nd, 3rd...) flips , that is, V _form >V _th . To distinguish them, the first flip is called forming (or firing), and the subsequent flip is called switching (including switch-ON and switch-OFF).

The forming process is considered a nuisance in 3D-XPoint. This is because each 3D-XPoint storage element needs to be initialized before use, that is, its state is converted with a larger V _form , so that its subsequent flipping voltage V _th is basically close. Due to the large number of 3D-XPoint storage elements (128Gb), this takes a long time. Therefore, the industry has been looking for an OTS film that does not require forming (forming-free). For example, Hennen et al. "Forming-free Mott-oxidethreshold selector nanodevice showing s-type NDR with endurance(>10^12cycles), excellent V _th stability(<5%), fast(<10ns) switching, and promising scaling properties", 2018 International Electron Device Meeting (IEDM) Technical Digest, pp.867-870.

OTS/OTP memory does not think the forming process of the OTS film is troublesome. Instead, the (first) forming process of the OTS film is used to realize the write operation of the memory element, and the (subsequent) switching process realizes the read operation of the memory element, thereby realizing a one-time programming memory (OTP) . The biggest advantage of OTS/OTP memory is that its OTS film not only has the function of gate film, but also has the function of storage film. Therefore, the OTS/OTP memory element does not need to contain a separate programming film at all. It is a single film structure (1S structure, S refers to the gate film), rather than the 1S1R structure of 3D-XPoint (S refers to the gate film, R refers to programming film). OTS/OTP memory cells have the advantages of simple structure, small aspect ratio, easy manufacture, and easy shrinkage.

Correspondingly, the present invention proposes a memory with an ultra-thin storage unit, which is characterized in that it includes: an ultra-thin storage unit (0X), and the ultra-thin storage unit (0X) includes: a first address line (10) and a first address line (10) Two address lines (20), the second address line (20) intersects with the first address line (10); the storage film (30) arranged between the first address line and the second address line ); the storage film (30) includes a layer of OTS film (30A), and the storage film (30) does not contain a separate programming film.

In addition to the above-mentioned three-dimensional horizontal memory (all address lines are horizontal), the present invention further proposes a three-dimensional vertical memory (1000), and its ultra-thin memory element (0Y) includes: a first address line (10); The storage hole (40) of the first address line (10); the storage film (30) formed on the side wall of the storage hole (40); located in the storage hole (40), covered by the storage film ( 30) the second address line (20) surrounded; the storage film (30) includes a layer of OTS film (30A), and the storage film (30) does not contain a separate PCM film (even, does not contain a separate programming film ).

The beneficial effects of the embodiments of the present application include:

The storage film is formed by one layer of OTS film and one layer of antifuse film, or only one layer of OTS film is needed, so the structure is simple, the thickness-to-width ratio of the storage film is reduced, and it is easy to manufacture and shrink.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the accompanying drawings used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, so It should be regarded as a limitation on the scope, and those skilled in the art can also obtain other related drawings based on these drawings without creative work.

Figure 1 shows a perspective view of a memory cell used in an interleaved array (prior art).

FIG. 2A is a cross-sectional view of a 3D-OTP; FIG. 2B is a cross-sectional view of a 3D-MTP (prior art).

Fig. 3A is a perspective view of an ultra-thin memory; Fig. 3B is a cross-sectional view of an ultra-thin memory element.

4A-4D are cross-sectional views of four ultra-thin memory cells.

Figure 5 is the I-V characteristic curve of a typical OTS film.

Figure 6 (Table 1) compares the performance parameters of various OTS films.

Fig. 7 is a cross-sectional view of an OTS/OTP memory cell.

Fig. 8 is a perspective view of a three-dimensional lateral ultrathin memory.

Figure 9 is a perspective view of a vertical memory cell.

Fig. 10 is a cross-sectional view of a three-dimensional vertical ultrathin memory.

Icon: 00 or 0X or 0Y-storage element; 10 or 10a or 10b or 01-first address line; 20 or 20a or 20b or 02-second address line; 03-gate film; 04-programming film; 01P- 02P-the lower surface of the second address line; 30 or 06-storage film; 10P-the first surface; 20P-the second surface; 1000-ultra-thin memory; 0X-ultra-thin storage element; 30A- OTS film; 30B-antifuse film; 30C-isolation film; 30D-interface isolation film; 0-substrate; 100-first storage layer; 200-second storage layer; 120v or 220v-channel hole; 0Y-longitudinal storage element; 40-storage hole; 16Z-storage string; 50-insulation medium.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of this application, not all of them. The components of the embodiments of the application generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations.

Accordingly, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the application. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

It should be noted that like numerals and letters denote similar items in the following figures, therefore, once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

In the description of this application, it should be noted that if the orientation or positional relationship indicated by the terms "upper", "lower", "inner", "outer" etc. appear, it is based on the orientation or positional relationship shown in the drawings, or It is the orientation or positional relationship that the product of the invention is usually placed in use, and it is only for the convenience of describing the application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation , and therefore cannot be construed as limiting the application.

In addition, terms such as "first" and "second" are used only for distinguishing descriptions, and should not be understood as indicating or implying relative importance.

It should be noted that, in the case of no conflict, the features in the embodiments of the present application may be combined with each other.

The present invention proposes a memory with an ultra-thin memory film (abbreviated as "ultra-thin memory"), which combines the anti-fuse film in 3-DOTP (Fig. 2A) with a very thin thickness T _M (generally <10nm) ) and the OTS film in 3D-XPoint ( FIG. 2B ), that is, the thickness T _S of the gate film 03 is relatively thin (generally ≤ 50nm), so as to realize an ultra-thin storage film. Its storage film 06 adopts OTS film as gate film 03, adopts antifuse film as programming film 04 (in the embodiment of Fig. 7 even does not need antifuse film), total thickness T is not more than 60nm, the width of address line F is not greater than 60nm. Even if F is shrunk to 10nm, the thickness-to-width ratio (T:F) of the storage film 06 is only 6:1, which is easy to manufacture. Note that the storage film 06 does not contain a separate PCM film in order not to increase its total thickness T. Given that its programming film 04 is an antifuse film, the ultra-thin memory is a one-time programming memory.

As shown in Figure 3A and Figure 3B, the ultrathin memory 1000 contains a plurality of first address lines (10a, 10b...) located on the same plane, the upper surface of which constitutes the first surface 10P; a plurality of second address lines located on another plane Lines (20a, 20b...), the lower surface of which forms the second surface 20P; the second address line (20a, 20b...) intersects the first address line (10a, 10b...). The memory film 30 is interposed between the first and second surfaces (10P, 20P) and coupled to the first and second address lines (10a, 10b; 20a, 20b). The storage film 30 includes an OTS film. Note that since the memory film 30 does not contain a separate PCM film (see FIG. 2B ), its total thickness T is not greater than 60 nm, which is easy to shrink.

4A-4D are four embodiments of the ultra-thin memory cell OX, the memory films 30 of which all contain an OTS film 30A and an antifuse film 30B. In order to obtain better interface properties, a layer of interface isolation material, such as carbon thin film, may be included around the OTS film 30A. The anti-fuse film 30B is a thin layer of insulating medium (such as silicon dioxide), which is in a high-resistance state before programming; under the programming voltage, the anti-fuse film is broken down and irreversibly enters a low-resistance state. Overall, the total thickness T of the memory film 30 is not greater than 60 nm.

In the embodiment of FIG. 4A , the antifuse film 30B can be directly deposited (such as by CVD or ALD) on the first address line 10, and can also be formed by directly depositing the metal surface in the first address line 10. Oxidation or nitriding generation (such as directly oxidizing or nitriding the upper surface of the metal electrode in the first address line). In the embodiment of FIG. 4B, the antifuse film 30B can be directly deposited (such as by CVD or ALD) on the OTS film 30A, or can be formed by oxidizing or nitriding the OTS film 30A (such as directly depositing the OTS Oxidation or nitriding of the upper surface of the single element tellurium in the film).

The embodiment of FIG. 4C further adds a barrier film 30C between the OTS film 30A and the antifuse film 30B. The isolation film 30C contains a conductive material, mainly to prevent the OTS film 30A from being affected by the high temperature effect when the antifuse film 30B is programmed. The antifuse film 30B can also be formed by directly oxidizing or nitriding the conductive material in the isolation film 30C besides the deposition method. In the embodiment of FIG. 4D , an interface isolation film 30D (such as carbon element) is added between the OTS film 30A and the antifuse film 30B and the first and second address lines 10 and 20 to improve interface performance.

In order to further reduce the total thickness T of the storage film, simplify the structure of the storage unit, and make the storage unit easier to shrink and manufacture, the present invention also proposes a kind of ultra-thin one-time programming memory based on the OTS film (abbreviated as "OTS/OTP memory") . It is based on the forming (or firing) properties of the OTS film. As shown in Figure 5, most of the OTS films exhibit a forming characteristic - when the current-voltage (IV) scan is performed on the OTS film, the first (the first time, referring to the first time after the OTS film is formed) flip curve includes: OTS The membrane is turned on at V _form during forward scanning (0→1→2), and disconnected at V _hold during reverse scanning (3→4→5); subsequent (2nd, 3rd...) The reversal curve includes: conduction at V _th during forward scanning (6→7→8), and reverse scanning is also (3→4→5). Note that the V _th of each of the subsequent (2nd, 3rd...) flips is basically close, while the V _form of the first (1st) flip is larger than the V _th of the subsequent (2nd, 3rd...) flips , that is, V _form >V _th . To distinguish them, the first flip is called forming (or firing), and the subsequent flip is called switching (including switch-ON and switch-OFF).

The forming process is considered a nuisance in 3D-XPoint. This is because each 3D-XPoint storage element needs to be initialized before use, that is, its state is converted with a larger V _form , so that its subsequent flipping voltage V _th is basically close. Due to the large number of 3D-XPoint storage elements (128Gb), this takes a long time. Therefore, the industry has been looking for an OTS film that does not require forming (forming-free). For example, Hennen et al. "Forming-free Mott-oxidethreshold selector nanodevice showing s-type NDR with endurance(>10^12cycles), excellent V _th stability(<5%), fast(<10ns) switching, and promising scaling properties", 2018 International Electron Device Meeting (IEDM) Technical Digest, pp.867-870.

Figure 6 (Table 1) compares the performance parameters of various OTS materials, which generally contain chalcogen elements (halcogen), such as Te group, Se group, S group (sulfide) and O group (oxide). A typical OTS material is chalcogenide glass, examples of which include: TiN/AsTeGeSiN/TiN (Sungho Kim et al, VLSI 2013, pp. T240-1). In addition, OTS materials (Shen et al, Science 374, pp.1390-1394, 2021) based on single elements (such as single element tellurium Te or single element antimony Sb) also have good performance. Since it contains a single element, the manufacturing process of the OTS material will be easier. For the single-element OTS film, among all the elements contained in the OTS film 30A, the mole ratio of a single element (such as the single element tellurium Te or the single element antimony Sb) exceeds 80%.

OTS/OTP memory does not think the forming process of the OTS film is troublesome. Instead, the (first) forming process of the OTS film is used to realize the write operation of the memory element, and the (subsequent) switching process realizes the read operation of the memory element, thereby realizing a one-time programming memory (OTP) . As shown in FIG. 7, the OTS/OTP memory cell OX includes first and second address lines 10, 20, and a memory film 30 interposed therebetween. The memory film 30 includes an OTS film 30A. The OTS film 30A has not only the function of a gate film but also the function of a memory film. Therefore, the OTS/OTP memory element 0X does not need to contain a separate programming film at all. It is a single film structure (1S structure, S refers to the gate film), rather than the 1S1R structure of 3D-XPoint (S refers to the gate film, R refers to the programming film). OTS/OTP memory cells have the advantages of simple structure, small aspect ratio, easy manufacture, and easy shrinkage. Similar to FIG. 4D , an interface isolation film 30D may also be included between the OTS film 30A and the first address line 10 and/or the second address line 20 . In order to ensure the necessary aspect ratio, in one embodiment, the total thickness T of the storage film 30 is not greater than 60nm; in another embodiment, the line width F of the first address line 10 or the second address line 20 is not greater than 60nm.

Three-dimensional memory can be divided into three-dimensional horizontal memory and three-dimensional vertical memory. All the address lines in the three-dimensional horizontal memory are horizontal address lines; the three-dimensional vertical memory contains at least one set of vertical address lines. As shown in FIG. 8 , the three-dimensional lateral ultra-thin memory 1000 includes a semiconductor substrate 0 (including transistors 0T and their interconnections 0M). A first storage layer 100 is stacked on a substrate 0 , and a second storage layer 200 is stacked on the first storage layer 100 . The address line is coupled with the substrate 0 through the contact via hole 120v and the via hole 220v. For details about the 3D lateral memory, please refer to the 3D ROM disclosed in US Pat. No. 5,835,396. The storage unit 0X of the three-dimensional horizontal memory is called a horizontal storage unit.

9 and 10 are three-dimensional vertical ultra-thin memory 1000 and its vertical storage element 0Y. As shown in FIG. 9 , the vertical memory cell 0Y has a horizontal first address line (horizontal address line) 10 . The memory hole 40 penetrates through the horizontal address line, that is, the first address line 10 . Afterwards, a storage film 30 is first formed on the wall of the storage hole 40 . Then, the conductive material is continuously filled in the storage hole 40 to form a vertical second address line (vertical address line) 20 . In this way, the memory film 30 is formed between the horizontal address lines, that is, the first address lines 10 and the vertical address lines 20 . Note that the memory film 30 contains an OTS film 30A, but does not contain a separate PCM film. In order to reduce the diameter of the memory hole 40, the total thickness T of the memory film 30 is preferably not greater than 60 nm. In another embodiment, memory film 30 does not contain a separate programming film.

The three-dimensional vertical ultrathin memory 1000 (FIG. 10) includes a substrate 0 (including transistors and their interconnections). Above this there are a number of horizontal address lines 10a-10h stacked vertically on top of each other. The horizontal address lines 10a-10h are separated by insulating medium 50. Memory holes 40 penetrate horizontal address lines 10a-10h. Afterwards, a storage film 30 (such as an OTS film 30A) is first formed on the side wall of the storage hole 40 . Then, the conductive material is continuously filled in the storage hole 40 to form a vertical address line, that is, the second address line 20 . In this way, the vertical address lines, that is, the second address lines 20, the memory film 30 and the horizontal address lines 10a-10h respectively form a plurality of vertical memory cells 0Ya-0Yh. These memory cells 0Ya-0Yh constitute a memory string 16Z. Compared with the storage hole of 3D-NAND containing 5 layers of films, the storage hole 40 of the three-dimensional vertical ultra-thin memory 1000 only contains 2 layers of films: the storage film 30 (such as the OTS film 30A) and the vertical address line, that is, the second address line 20 . Of course, in other embodiments of the present invention, the storage hole 40 may also contain an antifuse film or the like. Generally speaking, the three-dimensional vertical ultrathin memory 1000 has a simple structure, its storage holes 40 can be made smaller, the process is simpler, and the cost is lower.

The above is only a specific embodiment of the application, but the scope of protection of the application is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. All should be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims (10)

1. A memory with an ultra-thin storage element, characterized in that it comprises: an ultra-thin storage element (0X), and the ultra-thin storage element (0X) comprises: A first address line (10) and a second address line (20), the second address line (20) intersecting with the first address line (10); a storage film (30) disposed between the first address line (10) and the second address line (20); The storage film (30) includes: a layer of OTS film (30A) and a layer of antifuse film (30B), and the storage film (30) does not contain a separate PCM film; The total thickness of the storage film (30) is less than or equal to 60nm, and the width of the first address line (10) or the second address line (20) is less than or equal to 60nm. 2. The memory with ultra-thin storage element according to claim 1, characterized in that, the ultra-thin storage element (0X) has one of the following (A)-(F) characteristics: (A) the antifuse film (30B) is formed on the first address line (10) or the OTS film (30A) by deposition; (B) formed by oxidizing or nitriding the metal surface of the first address line (10); (C) formed by oxidizing or nitriding the upper surface layer of the OTS film (30A); (D) the storage film (30) further includes an isolation film (30C), and the isolation film (30C) is disposed between the OTS film (30A) and the antifuse film (30B); or (E) The storage film (30) further includes: an interface isolation film (30D), the interface isolation film (30D) is arranged on the OTS film (30A) and the first address line (10), and the between the antifuse film (30B) and the second address line (20); (F) The memory is a one-time program memory. 3. A memory with an ultra-thin storage element, characterized in that it comprises: an ultra-thin storage element (0X), and the ultra-thin storage element (0X) comprises: A first address line (10) and a second address line (20), the second address line (20) intersecting with the first address line (10); a storage film (30) disposed between the first address line and the second address line; The memory film (30) includes an OTS film (30A), and the memory film (30) does not contain a separate programming film. 4. The memory device with ultra-thin memory elements according to claim 3, characterized in that: the V _form of the OTS film (30A) is greater than V _th , wherein V _form is the first switching voltage, and V _th is the subsequent switching voltage . 5. The memory with ultra-thin storage element according to claim 3, characterized in that, the ultra-thin storage element (0X) has one of the following (G)-(J) characteristics: (G) The total thickness of the storage film (30) is less than or equal to 60nm; (H) the width of the first address line (10) or the second address line (20) is less than or equal to 60nm; (1) the storage film (30) also includes: an interface isolation film (30D), the interface isolation film (30D) is arranged on the OTS film (30A) and the first address line (10), and/ or between the OTS film (30A) and the second address line (20); (J) The memory is a one-time program memory. 6. A memory with an ultra-thin storage element, characterized in that it comprises: an ultra-thin storage element (0Y), and the ultra-thin storage element (0Y) comprises: first address line (10); a storage hole (40) penetrating through said first address line (10); a storage film (30) formed on the side wall of the storage hole (40); a second address line (20) located within the storage hole (40) surrounded by the storage film (30); The storage film (30) includes a layer of OTS film (30A), and the storage film (30) does not contain a separate PCM film. 7. A memory with an ultra-thin storage element, characterized in that it comprises: an ultra-thin storage element (0Y), and the ultra-thin storage element (0Y) includes: first address line (10); a storage hole (40) penetrating through said first address line (10); a storage film (30) formed on the side wall of the storage hole (40); a second address line (20) located within the storage hole (40) surrounded by the storage film (30); The memory film (30) includes an OTS film (30A), and the memory film (30) does not contain a separate programming film. 8. The memory device with ultra-thin storage elements according to claim 7, characterized in that: V _form of the OTS film (30A) is greater than V _th , wherein V _form is the first switching voltage, and V _th is the subsequent switching voltage . 9. The memory with ultra-thin memory elements according to any one of claims 1-8, characterized in that the OTS film (30A) contains chalcogen. 10. A memory with an ultra-thin storage element, comprising: A substrate (0), and the ultra-thin storage element according to any one of claims 1-9; A plurality of ultra-thin storage elements are vertically stacked on the substrate to form a three-dimensional memory.

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