CN114447024A - Gating device, storage and preparation method thereof - Google Patents

Abstract

The embodiment of the invention discloses a gate, which comprises: a gate layer of a material comprising two-dimensional Bi₂O₂X material, wherein X is selected from at least one of S, Se and Te. The invention adopts two-dimensional Bi₂O₂The X material is used as a gate layer, the function of the gate layer is realized by using the unipolar resistance change behavior of the X material in the out-of-plane direction, and the good bidirectional conduction characteristic can be realized. Due to the characteristics of the two-dimensional material, the depth-to-width ratio of the device can be well reduced, thereby being beneficial to the high density of the device. Bi of another two dimensions₂O₂The X material itself has insulating properties and has a low leakage current in the off state. Meanwhile, the performance of the device can be controlled by adjusting oxygen vacancies and X vacancies in the material, and the gating layer has better regulation freedom degree.

Description

A kind of gate, memory and preparation method thereof

technical field

The present invention relates to the technical field of semiconductors, and in particular, to a gate, a memory and a preparation method thereof.

Background technique

The gate is an important digital circuit structure, and it is also an important component of many devices such as field programmable gate array (FPGA) and memory (Memory), which directly affects the performance of the device such as speed and power consumption. Three-dimensional (3D) memory using gating is a memory device for storing information in modern information technology, and it is very promising in terms of ultra-high integration density. However, leakage paths in 3D memory reduce its performance, increase overall power consumption, and limit the size of 3D memory. With the gradual increase of storage density, how to optimize and improve the gate, and how to apply the gate to the three-dimensional memory performance has become an important research direction in this field.

SUMMARY OF THE INVENTION

In view of this, the embodiments of the present invention provide a gate, a memory and a preparation method thereof to solve at least one problem existing in the background art.

In order to achieve the above object, the technical scheme of the present invention is achieved in this way:

An embodiment of the present invention provides a gate, the gate includes: a gate layer, the material of the gate layer includes a two-dimensional Bi ₂ O ₂ X material, wherein X is selected from S, Se, and Te at least one of.

In the above solution, the material of the gate layer includes two-dimensional Bi ₂ O ₂ Se material.

In the above solution, the threshold voltage of the gate layer is less than 4V.

In the above solution, the thickness of the gate layer is less than 10 nm.

An embodiment of the present invention further provides a memory, where the memory includes the gater described in the above solution.

In the above solution, the memory includes:

a first conductive line extending in a first direction;

a gate layer stacked on the first conductive line and extending along a first direction, the gate layer is the layered gate;

a second conductive line extending along a second direction, the first direction intersecting the second direction;

A memory cell located between the gate layer and the second conductive line and extending along a third direction, the third direction being perpendicular to the first direction and the second direction.

The embodiment of the present invention also provides a preparation method of a gate, comprising:

A gate layer is formed, the gate layer includes a two-dimensional Bi ₂ O ₂ X material, and the X is selected from at least one of S, Se, and Te.

In the above solution, the material of the gate layer includes two-dimensional Bi ₂ O ₂ Se material.

In the above solution, the threshold voltage of the gate layer is less than 4V.

In the above solution, the thickness of the gate layer is less than 10 nm.

An embodiment of the present invention also provides a method for preparing a memory, including:

forming a first conductive wire material layer, the first conductive wire material layer being used to form a first conductive wire extending along a first direction;

A gate material layer and a memory cell material layer stacked in a third direction are formed on the first conductive wire material layer, the gate material layer includes a two-dimensional Bi ₂ O ₂ X material, and X is selected from S , at least one of Se, Te, the gate material layer and the memory cell material layer are used to form the gate layer and the memory cell;

forming a second conductive line extending along the second direction on the storage unit; wherein,

The first direction and the second direction intersect, and the third direction is perpendicular to the first direction and the second direction.

In the above solution, the gate material layer and the memory cell material layer are used to form the gate layer and the memory cell, including:

The gate material layer and the memory cell material layer are used to form a gate layer and a plurality of memory cells, and the plurality of memory cells are located on the same gate layer.

In the embodiment of the present invention, two-dimensional Bi ₂ O ₂ X material is used as the gate layer, and the function of the gate layer is realized by the unipolar resistive switching behavior in the out-of-plane direction, which can achieve good bidirectional conduction characteristics. Due to the characteristics of two-dimensional materials, the aspect ratio of the device can be well reduced, which is beneficial to the high density of the device. In addition, the two-dimensional Bi ₂ O ₂ X material itself has insulating properties and has lower leakage current in the off-state. At the same time, the device performance can be controlled by adjusting the oxygen vacancies and X vacancies in the material, and the gate layer has a better degree of freedom in regulation.

Additional aspects and advantages of the present invention will be set forth, in part, from the following description, and in part will be apparent from the following description, or may be learned by practice of the invention.

Description of drawings

1 is a schematic structural diagram of a memory in the related art;

FIG. 2 is a schematic structural diagram of a memory provided by an embodiment of the present invention;

FIG. 3 is a schematic diagram of the conduction principle of the two-dimensional Bi ₂ O ₂ X material;

4 is a schematic structural diagram of a memory provided by another embodiment of the present invention;

5 is a schematic flowchart of a method for preparing a memory according to an embodiment of the present invention;

6a to 6f are schematic structural diagrams of a memory provided in an embodiment of the present invention in a manufacturing process.

Reference number:

110-bit line; 111-word line; 112-strobe layer; 113-memory cell;

210-first conductive wire; 210'-first conductive wire material layer; 211-second conductive wire; 211'-second conductive wire material layer; 212-gate layer; 212'-gate material layer; 213- memory cell; 213'-memory cell material layer; 213"-memory cell structure; 221-first electrode layer; 221'-first electrode material layer; 222-memory layer; 222'-memory material layer; 223-th Two electrode layers; 223'-the second electrode material layer;

Substrate-310; _Two -dimensional _Bi2O2X material-311; Hill-like structure-312.

Detailed ways

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that the present invention will be more thoroughly understood, and will fully convey the scope of the present disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other instances, some technical features that are well known in the art have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and constructions are not described in detail.

In the drawings, the sizes of layers, regions, elements, and their relative sizes may be exaggerated for clarity. The same reference numbers refer to the same elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on the other elements or layers , adjacent thereto, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. The discussion of a second element, component, region, layer or section does not imply that the first element, component, region, layer or section is necessarily present of the invention.

Spatial relational terms such as "under", "below", "under", "under", "above", "above", etc., are used herein for convenience Description is used to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "compose" and/or "include", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

As used in the description below, the term "three-dimensional memory" refers to a semiconductor device having memory cells arranged vertically on a laterally oriented substrate such that the number of memory cells is vertically opposite increased on the substrate. As used herein, the term "vertical/perpendicular" means nominally perpendicular to the lateral surface of the substrate.

As shown in FIG. 1 , in the related art, the three-dimensional memory is mainly a three-dimensional cross-point structure, in which the gate layer 112 and the memory cell 113 are located in the bit line (BL) 110 and the word line ( WL) at the intersection of 111. For phase change memory, resistive memory and magnetic random access memory based on the cross-point structure, the leakage current problem in the cross-point array is the main obstacle to the realization of high-density integration. Layers are important for realizing high-density three-dimensional crossbar array integration of the above-mentioned memories. For advanced gate layer materials, it is not only required to have a good on-off ratio, that is, a large on-state resistance to meet the needs of large operating currents, and a low off-state resistance to meet the needs of small leakage currents, but also require The gate layer material has good fatigue properties, that is, the number of repeated switching must match the fatigue properties of the storage material, otherwise the stored information will be lost and the device will fail. In addition, the continuous evolution of advanced process nodes also requires our gate layer to be as thin and small as possible. In addition, the requirement for the gate layer is that its switching speed should be as fast as possible, otherwise the operation speed of the device will be affected.

The current 1S1R (one-to-one resistor) phase-change memory or resistive-change memory all use bidirectional threshold switching (OTS, Ovonic threshold switching) as the gate layer unit, but the OTS gate layer unit has high thickness and large leakage current. , The disadvantage of high threshold voltage.

Based on this, an embodiment of the present invention provides a gate, as shown in FIG. 2 , the gate includes: a gate layer 212 , and the material of the gate layer 212 includes a two-dimensional Bi ₂ O ₂ X material , wherein X is selected from at least one of S, Se, and Te.

An embodiment of the present invention further provides a memory including the gate of the above solution. As shown in FIG. 2 , the memory includes: a first conductive line 210 extending along a first direction; The gate layer 212 on the conductive line 210 and extending along the first direction, the gate layer 212 is the layered gate; the second conductive line 211 extending along the second direction, the first direction and the The second direction intersects; the memory cell 213 is located between the gate layer 212 and the second conductive line 211 and extends along a third direction, the third direction is perpendicular to the first direction and all the second direction.

In actual operation, the first conductive lines 210 and the second conductive lines 211 can be used as word lines and bit lines, respectively. For example, when the first conductive line 210 is a word line, the second conductive line 211 is a bit line, and when the first conductive line 210 is a bit line, the second conductive line 211 is a word line. The first conductive lines 210 and the second conductive lines 211 may be formed of 20nm/20nm equal-width (line/space, L/S) conductive lines formed after the patterning process. The materials of the first conductive lines and the second conductive lines may include conductive materials including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, Doped silicon, silicide, or any combination thereof. In some specific embodiments, the material of the first conductive wire and the second conductive wire is tungsten.

In some embodiments, the first direction and the second direction may be perpendicular to each other.

In the embodiment of the present invention, two-dimensional Bi ₂ O ₂ X material is used as the gate layer, and the function of the gate layer is realized by the unipolar resistive switching behavior in the out-of-plane direction, which can achieve good bidirectional conduction characteristics. Due to the characteristics of two-dimensional materials, the aspect ratio of the device can be well reduced, which is beneficial to the high density of the device. In addition, the two-dimensional Bi ₂ O ₂ X material itself has insulating properties and has lower leakage current in the off-state. At the same time, the device performance can be controlled by adjusting the oxygen vacancies and X vacancies in the material, and the gate layer has a better degree of freedom in regulation.

In some embodiments, the material of the gate layer includes a two-dimensional Bi ₂ O ₂ Se material.

FIG. 3 is a schematic diagram of the conduction principle of the two-dimensional Bi ₂ O ₂ X material. As shown in FIG. 3 , a two-dimensional Bi ₂ O ₂ X material 311 is deposited on the surface of the substrate 310 , and the material of the substrate can be, for example, SiO ₂ /Si, a vertical electric field is formed in the local area of the two-dimensional Bi ₂ O ₂ X material 311 . The two-dimensional Bi ₂ O ₂ X material 311 has unique out-of-plane electrical properties at the nanoscale, that is, under the action of the vertical electric field, the surface of the two-dimensional Bi ₂ O ₂ X material 311 will form nano-scale mountains along the direction of the electric field. The hill-like structure 312, these unique changes in the nanoscale atomic structure will make the energy band structure of the electrons in this region undergo huge bending, thereby realizing the nano-conducting channel, making the originally insulating two-dimensional Bi ₂ O ₂ X material 311 in the The out-of-plane local area conduction along the electric field direction achieves good resistive switching behavior. As the electric field is removed, these formed hill-like structures 312 rapidly recover, returning to the original state. This conduction behavior of the two-dimensional Bi ₂ O ₂ X material 311 is independent of the direction of the electric field, similar to the OTS device, and can achieve good bidirectional conduction characteristics. And compared with OTS, due to the characteristics of the two-dimensional material itself, it can achieve a thickness of several atomic layers, so for the device, its aspect ratio can be well reduced, which is conducive to the high density of the device. In addition, the two-dimensional Bi ₂ O ₂ X material 311 material itself has insulating properties. When the electric field strength is higher than a certain threshold, that is, when a hill-like atomic structure is formed, the conduction path will be formed. Therefore, in the off state, the gate layer of this material will have lower leakage current. Only through the control at the atomic level, the effective control of device performance can be achieved. In addition to the participation of electrons in conduction, the dynamic balance between the movement of oxygen vacancies and X (S, Se, or Te) vacancies under the action of the electric field and the generation of Joule heating jointly contribute to the conduction process of the gate layer in the open state, so this The seed gating layer has better control freedom.

In some embodiments, the threshold voltage of the gate layer is less than 4V, for example, 3.5V, 2.5V, 1.5V. The current OTS gate layer realizes the on-state current according to the transition of electrons between the charge traps (charge traps), but due to the single carrier and the limitation of the trap (trap) density, the general on-state current is too low, so it is difficult to improve the performance. high drive current. For the current OTS gate layer, the threshold voltage is relatively high, usually higher than 4V, so the selection and design of peripheral circuits also bring a lot of trouble. In addition, the high turn-on voltage also brings huge The impact of the inrush current makes our operation of the device uncontrollable. In this scheme, a two-dimensional Bi ₂ O ₂ X material is used as the gate layer, which can achieve stable on/off performance at a lower threshold voltage and increase the design freedom of the device.

In some embodiments, the thickness of the gate layer is less than 10 nm, for example, 7 nm, 4 nm, 2 nm. The conventional OTS gate layer needs to ensure a certain thickness to meet the requirement of low leakage, otherwise the leakage of the device will increase, which not only brings about the problem of misoperation, but also greatly increases the power consumption of the device. At the same time, due to the limitation of the aspect ratio, it will be difficult to continue to reduce the size of the 1S1R memory based on the OTS gate layer, otherwise it will bring huge challenges to the process. This scheme uses two-dimensional Bi ₂ O ₂ X material as the gate layer. Due to the characteristics of the two-dimensional material itself, it can achieve a thickness of several atomic layers, so for the device, its depth and width can be well reduced. ratio, thus facilitating the high density of the device. At the same time, the device performance can be effectively regulated only through the regulation at the atomic level.

In some embodiments, the Bi ₂ O ₂ X material includes oxygen vacancies and X (X is selected from at least one of S, Se, Te) vacancies. Exemplarily, the concentration of the oxygen vacancies is greater than 0.02 and less than 0.2, and the concentration of the X vacancies is greater than 0.01 and less than 0.1. The concentration of oxygen vacancies and X vacancies is too high, too high defects will lead to the decline of the performance of 2D _Bi2O2X materials, and the concentrations of oxygen _vacancies and X vacancies are too low, which is not conducive to improving the plane of _{2D Bi2O2X} materials Outward direction electrical properties. The originally insulating two-dimensional Bi ₂ O ₂ X material conducts in a local area outside the plane along the direction of the electric field. In addition to the participation of electrons in conduction, the dynamic balance between the movement of oxygen vacancies and Se vacancies under the action of the electric field and the generation of Joule heat , which together contribute to the conduction process of the gate layer in the open state, so this gate layer has a better degree of freedom in regulation. In practical operation, parameters such as the threshold voltage of the gate layer, on-off ratio, and electrical conductivity can be adjusted by oxygen vacancies and X vacancies.

In some embodiments, as shown in FIG. 2 , the storage unit 213 includes a first electrode 221 , a storage layer 222 and a second electrode 223 that are sequentially stacked and distributed along a third direction, wherein the storage layer 222 includes a phase Change memory material or resistive change memory material. The materials of the first electrode 221 and the second electrode include metal materials or carbon-containing materials, the metal materials include but are not limited to tungsten or titanium, and the carbon-containing materials include but are not limited to amorphous carbon, carbon nanotubes or graphene etc. In some embodiments, the thickness of the first electrode 221 and the second electrode may be 10-50 nm, for example, 12 nm, 18 nm, and the like. The first electrode 221 and the second electrode 223 are respectively connected to the gate layer 212 and the second conductive line 211 , and the gate layer 212 is based on the voltage on the first conductive line 210 and the second conductive line 211 Signals that drive the storage layer to complete data storage or erasing. The phase change memory material includes a chalcogenide based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or any other suitable phase change material. The resistive memory materials include, but are not limited to, HfOx, AlOx, TaOx, etc., or any other suitable resistive materials.

In some embodiments, as shown in FIG. 4 , the memory includes: a plurality of memory cells 213 , and the plurality of memory cells 213 are located on the same gate layer 212 . The traditional OTS gate layer is in one-to-one correspondence with the memory cells, and each gate layer drives the data storage or erasing of one memory cell. When preparing the OTS gate layer, the OTS gate material layer needs to be formed first, and then an additional etching process is performed to form a single OTS gate layer. On the one hand, the etching process increases the cost and will cause pollution or other damage to the device. On the other hand, if the adjacent OTS gate layers are too close together, unnecessary crosstalk will be caused. In the embodiment of the present disclosure, a two-dimensional Bi ₂ O ₂ X material is used as the gate layer, and the function of the gate layer is realized by using its unipolar resistive switching behavior in the out-of-plane direction, and the gate layer can be formed in one step without additional etching. and has unique electrical properties in the out-of-plane direction, so that conduction can be achieved in the area where there is a vertical electric field locally, and other areas remain insulated, and a two-dimensional Bi ₂ O ₂ X gate layer plane can be in the vertical direction. A plurality of memory cells are driven up, which increases the integration level of the device.

In some embodiments, the memory further includes: an isolation structure (not shown in the figure), the isolation structure is located between adjacent memory cells for electrically isolating the adjacent memory cells. The isolation structure includes, but is not limited to, one of silicon oxide, silicon oxynitride, and silicon nitride, or a combination thereof.

An embodiment of the present disclosure also provides a method for preparing a gate, the preparation method comprising: forming a gate layer, the gate layer comprising a two-dimensional Bi ₂ O ₂ X material, and the X is selected from S, Se , at least one of Te. The formation method of the gate layer includes, but is not limited to, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process, or a combination thereof.

An embodiment of the present disclosure further provides a method for preparing a memory, and FIG. 5 is a schematic flowchart of the method for preparing a memory according to an embodiment of the present invention. As shown in Figure 5, the method includes:

Step 501 , forming a first conductive wire material layer, where the first conductive wire material layer is used to form a first conductive wire extending along a first direction;

Step 502 , forming a gate material layer and a memory cell material layer stacked in a third direction on the first conductive wire material layer, where the gate material layer includes a two-dimensional Bi ₂ O ₂ X material, and the X At least one selected from S, Se, and Te, the gate material layer and the memory cell material layer are used to form the gate layer and the memory cell;

Step 503 , forming a second conductive line extending along the second direction on the storage unit; wherein, the first direction intersects the second direction, and the third direction is perpendicular to the first direction and the second direction. the second direction.

In some embodiments, the gate layer includes a two-dimensional Bi ₂ O ₂ Se material.

Hereinafter, with reference to the schematic structural diagrams of the memory during the preparation process in FIGS. 6a to 6f, the memory and the preparation method thereof provided by the embodiments of the present invention will be further described in detail.

The method starts at step 501, as shown in Fig. 6a, forming a first conductive wire material layer 210' for forming a first conductive wire 210 extending in a first direction.

In actual operation, the substrate 310 may be provided first, and the substrate is located below the process execution surface, so as to provide support for the process. Here, the substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (eg, silicon (Si) substrate, germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II - VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

Then, a first conductive wire material layer 210 ′ is formed on the substrate 310 . The material of the first conductive wire may include conductive materials, and the conductive materials include but are not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, suicide, or any combination thereof.

Next, step 502 is performed, referring to FIGS. 6b to 6d , a gate material layer 212 ′ and a memory cell material layer 213 ′ stacked in a third direction are formed on the first conductive wire material layer 210 ′. The gate material layer 212' includes a two-dimensional Bi ₂ O ₂ X material, and the X is selected from at least one of S, Se, and Te, for example, including but not limited to a two-dimensional Bi ₂ O ₂ Se material, the gate The material layer 212 ′ and the memory cell material layer 213 ′ are used to form the gate layer 212 and the memory cell 213 .

Specifically, first, referring to FIG. 6b, a gate material layer 212' is formed on the first conductive wire material layer 210'. In actual operation, the formation process of the gate material layer 212' includes but is not limited to chemical vapor phase Deposition (CVD) process, plasma enhanced chemical vapor deposition (PECVD) process, atomic layer deposition (ALD) process, or a combination thereof.

In some embodiments, after forming the gate material layer, the method further includes: annealing the gate material layer in a vacuum or a reducing atmosphere. The reducing atmosphere may be, for example, H ₂ . The oxygen vacancy and X (X is selected from at least one of S, Se, and Te) vacancy concentrations of the two-dimensional Bi ₂ O ₂ X material are increased by annealing in a vacuum or reducing atmosphere. The originally insulating two-dimensional Bi ₂ O ₂ X material conducts in a local area outside the plane along the direction of the electric field. In addition to the participation of electrons in conduction, the dynamic balance between the movement of the oxygen vacancies and the X vacancies under the action of the electric field and the generation of Joule heat , which together contribute to the conduction process of the gate layer in the open state, so this gate layer has a better degree of freedom in regulation. In practical operation, parameters such as the threshold voltage of the gate layer, on-off ratio, and electrical conductivity can be adjusted by oxygen vacancies and X vacancies. Specifically, the concentration of the oxygen vacancies is greater than 0.02 and less than 0.2, and the concentration of the X vacancies is greater than 0.01 and less than 0.1. The concentration of oxygen vacancies and X vacancies is too high, too high defects will lead to the decline of the performance of 2D Bi ₂ O ₂ X materials, and the concentrations of oxygen vacancies and X vacancies are too low to improve the performance of 2D Bi ₂ O ₂ X Electrical properties of materials in out-of-plane directions.

Next, referring to FIG. 6c, a memory cell material layer 213' is formed on the gate material layer 212'. In some embodiments, the memory cell material layer 213' includes a first electrode material layer 221', a memory material layer 222' and a second electrode material layer 223' that are sequentially stacked and distributed along a third direction, wherein the memory The material layer 222' includes a phase change memory material or a resistive change memory material. The first electrode material layer 221', the storage material layer 222' and the second electrode material layer 223' are used to form the first electrode layer 221, the storage layer 222 and the second electrode layer 223, respectively.

The materials of the first electrode material layer 221 ′ and the second electrode material layer 223 ′ include metal materials or carbon-containing materials, the metal materials include but are not limited to tungsten or titanium, and the carbon-containing materials include but are not limited to Amorphous carbon, carbon nanotubes or graphene, etc. In some embodiments, the thickness of the first electrode material layer 221' and the second electrode material layer 223' may be 10-50 nm, for example, 12 nm, 18 nm, and the like.

The phase change memory material includes a chalcogenide based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or any other suitable phase change material. The resistive memory materials include, but are not limited to, HfOx, AlOx, TaOx, etc., or any other suitable resistive materials.

The first electrode 221 and the second electrode 223 are respectively connected to the gate layer 212 and the second conductive line 211 , and the gate layer is based on the voltage signals on the first conductive line 210 and the second conductive line 211 . , which drives the storage layer to complete data storage or erasure.

Next, as shown in FIG. 6d, the memory cell material layer 213', the gate material layer 212' and the first electrode material layer 210' are etched along a first direction, the first electrode material The layer 210 ′ becomes the first conductive line 211 extending along the first direction, the gate material layer 212 ′ becomes the gate layer 212 , and the memory cell material layer 213 ′ becomes the memory cell structure 213 ″.

Finally, step 503 is performed, as shown in FIG. 6e and FIG. 6f, to form a second conductive line 211 on the storage unit 213 extending along a second direction; wherein the first direction and the second The directions intersect, and the third direction is perpendicular to the first direction and the second direction.

Specifically, first, as shown in FIG. 6e, a second conductive wire material layer 211' extending along the second direction is formed on the memory cell structure 213''.

The material of the second conductive wire material layer 211' may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon , silicide, or any combination thereof.

Next, the second conductive wire material layer 211 ′ and the memory cell structure 213 ″ are etched along the second direction, and the second conductive wire material layer 211 ′ becomes the second conductive wire 211 extending along the second direction , the storage unit structure 213 ″ becomes the storage unit 213 . Specifically, the first electrode material layer 221', the storage material layer 222' and the second electrode material layer 223' respectively become the first electrode layer 221, the storage layer 222 and the second electrode layer 223.

In actual operation, before forming the second conductive wire material layer 211', a filling material may also be used to fill the gaps between the memory cell structures 213''.

In some embodiments, as shown in FIG. 6f, the gate material layer 212' and the memory cell material layer 213' are used to form the gate layer 212 and the memory cell 213, including: the gate material layer 212' and the memory cell material layer 213 ′ is used to form a gate layer 212 and a plurality of memory cells 213 , and the plurality of memory cells 213 are located on the same gate layer 212 . In actual operation, as shown in FIGS. 6e and 6f , a second conductive wire material layer 211 ′ extending along the second direction is formed on the memory cell structure 213 ″, and the second conductive line material layer 211 ′ is etched along the second direction The conductive wire material layer 211 ′ and the memory cell structure 213 ″. At this time, the etching process does not need to penetrate through the gate layer 212, for example, the surface of the gate layer 212 can be used as an etch stop layer or an etch stop layer. The traditional OTS gate layer is in one-to-one correspondence with the memory cells, and each gate layer drives the data storage or erasing of one memory cell. When preparing the OTS gate layer, the OTS gate material layer needs to be formed first, and then an additional etching process is performed to form a single OTS gate layer. On the one hand, the etching process increases the cost and will cause pollution or other damage to the device. On the other hand, if the adjacent OTS gate layers are too close together, unnecessary crosstalk will be caused. By using the two-dimensional Bi ₂ O ₂ Se material as the gate layer, the function of the gate layer can be realized by using its unipolar resistive switching behavior in the out-of-plane direction, and the gate layer can be formed in one step without additional etching process; and It has unique electrical properties in the out-of-plane direction, that is, conduction can be achieved in the region where a vertical electric field exists locally, and other regions remain insulated. A two-dimensional Bi ₂ O ₂ Se gate layer plane can drive multiple A memory unit increases the integration level of the device.

In some embodiments, the method further includes: forming an isolation structure (not shown in the figure), the isolation structure is located between the adjacent memory cells 213 for electrically isolating the adjacent memory cells 213 . The isolation structure includes, but is not limited to, one of silicon oxide, silicon oxynitride, and silicon nitride, or a combination thereof.

In some embodiments, the threshold voltage of the gate layer is less than 4V, for example, 3.5V, 2.5V, 1.5V. The current OTS gate layer realizes the on-state current according to the transition of electrons between the charge traps (charge traps), but due to the single carrier and the limitation of the trap (trap) density, the general on-state current is too low, so it is difficult to improve the performance. high drive current. For the current OTS gate layer, the threshold voltage is relatively high, usually higher than 4V, so the selection and design of peripheral circuits also bring a lot of trouble. In addition, the high turn-on voltage also brings huge The impact of the inrush current makes our operation of the device uncontrollable. In this scheme, a two-dimensional Bi ₂ O ₂ X material is used as the gate layer, which can achieve stable on/off performance at a lower threshold voltage and increase the design freedom of the device.

In some embodiments, the thickness of the gate layer is less than 10 nm, for example, 7 nm, 4 nm, 2 nm. The conventional OTS gate layer needs to ensure a certain thickness to meet the requirement of low leakage, otherwise the leakage of the device will increase, which not only brings about the problem of misoperation, but also greatly increases the power consumption of the device. At the same time, due to the limitation of the aspect ratio, it will be difficult to continue to reduce the size of the 1S1R memory based on the OTS gate layer, otherwise it will bring huge challenges to the process. This scheme uses two-dimensional Bi ₂ O ₂ X material as the gate layer. Due to the characteristics of the two-dimensional material itself, it can achieve a thickness of several atomic layers, so for the device, its depth and width can be well reduced. ratio, thus facilitating the high density of the device. At the same time, the device performance can be effectively regulated only through the regulation at the atomic level.

To sum up, in the embodiment of the present invention, the two-dimensional Bi ₂ O ₂ X material is used as the gate layer, and the function of the gate layer is realized by the unipolar resistive switching behavior in the out-of-plane direction, and good bidirectional conduction can be realized. characteristic. Due to the characteristics of two-dimensional materials, the aspect ratio of the device can be well reduced, which is beneficial to the high density of the device. In addition, the two-dimensional Bi ₂ O ₂ X material itself has insulating properties and has lower leakage current in the off-state. At the same time, the device performance can be controlled by adjusting the oxygen vacancies and X vacancies in the material, and the gate layer has a better degree of freedom in regulation.

It should be noted that the gate, the preparation method of the gate, the memory using the gate, and the preparation method of the memory provided by the present disclosure belong to the same concept; the gate and the gate provided by the embodiments of the present disclosure The fabrication method and the memory and the fabrication method of the memory can be applied to any integrated circuit including the structure. The technical features in the technical solutions described in the embodiments can be combined arbitrarily unless there is a conflict. Those skilled in the art can change the order of the steps of the above-mentioned formation method without departing from the protection scope of the present disclosure. If the steps in the embodiments of the present disclosure do not conflict, some of the steps may be executed simultaneously, or they may be executed sequentially. .

The above are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included in the within the protection scope of the present invention.

Claims (12)

1. A gate, comprising:

a gate layer of a material comprising two-dimensional Bi₂O₂X material, wherein X is selected from at least one of S, Se and Te.

2. The gate of claim 1, wherein the material of the gate layer comprises Bi in two dimensions₂O₂A Se material.

3. The gate of claim 1, wherein the threshold voltage of the gate layer is less than 4V.

4. The gate of claim 1, wherein the gate layer has a thickness of less than 10 nm.

5. A memory, characterized in that it comprises a gate according to any one of claims 1 to 4.

6. The memory of claim 5, comprising:

a first conductive line extending in a first direction;

a gate layer stacked on the first conductive line and extending in a first direction, the gate layer being the gate in a layer shape;

a second conductive line extending along a second direction, the first direction intersecting the second direction;

a memory cell between the pass layer and the second conductive line and extending along a third direction, the third direction being perpendicular to the first direction and the second direction.

7. A method of fabricating a gate, comprising:

forming a gate layer comprising two-dimensional Bi₂O₂X is selected from at least one of S, Se and Te.

8. The method of claim 7, wherein the material of the gate layer comprises Bi in two dimensions₂O₂A Se material.

9. The method of claim 7, wherein the gate layer has a threshold voltage of less than 4V.

10. The method of claim 7, wherein the thickness of the gate layer is less than 10 nm.

11. A method of fabricating a memory, comprising:

forming a first conductive line material layer for forming a first conductive line extending in a first direction;

forming a gate material layer and a memory cell material layer stacked in a third direction on the first conductive line material layer, the gate material layer including two-dimensional Bi₂O₂The X material is selected from at least one of S, Se and Te, and the gate material layer and the memory cell material layer are used for forming a gate layer and a memory cell;

forming a second conductive line extending in a second direction on the memory cell; wherein,

the first direction intersects the second direction, and the third direction is perpendicular to the first direction and the second direction.

12. The method of claim 11, wherein the gate material layer and the memory cell material layer are used to form a gate layer and a memory cell, and the method comprises:

the gate material layer and the memory cell material layer are used for forming a gate layer and a plurality of memory cells, and the plurality of memory cells are located on the same gate layer.

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