CN101976677B - ZnO Schottky diode-based phase-change random access memory array and manufacturing method - Google Patents

Abstract

The invention discloses a phase change random access memory array based on a ZnO Schottky diode and a manufacturing method thereof. The structure includes: a semiconductor substrate; an insulating buffer layer on the semiconductor substrate; a plurality of word lines on the insulating buffer layer; a plurality of ZnO Schottky diodes electrically connected to the word line, and a second conductor layer respectively located above each ZnO Schottky diode; phase change memory layers respectively located on each second conductor layer; and the ZnO Schottky diode is composed of a first conductor layer and an n-type ZnO polycrystalline film. The invention adopts the ZnO Schottky diode formed by the n-type ZnO polycrystalline film and the metal layer as the gating element, so that the phase change memory has higher density, lower power consumption and higher performance.

Description

ZnO Schottky diode-based phase-change random access memory array and manufacturing method

technical field

The invention belongs to the technical field of semiconductors, and relates to a phase-change random access memory (PCRAM) and a manufacturing method thereof, in particular to a high-density phase-change random access memory array based on ZnO Schottky diode gating formed at a low temperature and a manufacturing method thereof .

Background technique

Phase-change random storage technology is based on Ovshinsky's research in the late 1960s (Phys. Rev. Lett., 21, 1450-1453, 1968) and early 1970s (Appl. Phys. Lett., 18, 254-257, 1971) The proposed phase-change thin film can be applied to the idea of phase-change storage media, and it is an electric storage device with low cost, high speed, high storage density, simple manufacturing process and stable performance, and its preparation is similar to that of existing Compatibility with standard CMOS processes has drawn worldwide attention.

The basic principle of phase change random access memory (referred to as PCRAM) is to use electric pulse signals to act on the device unit electrodes to make phase change materials undergo reversible phase transitions between amorphous and polycrystalline states. By distinguishing the high resistance value of the amorphous state With the low resistance value of the polycrystalline state, the storage of "0" and "1" states is realized, thereby completing the writing, erasing and reading operations of information. Due to the advantages of high-speed reading, high cycle times, non-volatility, small device size, low power consumption, strong vibration resistance and radiation resistance, phase change RAM is considered by the International Semiconductor Industry Association to be the most likely to replace the current flash memory And it will become the mainstream product of memory in the future, especially in the fields of national defense and aerospace, which has great application prospects.

During the electrical operation of the phase-change random access memory unit, it is generally believed that during the SET (setting) process (corresponding to crystallization), a low and wide electric pulse is applied to heat the phase-change material. When the temperature of the material When it is higher than the crystallization temperature (650K) but lower than the melting temperature (893K), the phase change material will crystallize, thus forming a polycrystalline state with a lower resistance value; and during the RESET (reset) process (corresponding to Amorphization), you need to apply a high and narrow electric pulse for heating, so that the temperature of the material is higher than the melting temperature of the phase change material to break the original chemical bonds in the polycrystalline material, followed by a quenching process of quenching ( The cooling rate reaches 1011K/s), so that the atoms in the material have no time to re-bond and arrange, forming an amorphous state with short-range order and long-range disorder, and this amorphous state has a high resistivity compared with the polycrystalline state. The value is high. Phase-change random access memory is to use the difference between the high and low resistance values of the amorphous state and the polycrystalline state that can be reversibly changed to realize the storage of data "0" and "1". In the process of reading (READ), the electric pulse is very weak and the time is very short, which is not enough to cause any phase change in the phase change material, so the information stored in it will not be destroyed.

At present, most of the institutions engaged in the research and development of phase change random access memory in the world are large companies in the semiconductor industry (Ovonyx, Intel, Samsung, IBM and AMD, etc.), and their focus is on how to realize the commercialization of phase change random access memory as soon as possible. superior. Among them, the realization of high-density, high-speed mass storage array is the research direction. Compared with the previous 1T1R structure of MOSFET (complementary metal oxide field effect transistor) driving phase change memory unit, the 1D1R structure of diode driving phase change unit has the advantages of small area, low power consumption and fast circuit speed. In view of this, the present invention proposes a ZnO Schottky diode-based phase-change random access memory array fabricated at a low temperature for realizing high-speed, high-density, low-power mass storage arrays.

Contents of the invention

The technical problem mainly solved by the present invention is to provide a ZnO Schottky diode-based phase-change random access memory array and a manufacturing method thereof.

In order to solve the above technical problems, the present invention adopts the following technical solutions:

A phase-change random access memory array based on ZnO Schottky diodes, comprising:

a semiconductor substrate of the first conductivity type;

an insulating buffer layer over the semiconductor substrate;

a plurality of word lines of the second conductivity type parallel to each other located on the insulating buffer layer;

A plurality of ZnO Schottky diodes located on the word line and electrically connected to the word line, the ZnO Schottky diodes are composed of a first conductor layer and an n-type ZnO polycrystalline thin film connected thereto;

a second conductor layer respectively located on each of said ZnO Schottky diodes;

phase change storage layers respectively located on each second conductor layer;

Located on the phase-change storage layer and electrically connected to a plurality of bit lines of the phase-change storage layer, the bit lines are spatially perpendicular to the word lines.

Wherein, the first conductivity type is p-type, and the second conductivity type is n-type.

An insulating isolation layer, preferably made of TEOS (tetraethyl silicate) material, is filled between the plurality of word lines.

The first conductor layer in the ZnO Schottky diode is made of larger metal function material, such as copper, platinum or silver; the second conductor layer above the ZnO Schottky diode is made of aluminum or aluminum-copper alloy material .

A first dielectric isolation structure is provided around the ZnO Schottky diode and the second conductor layer thereon, and the first dielectric isolation structure is connected to the ZnO Schottky diode and the second conductor layer thereon A first dielectric barrier layer is provided between them; a second dielectric isolation structure is provided around the phase change storage layer, and a second dielectric barrier layer is provided between the second dielectric isolation structure and the phase change storage layer . The first dielectric isolation structure and the second dielectric isolation structure use dielectric materials such as SiO ₂ or SiON. Materials such as silicon nitride or SiON are used for the first dielectric barrier layer and the second dielectric barrier layer.

Preferably, the upper and lower surfaces of the word line and the bit line are respectively provided with barrier layers, and the barrier layers are made of materials such as TaN, TiN or Ti/TiN to ensure the reliability of metal conductors.

In addition, the present invention also provides a method for manufacturing a phase-change random access memory array based on ZnO Schottky diodes, comprising the following steps:

(1) forming an insulating buffer layer on the semiconductor substrate;

(2) Form a plurality of word lines parallel to each other on the insulating buffer layer by deposition and photolithography, and fill an insulating isolation layer between the plurality of word lines, and then carry out chemical mechanical polishing to make the surface flat change;

(3) Form a first conductor layer on the word line, and then use atomic layer deposition (ALD) technology to plate ZnO layer by layer in the form of single atoms on the surface of the first conductor layer to form an n-type ZnO polycrystalline film , the deposition temperature is not higher than 200°C; then a second conductor layer is formed on the n-type ZnO polycrystalline film, and a plurality of layers including the first conductor layer, n-type ZnO polycrystalline film and second A columnar unit of the conductor layer, a plurality of the columnar units form a columnar array;

(4) first preparing a first dielectric barrier layer on the surface of the inner wall of the gap of the columnar array, and then filling the gap with a dielectric material to form a first dielectric isolation structure, and then performing chemical mechanical polishing to planarize the surface;

(5) Prepare a layer of dielectric material on the first dielectric isolation structure, and then use a photolithography etching process to open a plurality of through holes to expose the second conductor layer of the lower columnar unit respectively, and make the second conductor layer in the through hole preparing a second dielectric barrier layer on the surface of the inner wall, and then filling the through hole with a phase-change material to form a phase-change storage layer, and the phase-change storage layer and the dielectric material around the second dielectric barrier layer form a second dielectric isolation structure;

(6) Using chemical mechanical polishing to planarize the surface of the phase change storage layer, and then fabricating bit lines thereon, the space of the bit lines being perpendicular to the word lines.

Wherein, when the n-type ZnO polycrystalline thin film is formed by atomic layer deposition technology in step (3), the substrate ^temperature is 60-200°C, the vacuum degree of the chamber is ^{4x10-9-6x10-9} Torr, and the gas flow rate is 0.06-0.08 L/s; the precursors are diethyl zinc and H ₂ O, and the chemical reaction formula is:

Zn(C ₂ H ₅ ) ₂ +H ₂ O→ZnO+2C ₂ H ₆

Preferably, the deposition rate is 0.12-0.16 nm/cycle, and the deposition cycle includes: the pulse time for introducing the precursor H ₂ O is 14-16 ms, the cleaning time for H ₂ O is 8-20 s, and the time for introducing the precursor diethyl zinc The pulse time is 20-90ms, and the cleaning time for diethyl zinc is 7-9s.

Preferably, barrier layers are prepared on the upper and lower surfaces of the word lines and bit lines, respectively.

As a preferred solution of the present invention, a conductive plug is made on each word line to lead out the word line, so that the bit line and the word line are located on the substrate.

Compared with the prior art, the beneficial effects of the present invention are:

Among many types of diodes, ZnO Schottky diodes are often used in the field of optoelectronic devices. They belong to majority carrier devices and have the characteristics of low turn-on voltage and fast response speed. The study found that since the undoped ZnO semiconductor material itself has n-type conductivity, depositing ZnO semiconductor thin film on the metal conductor can directly form a Schottky diode, thus avoiding high temperature such as diffusion or ion implantation and annealing. crafting process. Therefore, the process temperature of the Schottky diode formed by using ZnO semiconductor and metal is lower than that of the diode formed by the selective epitaxial process. Moreover, the characteristic size of the diode formed by ZnO semiconductor can reach 2F ² , which is obviously smaller than that of the diode formed by the epitaxial process, and its turn-on voltage is also lower than that of the pn junction diode.

The phase-change random memory array of the present invention adopts a ZnO Schottky diode directly formed by ZnO semiconductor and metal layer as a gating element to realize the 1D1R structure of the diode-driven phase-change unit, which has small area, low power consumption, and high circuit speed. Fast and other advantages. In addition, since the ZnO semiconductor film can be directly deposited on the metal word line to form diodes, the processing temperature does not exceed 350°C during the formation of the phase change memory array. This low-temperature process is conducive to stacking multiple memory arrays to achieve three-dimensional stacked structure to further increase device density. Therefore, the invention can make the phase-change random access memory have higher density, lower power consumption and higher performance.

The present invention also provides the low-temperature manufacturing process of this ZnO Schottky diode-based phase-change random access memory array. It is found that only the specific process conditions of atomic layer deposition (ALD) can be used at a relatively low growth temperature (200°C). In order to obtain n-type low-conductivity ZnO semiconductor material, and then form a Schottky barrier with specific metals. The present invention manufactures Schottky diodes through the process of atomic layer deposition of n-type ZnO polycrystalline thin films under low temperature conditions, which is competitive in cost and is expected to be widely used in three-dimensional phase change memory circuits. The development of memory is of great significance.

Description of drawings

FIG. 1 is a schematic structural diagram of a first phase-change random memory cell (1D1R) gated by a ZnO Schottky diode.

Figure 2 is a schematic diagram of the three-dimensional structure of 1D1R.

FIG. 3 is a schematic diagram of a three-dimensional structure of a phase change memory array.

Figure 4 is a schematic diagram of the 1D1R 4x4 memory cell array circuit.

Fig. 5 is the characteristic curve (relationship curve between current density and voltage) of ZnO Schottky diode in the embodiment.

FIG. 6 is a cross-sectional view of a phase-change random access memory array in an embodiment.

Fig. 7 is a cross-sectional view of the phase-change random access memory array along the direction AA' in Fig. 6 .

Fig. 8 is a schematic diagram of a three-dimensional structure of a phase-change random access memory in an embodiment.

Detailed ways

Hereinafter, the present invention is more fully described in reference examples with reference to the accompanying drawings. Where the drawings are schematic illustrations of idealized embodiments of the invention, the illustrated embodiments of the invention should not be construed as limited to the particular shapes of the regions shown in the drawings, but to include resulting shapes, such as manufacturing-induced deviations For example, the curves obtained by dry etching usually have curved or rounded features, but in the illustrations of the embodiments of the present invention, they are all represented by rectangles or cubes, and the representations in the figures are schematic, but this should not be considered as a limitation scope of the invention. Like reference numerals in the figures may denote like structural parts.

The present invention adopts a ZnO Schottky diode to form a 1D1R structure of a diode-driven phase-change unit. As shown in FIG. 1, the ZnO Schottky diode gates the phase-change material, and the second conductor is mainly used to connect the diode and the phase-change storage layer. effect. In an embodiment of the present invention, a three-dimensional schematic diagram of the 1D1R structure is shown in FIG. 2 , the extending direction parallel to the bit line is the x direction, the extending direction parallel to the word line is the y direction, and the upward stacking direction is the z direction. Figure 3 is a schematic diagram of a three-dimensional structure of a phase-change memory array. Multiple parallel bit lines in the x direction and multiple parallel word lines in the y direction are perpendicular to each other. ZnO Schottky diodes and phase A columnar structure composed of variable storage layers. FIG. 4 is an equivalent circuit diagram of the 4x4 1D1R structure corresponding to FIG. 3 .

Fig. 5 is the test curve of the current density and the voltage of a kind of ZnO Schottky diode, and wherein this ZnO Schottky diode is made up of n-type ZnO polycrystalline thin film and the first conductor layer, and the first conductor layer adopts Ag, in Ag A Schottky barrier is formed on the interface with ZnO, and the second conductor layer is Al. At a voltage of 1 volt, the current density through the diode reaches 100 A/cm ² . The current density increases exponentially with the voltage applied between the upper and lower electrodes, which can realize the function of driving the phase change memory unit.

The specific structure of this ZnO Schottky diode-based phase-change random access memory array in the embodiment of the present invention is shown in Figure 6, which is a cross-sectional view in the xz direction, and the structure includes:

Si substrate 100 of the first conductivity type (preferably p-type in this embodiment);

an insulating buffer layer 102 located on the Si substrate 100;

A plurality of parallel word lines 208 of the second conductivity type (n-type in this embodiment) located on the insulating buffer layer 102;

Located above the word line 208 and electrically connected to a plurality of ZnO Schottky diodes of the word line 208, the ZnO Schottky diode is composed of a first conductor layer 113 and an n-type ZnO polycrystalline thin film 114 connected thereto;

a second conductor layer 112 respectively located on each of said ZnO Schottky diodes;

a phase-change storage layer 218 located on each second conductor layer 112;

Located on the phase change memory layer 218 and electrically connected to a plurality of bit lines 209 of the phase change memory layer 218 , the bit lines 209 are spatially perpendicular to the word lines 208 .

Wherein, an insulating isolation layer 202, preferably made of TEOS material, is filled between the plurality of word lines 208 . The first conductor layer 113 in the ZnO Schottky diode adopts larger metal function materials, such as copper, platinum or silver; the second conductor layer 114 on the ZnO Schottky diode adopts aluminum or aluminum copper Alloy materials. A first dielectric isolation structure formed by a dielectric material 108 is provided around the first conductor layer 113, the n-type ZnO polycrystalline thin film 114 and the second conductor layer 112 thereon, and the first dielectric isolation structure and the A first dielectric barrier layer 212 is provided between the ZnO Schottky diode and the second conductor layer 112 thereon. A second dielectric isolation structure formed of a dielectric material 108 is provided around the phase change storage layer 218 , and a second dielectric barrier layer 210 is provided between the second dielectric isolation structure and the phase change storage layer 218 . The first dielectric isolation structure and the second dielectric isolation structure use dielectric materials such as SiO ₂ or SiON. The first dielectric barrier layer 212 and the second dielectric barrier layer 210 are made of materials such as silicon nitride or SiON. Barrier layers 204 are provided on the upper and lower surfaces of the word line 208 and the bit line 209 respectively, and the barrier layer 204 is made of materials such as TaN, TiN or Ti/TiN to ensure the reliability of the metal conductor.

Fig. 7 is a cross-sectional view in the yz direction of a memory cell including a metal ZnO Schottky diode and a phase-change memory layer, viewed along the direction AA' according to an embodiment of the present invention.

The manufacturing method of the above-mentioned phase-change random access memory array includes the following steps:

(1) An insulating buffer layer 102 is deposited on the p-type Si substrate 100 .

(2) Depositing a first etch stop layer 201 on the upper surface of the insulating buffer layer 102, the first etch stop layer 201 can be made of materials such as SiN or SiON, and a word line layer is formed by methods such as physical vapor deposition (PVD), And prepare barrier layers 204 on the upper and lower surfaces of the word line layer; wherein the word line layer can be made of copper or aluminum-copper alloy, and the process temperature does not exceed 350°C. A plurality of parallel word lines 208 are formed by photolithography and other processes, and an insulating isolation layer 202, which may be TEOS, is filled between the plurality of word lines 208, and then chemical mechanical polishing (CMP) is performed to planarize the surface.

(3) Form a layer of first conductor material on the word line 208, and then use atomic layer deposition (ALD) technology to plate ZnO layer by layer in the form of single atoms on the surface of the first conductor material to form an n-type ZnO layer. Crystalline thin film, the deposition temperature is not higher than 200°C; a layer of second conductor material is formed on the n-type ZnO polycrystalline thin film; and then the first conductive material, n-type ZnO polycrystalline thin film and second conductor The material is processed by photolithography process and dry etching process. For example, electron beam exposure process can be used to form a pattern to form a columnar array. Each unit of the columnar array includes a first conductor layer 113 and an n-type ZnO polycrystalline thin film 114. and the second conductor layer 112 . Wherein, the high-density and small-sized first conductor layer 113 may also be formed by means of electroplating or the like. The first conductor layer 113 needs to be aligned with the word line 208 to form an electrical connection.

(4) First prepare the first dielectric barrier layer 212 on the surface of the inner wall of the gap of the columnar array, for example, it can be prepared by PVD technology; then use the dielectric material 108 to fill the gap to form the first dielectric isolation structure, and then use CMP technology removing the medium other than the gap to expose the second conductor layer 112;

(5) A second etching stop layer 213 is fabricated on the surface of the structure obtained in step (4), and the material can be Si ₃ N ₄ , and then a layer of dielectric material 108 is prepared, and then a plurality of through holes are opened by using a photolithographic etching process, The second conductor layer 112 of the lower columnar unit is exposed respectively, and the second dielectric barrier layer 210 is prepared on the inner wall surface of the through hole, and then the phase change material 108 is filled in the through hole by magnetron sputtering to form a phase change storage layer 218 , the dielectric material around the phase change storage layer 218 and the second dielectric barrier layer 210 becomes a second dielectric isolation structure. The second dielectric barrier layer 210 can be made of Si ₃ N ₄ or SiON material. This structure is beneficial to fix the shape of the phase change material and prevent Te from penetrating into the dielectric material 108 when the phase change material is deposited by magnetron sputtering. The dielectric material 108 may be SiO ₂ or SiON.

(6) Chemical-mechanical polishing is used to planarize the surface of the phase-change storage layer, and the phase-change material outside the through holes needs to be removed by CMP. A bitline 209 is then fabricated thereon, said bitline 209 being spatially perpendicular to said wordline 208 . Ti/TiN barrier layers 204 are respectively deposited on the upper and lower surfaces of the bit line 109 to ensure the reliability of the metal conductor of the bit line 209 .

Among them, step (3) utilizes atomic layer deposition technology to form a ZnO polycrystalline thin film, the film thickness does not exceed 100nm, and the deposition parameters (film thickness, composition, structure) are easy to control, and the flat film interface can form a good contact with the second conductor .

When using atomic layer deposition technology to form ZnO polycrystalline thin film, the substrate temperature is 60-200°C, the chamber vacuum is 4x10 ^-9 -6x10 ^-9 Torr, the gas flow rate is 0.06-0.08L/s; the precursor is two Ethyl zinc (chemical formula Zn(C ₂ H ₅ ) ₂ , also known as DEZn) and H ₂ O, the chemical reaction formula is:

Zn(C ₂ H ₅ ) ₂ +H ₂ O→ZnO+2C ₂ H ₆

Preferably, the deposition rate is 0.12-0.16nm/cycle, the deposition cycle includes the pulse time of 14-16ms for introducing the precursor H ₂ O, the cleaning time for H ₂ O is 8-20s, and the introduction of the precursor diethyl zinc The pulse time is 20-90ms, and the cleaning time for diethyl zinc is 7-9s. The longer cleaning time in this process condition makes the deposited ZnO thin film have a low free electron concentration and a high mobility n-type semiconductor material suitable for Schottky diodes. In addition, when dimethyl zinc (DMZn) is selected as the zinc precursor source, the growth temperature of the ZnO thin film is room temperature. In this way, a Schottky barrier is formed on the interface between the specific metal and the ZnO semiconductor thin film, and its rectification characteristics under forward bias are shown in FIG. 5 .

In a specific embodiment, the preferred process temperature for depositing an n-type ZnO polycrystalline film by ALD is 100°C, the substrate temperature is 60 to 200°C, the chamber vacuum is 5x10 ^-9 Torr, and the gas flow rate is 0.07L/ s. The deposition rate is about 0.14nm/cycle, and the deposition cycle period includes the pulse time of introducing the precursor H ₂ O is 15ms, the cleaning time of H ₂ O is 8-20s, the pulse time of introducing the precursor DEZn is 20-90ms and for The cleaning time of DEZn is 8s.

FIG. 8 is a schematic diagram of a three-dimensional structure of a phase-change random access memory in a preferred solution of the present invention. Conductive plugs are made on each word line to lead out the word line, and the bit line is on the same side of the silicon substrate. The extracted word lines and bit lines are connected with peripheral driving circuits.

The non-volatile phase-change memory cell of the present invention has been described above in the context of a ZnO Schottky diode-gated phase-change RAM array, which facilitates the application of a three-dimensional stack structure in the context of low manufacturing temperature.

The detailed manufacturing method has been described herein, and other phase-change RAM arrays that can be realized with similar structures and different materials are within the scope of the present invention.

Other process conditions involved in the present invention are conventional process conditions, which belong to the category familiar to those skilled in the art, and will not be repeated here. The above embodiments are only used to illustrate but not limit the technical solution of the present invention. Any technical solutions that do not deviate from the spirit and scope of the present invention shall be included in the patent application scope of the present invention.

Claims (5)

1. a method for making a phase-change random access memory array based on ZnO Schottky diode, is characterized in that, comprises the steps: (1) forming an insulating buffer layer on the semiconductor substrate; (2) Form a plurality of word lines parallel to each other on the insulating buffer layer by deposition and photolithography, and fill an insulating isolation layer between the plurality of word lines, and then carry out chemical mechanical polishing to make the surface flat change; (3) form the first conductor layer on the word line, then utilize atomic layer deposition technology to form n-type ZnO polycrystalline thin film on the surface of the first conductor layer layer by layer with ZnO in single atom form, deposition temperature not higher than 200°C; and then form a second conductor layer on the n-type ZnO polycrystalline film, and form a plurality of layers including the first conductor layer, n-type ZnO polycrystalline film and the second conductor layer through an etching process A columnar unit, a plurality of columnar units form a columnar array; (4) first preparing a first dielectric barrier layer on the surface of the inner wall of the gap of the columnar array, and then filling the gap with a dielectric material to form a first dielectric isolation structure, and then performing chemical mechanical polishing to planarize the surface; (5) Prepare a layer of dielectric material on the first dielectric isolation structure, and then use a photolithography etching process to open a plurality of through holes to expose the second conductor layer of the lower columnar unit respectively, and make the second conductor layer in the through hole preparing a second dielectric barrier layer on the surface of the inner wall, and then filling the through hole with a phase-change material to form a phase-change storage layer, and the phase-change storage layer and the dielectric material around the second dielectric barrier layer form a second dielectric isolation structure; (6) Using chemical mechanical polishing to planarize the surface of the phase change storage layer, and then fabricating bit lines thereon, the space of the bit lines being perpendicular to the word lines. 2. according to the manufacture method of the phase-change RAM array based on ZnO Schottky diode described in claim 1, it is characterized in that: when step (3) utilizes atomic layer deposition technique to form n-type ZnO polycrystalline film, substrate temperature 60～200℃, the chamber vacuum is 4x10 ^-9 ～6x10 ^-9 Torr, the gas flow rate is 0.06～0.08L/s; the precursors are diethylzinc and H ₂ O, and the chemical reaction formula is: Zn(C ₂ H ₅ ) ₂ +H ₂ O→ZnO+2C ₂ H ₆ . 3. according to the manufacture method of the phase-change RAM array based on ZnO Schottky diode described in claim 2, it is characterized in that: when step (3) utilizes atomic layer deposition technique to form n-type ZnO polycrystalline thin film, deposition rate is 0.12-0.16nm/cycle, the deposition cycle includes: the pulse time for introducing the precursor H ₂ O is 14-16ms, the cleaning time for H ₂ O is 8-20s, the pulse time for introducing the precursor diethyl zinc is 20-90ms, The cleaning time for diethyl zinc is 7-9s. 4. The method for manufacturing a phase-change random access memory array based on ZnO Schottky diodes according to claim 1, characterized in that: when making word lines and bit lines, barrier layers are prepared on their upper and lower surfaces respectively. 5. according to the manufacture method of the phase-change RAM array based on ZnO Schottky diode described in claim 1, it is characterized in that: make conductive plug on each word line and word line is drawn out, realize that bit line and word line are located at over the substrate.

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