CN115800728B - Clock charge pump circuit for configuring output voltage - Google Patents
Clock charge pump circuit for configuring output voltage Download PDFInfo
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Abstract
A clocked charge pump circuit for configuring an output voltage, characterized by: the circuit comprises a voltage configuration unit, a clock generation unit, a charge pump unit and a switch sampling unit; the voltage configuration unit is used for controlling the level state of the output voltage V b of the charge pump unit based on the initial charge quantity of the parallel capacitor inside the voltage configuration unit; a clock generation unit for generating and inputting the two-phase non-overlapping clock signals P A and P B of the charge pump unit into the charge pump unit based on the switch control voltage V c; the charge pump unit is used for pumping the power supply voltage based on the two-phase non-overlapping clock signals P A and P B and the output voltage V b which are respectively input by the clock generation unit and the voltage configuration unit, and generating and outputting a switching tube starting voltage V Cbst; and the switch sampling unit is connected with the charge pump unit and obtains a sampling voltage V sample based on the input voltage V in and the switch tube starting voltage V Cbs.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly to a clocked charge pump circuit configured to output voltage.
Background
At present, a switched capacitor sampling circuit is widely applied to various low-voltage low-power consumption integrated circuits, and when the power supply voltage in the circuit is very low, the on-resistance of a switching tube made of a CMOS tube is very high, so that an RC equivalent circuit is formed between the switching tube and a capacitor connected with the switching tube. The RC equivalent circuit will greatly affect the time that the signal builds up on the capacitor, especially when the gate voltage of the switching tube is near one half of the supply voltage, even if it takes the whole half period to charge and discharge, it will not build up the voltage on the capacitor to the desired value. Under the influence of the lower gate voltage, the switch cannot even be turned on at all.
In the prior art, in order to prevent such a problem, a charge pump is often used to realize enhancement of the control voltage of the gate of the switching transistor. For example, the on-time can be shortened by inputting a lower power supply voltage into the charge pump and realizing twice amplification of the voltage value, so that the on-resistance of the switching tube is reduced under the action of a larger gate voltage. Therefore, by the method, the switched capacitor sampling circuit can still realize normal conduction even under the action of a very small input voltage, and the conduction time is short enough.
However, the switch capacitor sampling circuit is realized by adopting a traditional charge pump circuit, and the grid voltage of the switch tube can only be modulated to be a fixed multiple of the power supply voltage. Because of the large amplitude of the supply voltage variation, it may float over a wide range, e.g., the supply voltage may be lower at times and may approach the highest voltage allowed by the chip or circuit process at times. Many times, the supply voltage will be less than the highest voltage allowed by the circuit process. This makes a discrepancy between the pumping power of the charge pump and the actual value of the supply voltage. For example, when the charge pump is twice the charge pump, the supply voltage may be relatively close to and exceed half of the highest voltage allowed by the chip or circuit process. For example, if a charge pump is used when the power supply voltage floats within a small range of more than half of the allowable maximum voltage, the actual voltage is higher than the maximum voltage, and the switching tube gate oxide breaks down at high voltage, so that the switching tube fails. At this time, if the charge pump is not adopted, the existing power supply voltage cannot fully drive the switching tube to be turned on, or the turn-on time delay is too long.
In view of the foregoing, a new configuration circuit is needed to enable the output multiple of the charge pump to be adjusted at any time according to the state of the power supply voltage or the requirements of the circuit designer.
Disclosure of Invention
In order to solve the defects in the prior art, the invention aims to provide the clock charge pump circuit for configuring the output voltage, and the output multiple of the charge pump is regulated and controlled through the initial charge states of N capacitors in the voltage configuration unit, so that the switched capacitor sampling circuit can provide rapid and accurate output of sampling voltage.
The invention adopts the following technical scheme.
A clocked charge pump circuit for configuring an output voltage, characterized by: the circuit comprises a voltage configuration unit, a clock generation unit, a charge pump unit and a switch sampling unit; the voltage configuration unit is connected with the charge pump unit and is used for controlling the level state of the output voltage V B of the charge pump unit based on the initial charge quantity of the parallel capacitor in the voltage configuration unit; a clock generation unit connected with the charge pump unit for generating and inputting the two-phase non-overlapping clock signals P A and P B of the charge pump unit into the charge pump unit based on the switch control voltage V C; the charge pump unit is respectively connected with the logic control unit, the voltage configuration unit and the switch unit and is used for pumping the power supply voltage based on the two-phase non-overlapping clock signals P A and P B and the output voltage V B respectively input by the clock generation unit and the voltage configuration unit, and generating and outputting a switch tube starting voltage V CBST; and the switch sampling unit is connected with the charge pump unit and obtains a sampling voltage V sample based on the input voltage V in and the switch tube starting voltage V CBS.
Preferably, the voltage configuration unit includes N configuration capacitances C B1、CB2 to C BN; one ends of the N configuration capacitors C B1、CB2 to C BN are connected with the source electrode of the MOS transistor Mn2 in the charge pump unit, and the other ends of the N configuration capacitors are connected with the output ends P B1、PB2 to P BN in the clock generation unit respectively.
Preferably, the clock generating unit includes first and second inverters, first and second nand gates, first and second buffers, first to nth and gates; the input end of the first inverter is connected with the switch control voltage V C, and the output end of the first inverter is connected with the first input end of the first NAND gate and the second input end of the second NAND gate; the output end of the first NAND gate outputs a clock signal P B after passing through a first buffer, the output end of the second NAND gate outputs a clock signal P A after passing through a second buffer, the output end of the first buffer is connected with the first input end of the second NAND gate, and the output end of the second buffer is connected with the second input end of the first NAND gate; the output end of the first buffer is respectively connected with the input end of the second inverter and the second input ends of the first to N-th AND gates; the first input ends of the first to N-th AND gates are respectively connected with the enable signals C 1、C2 to C N of the N capacitors, and the output ends of the first to N-th AND gates are respectively used as the output ends P B1、PB2 to P BN of the clock generation unit; the output end of the second inverter outputs an inverted clock signal
Preferably, the charge pump unit includes first to third NMOS transistors Mn1, mn2, and Mn3, a PMOS transistor Mp1, and a capacitor C A; the grid electrode of the first NMOS tube Mn1 is connected with the source electrode of the second NMOS tube Mn2, the drain electrode is connected with the power supply voltage V dd, and the source electrode is connected with one end of the capacitor C A and the grid electrode of the second NMOS tube Mn 2; the other end of the capacitor C A receives the clock signal P A from the clock generation unit; the grid electrode of the second NMOS tube Mn2 is connected with the source electrode of the first NMOS tube Mn1, the drain electrode is connected with the power supply voltage V dd, and the source electrode is connected with N configuration capacitors in the voltage configuration unit; the source of the PMOS tube MP1 is connected with the source of the NMOS tube Mn2, the voltage configuration unit comprises N configuration capacitors C B1、CB2 to C BN, the drain is connected with the drain of the NMOS tube Mn3 and the input end of the switch sampling unit, the grid and the grid of the NMOS tube Mn3 respectively receive the reverse clock signal from the clock generation unitThe source electrode of the NMOS tube Mn3 is grounded, and the drain electrode is used as the output end of the charge pump unit.
Preferably, the switch sampling unit comprises a switch tube Mn sample and a switch capacitor C sample; the gate of the switch tube Mn sample receives the switch tube starting voltage V CBST output by the charge pump unit, the drain receives the input voltage V in, the gate is connected with the switch capacitor C sample, and the sampling voltage V sample is output; the other end of the switch capacitor is grounded.
Preferably, the enable signals C 1、C2 to C N of the N capacitors are set based on a preset range of the switching tube start voltage V CBST.
Preferably, the capacitance values of the N configuration capacitances C B1、CB2 to C BN are all equal.
Preferably, when the level of M driving signals in the driving signals of the N capacitors is the power supply voltage V dd and the level of N-M driving signals is always 0V, the level state of the output voltage V B of the charge pump unit is stabilized after the charge pump circuit is always in normal operationWherein m= [1,2, …, N ].
Compared with the prior art, the clock charge pump circuit for configuring the output voltage has the beneficial effects that the output multiple of the charge pump can be regulated and controlled through the initial charge states of N capacitors in the voltage configuration unit, so that the switched capacitor sampling circuit can provide quick and accurate output of sampling voltage. The circuit structure of the invention is simple, the adaptation to different power supply voltage conditions can be satisfied according to flexible adjustment of a plurality of driving signals without changing the circuit structure, and the output precision degree is high.
Drawings
FIG. 1 is a prior art switched capacitor sampling circuit with a charge pump;
FIG. 2 is a schematic diagram of a main circuit portion of a clock charge pump circuit with an output voltage according to the present invention;
FIG. 3 is a schematic diagram of a clock generating unit in a clock charge pump circuit for configuring an output voltage according to the present invention;
fig. 4 is a schematic diagram of a timing waveform during a start-up of a clock charge pump circuit for configuring an output voltage according to the present invention.
Detailed Description
The application is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present application, and are not intended to limit the scope of the present application.
Fig. 1 is a prior art switched capacitor sampling circuit with a charge pump according to the present invention. As shown in fig. 1, the CMOS clock charge pump circuit adopted in the prior art can realize the output of multiple power supply voltages by alternately turning on and off two cross-connected NMOS transistors. Specifically, the prior art charge pump circuit includes NMOS transistors Mn1 and Mn2, one of which has its source connected to the gate of the other, and its drain receiving the supply voltage. In addition, the sources of the two NMOS transistors Mn1 and Mn2 are respectively connected to the control signals P A and P B of the charge pump through a capacitor, i.e., C A and C B, respectively.
Similar to the control signals for the charge pump in the prior art, P A and P B can be generally implemented by non-overlapping clock signals. After two non-overlapped clock signals are input to two ends of the charge pump together, the MOS tube can be controlled to be turned on and off.
The principle of the charge pump of the present invention is illustrated by way of example. If the input of the P A is the power supply voltage and the input of the P B is 0 at the moment of starting the charge pump, according to the element connection relationship in fig. 1, the position a in the circuit can be deduced, the voltage is raised to the power supply voltage after passing through the capacitor C A, the voltage at the point B is still 0V after passing through the capacitor C B, at this time, mn2 is turned on under the action of the voltage at the point a, and at the same time Mn1 is turned off under the action of the voltage at the point B. Therefore, mn2 turns on, and the voltage at the point B is raised to the power supply voltage.
When the circuit passes the period of the half control signal, the two-phase non-overlapping clock signals P A and P B realize the switching of the high and low levels, so that the input of P A is switched to 0 and the input of P B is switched to the power supply voltage. At this time, since the voltages at the two points AB at the previous time are both changed to the power supply voltage, and the voltage difference between the two ends of the capacitor is instantaneously unchanged along with the input of the signals P A and P B, the voltage at the point a is switched to 0V in this period, and the voltage at the point B is continuously increased on the basis of the power supply voltage in this period, so that the circuit realizes twice the power supply voltage at the point B.
The description of the subsequent circuit parts of the charge pump is continued. Since the drains and gates of the two tubes Mp1 and Mn3 are connected to each other, and the source of Mp1 is connected to the point B in the circuit, when the charge pump is started, the input of P A is the power supply voltage, the input of P B is 0, the gate voltages of the two tubes are the power supply voltages, at this time, mp1 is turned off, mp3 is turned on, and the voltage at the point B cannot be output to the subsequent circuit of the charge pump.
When the circuit passes through the period of half control signals, the two-phase non-overlapping clock signals P A and P B realize high-low level switching, the grid voltage of the two tubes is reduced, mp1 is conducted, and in the conducting process, the charge of the point B with the voltage raised to 2 times of the power supply voltage is output through the source-drain current of Mp 1. At this time, since the on-resistance of the Mp1 tube is small, it can be considered that the voltage at the gate of the Mp1 tube is equal to the B-point voltage.
Since the output terminal of the 2-time charge pump circuit is directly connected with the switched capacitor selection circuit, the starting voltage of the switched capacitor selection circuit also becomes twice the power supply voltage. At this time, the switching tube realizes output of the sampling voltage along with the input voltage of the drain electrode thereof. Because the switch can receive twice the power supply voltage as the conduction control signal, even if the power supply voltage is lower at the moment, the resistance of the switching tube is not large, that is to say, the RC equivalent circuit of the output end of the switching tube can not enable the switching tube to be opened for too long.
However, as described in the background section, the amplification of the input voltage by the charge pump is very fixed, and the change in the supply voltage relative to full scale is not fixed, so that the circuit cannot be turned on due to too small supply voltage when the charge pump is not used; when a charge pump is used, the supply voltage is too large, which causes the circuit to overshoot.
Accordingly, in view of the above problems, the present invention provides a clocked charge pump circuit that configures an output voltage.
Fig. 2 is a schematic diagram of a main circuit portion of a clock charge pump circuit with an output voltage according to the present invention. As shown in fig. 2, a clock charge pump circuit for configuring output voltage in the present invention, wherein the circuit includes a voltage configuration unit, a clock generation unit, a charge pump unit, and a switch sampling unit; the voltage configuration unit is connected with the charge pump unit and is used for controlling the high level state of the output voltage V B of the charge pump unit based on the initial charge quantity of the parallel capacitor in the voltage configuration unit; a clock generation unit connected with the charge pump unit for generating and inputting the two-phase non-overlapping clock signals P A and P B of the charge pump unit into the charge pump unit based on the switch control voltage V C; the charge pump unit is respectively connected with the logic control unit, the voltage configuration unit and the switch unit and is used for pumping the power supply voltage based on the two-phase non-overlapping clock signals P A and P B and the output voltage V B respectively input by the clock generation unit and the voltage configuration unit, and generating and outputting a switch tube starting voltage V CBST; and the switch sampling unit is connected with the charge pump unit and obtains a sampling voltage V sample based on the input voltage V in and the switch tube starting voltage V CBST.
It will be appreciated that the circuit of the present invention is made up of multiple parts. Briefly, the charge pump unit of the present invention, very similar to the charge pump power supply commonly used in the prior art, includes symmetrically arranged capacitors, NMOS transistors, and Mp1 and Mp3. In the invention, N configuration capacitors are arranged at the B point of the charge pump circuit, and can be respectively connected with a plurality of different driving signal control ends directly or indirectly, and the charging and discharging states of the N capacitors can be controlled by controlling the input signals of the circuit, so that the high and low levels of the B point are configured. After the high-low level of the point B is configured, the method can transfer the voltage of the point B to the drain electrode of the MP1, so that a proper grid voltage is provided for the switching tube.
Preferably, the voltage configuration unit includes N configuration capacitances C B1、CB2 to C BN; one ends of the N configuration capacitors C B1、CB2 to C BN are connected with the source electrode of the MOS transistor Mn2 in the charge pump unit, and the other ends of the N configuration capacitors are connected with the output ends P B1、PB2 to P BN in the clock generation unit respectively.
It can be understood that the N configuration capacitors in the present invention are all connected to the point B in the circuit, and the other ends thereof are controlled by the capacitor voltages based on the control signals P B1、PB2 to P BN output from the clock generating unit. It is readily conceivable that the method of the present invention is capable of setting the initial states of a plurality of capacitors by a plurality of control signals, thereby determining the voltage at the B-point position in the circuit in common by the plurality of capacitors.
Preferably, the capacitance values of the N configuration capacitances C B1、CB2 to C BN are all equal. It can be understood that the capacitance values of the N configuration capacitors in the present invention may be set to be identical, so as to facilitate calculation and control of the actually generated voltage in the present invention.
Fig. 3 is a schematic diagram of a clock generating unit in a clock charge pump circuit configured with an output voltage according to the present invention. As shown in fig. 3, the clock generating unit preferably includes first and second inverters, first and second nand gates, first and second buffers, first to nth and gates; the input end of the first inverter is connected with the switch control voltage V C, and the output end of the first inverter is connected with the first input end of the first NAND gate and the second input end of the second NAND gate; the output end of the first NAND gate outputs a clock signal P B after passing through a first buffer, the output end of the second NAND gate outputs a clock signal P A after passing through a second buffer, the output end of the first buffer is connected with the first input end of the second NAND gate, and the output end of the second buffer is connected with the second input end of the first NAND gate; the output end of the first buffer is respectively connected with the input end of the second inverter and the second input ends of the first to N-th AND gates; the first input ends of the first to N-th AND gates are respectively connected with the enable signals C 1、C2 to C N of the N capacitors, and the output ends of the first to N-th AND gates are respectively used as the output ends P B1、PB2 to P BN of the clock generation unit; the output end of the second inverter outputs an inverted clock signal
The clock control signal generation mode in the invention is similar to the non-overlapping clock generation circuit commonly adopted in the prior art, and the circuit can be formed by adopting a logic gate mode, however, because the invention needs to control a plurality of capacitors connected to the B point position of the circuit, the output ends of the clock generation unit are also a plurality of. The signal of output P A is substantially the same as the high level and low level of the control signal of the input terminal, and the phase of output P B is opposite to that of the control signal. In addition, an inverted clock signal obtained after inversion of the signal P B In phase with the control signal, the driving signals P B1、PB2 to P BN for the capacitors are changed according to the change of the enable signal at the input terminal.
Preferably, the charge pump unit includes first to third NMOS transistors Mn1, mn2, and Mn3, a PMOS transistor Mp1, and a capacitor C A; the grid electrode of the first NMOS tube Mn1 is connected with the source electrode of the second NMOS tube Mn2, the drain electrode is connected with the power supply voltage V dd, and the source electrode is connected with one end of the capacitor C A and the grid electrode of the second NMOS tube Mn 2; the other end of the capacitor C A receives the clock signal P A from the clock generation unit; the grid electrode of the second NMOS tube Mn2 is connected with the source electrode of the first NMOS tube Mn1, the drain electrode is connected with the power supply voltage V dd, and the source electrode is connected with N configuration capacitors in the voltage configuration unit; the source of the PMOS tube MP1 is connected with the source of the NMOS tube Mn2, the voltage configuration unit comprises N configuration capacitors C B1、CB2 to C BN, the drain is connected with the drain of the NMOS tube Mn3 and the input end of the switch sampling unit, the grid and the grid of the NMOS tube Mn3 respectively receive the reverse clock signal from the clock generation unitThe source electrode of the NMOS tube Mn3 is grounded, and the drain electrode is used as the output end of the charge pump unit.
In the present invention, the specific structure of the charge pump unit is very similar to that of the charge pump unit in the prior art, and will not be described here again.
Preferably, the switch sampling unit comprises a switch tube Mn sample and a switch capacitor C sample; the gate of the switch tube Mn sample receives the switch tube starting voltage V CBST output by the charge pump unit, the drain receives the input voltage V in, the gate is connected with the switch capacitor C sample, and the sampling voltage V sample is output; the other end of the switch capacitor is grounded.
Through the control of the charge pump unit, the voltage configuration unit and the clock generation unit, the circuit can effectively control the grid voltage in the switch sampling unit, so that the circuit can effectively realize sampling output.
Preferably, the driving signals C 1、C2 to C N of the N capacitors are set based on a preset range of the switching tube start voltage V CBST.
In the invention, the enabling of N capacitance driving signals can be flexibly realized based on the magnitude of the power supply voltage, and can also be designed in advance according to the requirements of a designer and stored in a circuit in advance.
It can be appreciated that in the present invention, the driving voltage of the lower plate of the capacitor C B can control the specific value of the output level of the circuit.
After the charge pump unit starts to operate, the enable signals C 1、C2 to C N of the plurality of capacitors respectively act on the plurality of capacitors together with the driving signal P B, and the enable signals C 1、C2 to C N of the plurality of capacitors can maintain the partial driving signals P B1、PB2 to P BM at the high level, while other partial driving signals are intercepted. With the continuous charging of the driving signals of the capacitors, no matter what state the enabling signals are, the C A and the N C B are fully charged, and the total charge quantity of the capacitors at the point B in the circuit is NCV dd.
Because the charge stored in each capacitor cannot be suddenly changed, the voltage at the point A and the point B in the circuit continuously changes due to the existence and the jump of the control signals P A and P B of the lower polar plate of the capacitor, wherein the voltage at the point B is increased in a certain proportion according to the change of the voltage of the lower polar plate when M P B are at a high level along with the action of the capacitor, and the configuration of the output voltage is realized in this way.
Preferably, when the level of M driving signals in the lower polar plate driving signals of the N capacitors is changed from 0V to the power supply voltage V dd, the level of N-M driving signals is always 0V, the level state of the switch tube starting voltage V B is stabilized after the charge pump works normallyWherein m= [1,2, …, N ].
The calculation of the above formula can be explained by the procedure from the start-up of the circuit to the realization of the steady state in the present invention. Fig. 4 is a schematic diagram of a timing waveform during a start-up of a clock charge pump circuit for configuring an output voltage according to the present invention. The description of the above process may be further described with reference to voltage variations at various locations in fig. 4. In the first period, when the switch control voltage V C is in the high state, the initial voltages of the two-phase non-overlapping clock signals P A and P B in the circuit are 0V and V dd, respectively, and the voltages at the point a and the point B in the circuit are also 0 because the charge pump circuit is not yet started. Meanwhile, based on the magnitude of the power supply voltage or the advanced design of a circuit user, M setting enabling states in driving signals of N capacitors are controlled, namely the capacitor can be driven by a clock, and C 1,C2…CM＝Vdd is adopted; the enable of the N-M drive signals is set to 0V, i.e., C M+1,CM+2…CN =0v.
For example, in one embodiment of the present invention, the driving signals on P B1、PB2 to P BM may be set, and the voltages on P BM+1、PBM+2 to P BN may be set to 0. In other words, according to the setting of the clock generating unit, the clock signals P BM+1、PBM+2 to P BN of the clock signals C BM+1、CBM+2 to C BN are masked by driving the clock signals C B1、CB2 to C BM based on the clock signals P B1、PB2 to P BM through N and gates. In the first period, the voltage at the point B in the circuit rises to V dd with the control of the plurality of driving signals. This turns on the MOS transistor Mn1, and the voltage at the A point is also raised to V dd.
In the second period, when the circuit enters the working state, the circuit switches the high level and the low level for the first time, the switch control voltage V C switches from the power voltage V dd to 0V for the first time, and at this time, the two-phase non-overlapping clock signals P A and P B respectively perform transitions along with the action of the clock generating circuit. The signal P B is first switched from the power voltage V dd to 0V, and the signal P A is first switched from 0V to the power voltage V dd. Under the action of the switching process, the voltage at the two points AB in the circuit also changes, and the voltage at the point A is instantaneously raised to 2 times of the power supply voltage 2V dd because the potential difference at the two ends of the capacitor is basically constant. The voltage at point B is instantaneously reduced to 0V.
Under the condition, according to the voltage at the two points AB, the MOS transistor Mn1 is turned off, the MOS transistor Mn2 is turned on, and the voltage at the point A can be kept unchanged at the power supply voltage V dd in the period because Mn1 is in the off state. And as Mn2 is in a conducting state, the voltage of the point B gradually rises along with the power supply voltage of the drain electrode of Mn2, and finally rises to the power supply voltage V dd.
After the second period is stable, the charge amounts in the capacitors at the point A and the point B in the circuit are added up respectively, so that the charge amount data in the capacitors can be obtained. Specifically, the charge carried by the capacitor at point A is the product of the voltage difference between two sides of point A and the capacitor at point A, and there is
On the other hand, N capacitors C B1、CB2 to C BN are connected to the circuit at the point B, so that the charge amount of the capacitor connected to the circuit at the point B is the total charge amount of the N capacitors. The charge quantity of the capacitor at the point B is the product of the voltage difference between the two ends of the capacitor and the capacitance value of the capacitor, and the capacitor has
It should be noted that, when the circuit is operating in the second period, the clock signal is invertedThe voltage is switched to V dd, so that the MOS tube MP1 cannot be conducted, and the voltage at the point B cannot be transmitted to the grid electrode of the switching tube. In addition, only the two ends of the M capacitors among the N capacitors connected at the point B have a voltage difference, and the two ends of the other N-M capacitors do not have a voltage difference, so that the circuit charges only the M capacitors initially. Over time, the N-M capacitors are charged by the M capacitors, i.e., the M capacitors discharge the charge to the N-M capacitors, so that the N capacitors are all in a fully charged state. Therefore, the total charge amount at the B point is V dd·N·CB.
In the third period, when the charge pump unit is turned over from the state where phase a, i.e., mn2 is on, to phase B, i.e., the two-phase non-overlapping clock signals P A and P B are inverted. This is because the switch control voltage V C in the circuit toggles again, jumping back from 0V to supply voltage V dd again, so that signal P A is at 0V and signal P B is at supply voltage V dd at this time. According to the change of the signals P A and P B, the voltage of the point A and the point B on the other side of the capacitor will also change, the voltage of the point A is instantaneously pulled down to 0V from the power voltage V dd, and the voltage of the point B is instantaneously raised to a state higher than the power voltage from the power voltage V dd. Specific values of the B-point voltage will be described below.
However, according to the voltage state of the two points AB, the on-off states of the MOS transistors Mn1 and Mn2 are switched, the MOS transistor Mn1 is turned on, and the MOS transistor Mn2 is turned off, at this time, the voltage of the point B remains unchanged due to the turn-off of the MOS transistor Mn2, and the voltage of the point a is rapidly increased again to the power supply voltage V dd along with the turn-on of the MOS transistor Mn 1. Therefore, the charge amounts at both points a and B can be confirmed using the following formula. Wherein, the point A is not in a suspended state, but has a charge path, that is Mn1 is conducted, so the charge quantity of the point A is changed, that is
Since Mn2 is turned off and the point B is in a floating state, the charge amount of the point B has no charge-discharge path, and thus remains unchanged before and after the state switching. Specifically, the voltage at the point B is raised from the power supply voltage V dd at the previous stage, and the reason for this is the driving signal at the other end of the N capacitors connected to the point B, that is, the change of P B1、PB2 to P BN. Specifically, in the third period, the control signals P B1、PB2 to P BM raise the lower plate voltages of the charge pumps M C B, so that the voltage that causes the rise of the B-point voltage can be calculated.
Suppose, at this time, the voltage in the circuit changes to V B(t3),
Because the point B is in a suspended state, the charge remains unchanged, so that
Substitution intoAndCan solve the expression of V B(t3 after lifting
In the third period, due to the inverted clock signalThe reduction of the voltage causes the conduction of the MOS tube Mp1, so that the gate voltage V CBST of the switching tube connected with the drain electrode of the MOS tube Mp1 is equal to the voltage of the point B in the periodWhen the MOS tube Mn2 is not conducted in the third period, the point B is always in a suspended state, the voltage of the point B is not changed and is always keptAnd (3) upper part. In the fourth period, when the phase of the two points AB in the circuit is inverted again, the potential of the point P A is the power supply voltage, and the point P B is 0V. Under ideal conditions without considering parasitic capacitance, charge leakage, and the like, there is a power supply voltage in which the point a voltage V A is instantaneously raised by 2 times, and the point B voltage V B is instantaneously pulled down. At this time, the Mn1 pipe is turned off and the Mn2 pipe is turned on. And, with the switching on and off of pipe, the voltage of two points AB also changes, and the voltage of point B finally stabilizes at power supply voltage. The charge quantity at point A is
The charge quantity at the point B is
At this time, the clock signal is invertedThe voltage is raised to V dd again, at the moment, the MP1 tube is not conducted, the grid voltage of the switching tube is pulled down to 0V by Mn3, and therefore the switching tube cannot be broken down or other unsafe factors are caused by continuous accumulation of the grid voltage.
After the four time periods are completed, the circuit enters a stable working state, and the circuit is circularly switched between the third time period and the fourth time period, so that stable conduction of the switching tube is ensured. In addition, the voltage at the point A is switched between a power supply voltage with the high and low levels of 2 times and a power supply voltage with the high and low levels of 1 time, and the voltage at the point B is switched between the high and low levels of 2 timesThe switching is performed between the power supply voltage which is multiplied by 1 and the power supply voltage which is multiplied by 1, so that the high and low levels of the switching tube starting voltage V CB received by the grid electrode of the switching tube are respectively inThe voltage of the power supply is continuously switched between 0V and the multiple power supply voltage.
Therefore, by the method, the high level of the switching tube starting voltage V CBST can be determined at will relative to the multiple of the power supply voltage, the switching tube starting voltage V CBST can adapt to the size of the power supply voltage, the voltage cannot be excessively large on the basis of providing a charge pump function, and the safety of the whole circuit is ensured.
For the followingAnalysis of this multiple shows that by changing the value of M, the magnitude of the switching tube start voltage V CBST can be changed. Specifically, if the power supply voltage is in a fixed state, when m=0, the high-level state of the switching tube start voltage V CBST to be output is equal to the power supply voltage V dd. When m=n/2, the high state of the switching tube start-up voltage V CBST is equal to 1.5 times the power supply voltage V dd. When m=n, the switching tube start-up voltage high state is equal to 2 times the power supply voltage V dd.
Compared with the prior art, the clock charge pump circuit for configuring the output voltage has the beneficial effects that the output multiple of the charge pump can be regulated and controlled through the initial charge states of N capacitors in the voltage configuration unit, so that the switched capacitor sampling circuit can provide quick and accurate output of sampling voltage. The circuit structure of the invention is simple, the adaptation to different power supply voltage conditions can be satisfied according to flexible adjustment of a plurality of driving signals without changing the circuit structure, and the output precision degree is high.
While the applicant has described and illustrated the embodiments of the present invention in detail with reference to the drawings, it should be understood by those skilled in the art that the above embodiments are only preferred embodiments of the present invention, and the detailed description is only for the purpose of helping the reader to better understand the spirit of the present invention, and not to limit the scope of the present invention, but any improvements or modifications based on the spirit of the present invention should fall within the scope of the present invention.
Claims (7)
1. A clocked charge pump circuit for configuring an output voltage, characterized by:
The circuit comprises a voltage configuration unit, a clock generation unit, a charge pump unit and a switch sampling unit; wherein,
The voltage configuration unit is connected with the charge pump unit and is used for controlling the level state of the output voltage V B of the charge pump unit based on the initial charge quantity of the parallel capacitor inside the voltage configuration unit;
the clock generation unit is connected with the charge pump unit and is used for generating two-phase non-overlapping clock signals P A and P B of the charge pump unit based on a switch control voltage V C and inputting the two-phase non-overlapping clock signals into the charge pump unit;
The clock generation unit comprises a first inverter, a second inverter, a first NAND gate, a second NAND gate, a first buffer, a second buffer and first to Nth AND gates; wherein,
The input end of the first inverter is connected with the switch control voltage V C, and the output end of the first inverter is connected with the first input end of the first NAND gate and the second input end of the second NAND gate;
The output end of the first NAND gate outputs a clock signal P B after passing through a first buffer, the output end of the second NAND gate outputs a clock signal P A after passing through a second buffer, the output end of the first buffer is connected with the first input end of the second NAND gate, and the output end of the second buffer is connected with the second input end of the first NAND gate;
The output end of the first buffer is respectively connected with the input end of the second inverter and the second input ends of the first to N-th AND gates;
The first input ends of the first to nth AND gates are respectively connected with the enable signals C 1、C2 to C N of the N capacitors, and the output ends of the first to nth AND gates are respectively used as the output ends P B1、PB2 to P BN of the clock generation unit;
The output end of the second phase inverter outputs an inverted clock signal
The charge pump unit is respectively connected with the logic control unit, the voltage configuration unit and the switch sampling unit and is used for pumping the power supply voltage based on the two-phase non-overlapping clock signals P A and P B and the output voltage V B respectively input by the clock generation unit and the voltage configuration unit to generate and output a switching tube starting voltage V CBST;
the switch sampling unit is connected with the charge pump unit and obtains a sampling voltage V sample based on an input voltage V in and a switch tube starting voltage V CB.
2. A clocked charge pump circuit for configuring an output voltage as claimed in claim 1, wherein:
The voltage configuration unit comprises N configuration capacitors C B1、CB2 to C BN;
One ends of the N configuration capacitors C B1、CB2 to C BN are connected with the source electrode of the MOS transistor Mn2 in the charge pump unit, and the other ends of the N configuration capacitors are connected with the output ends P B1、PB2 to P BN in the clock generation unit respectively.
3. A clocked charge pump circuit for configuring an output voltage as claimed in claim 2, wherein:
The charge pump unit comprises first to third NMOS tubes Mn1, mn2 and Mn3, a PMOS tube Mp1 and a capacitor C A; wherein,
The grid electrode of the first NMOS tube Mn1 is connected with the source electrode of the second NMOS tube Mn2, the drain electrode is connected with the power supply voltage V dd, and the source electrode is connected with one end of the capacitor C A and the grid electrode of the second NMOS tube Mn 2;
The other end of the capacitor C A receives a clock signal P A from the clock generation unit;
the grid electrode of the second NMOS tube Mn2 is connected with the source electrode of the first NMOS tube Mn1, the drain electrode is connected with the power supply voltage V dd, and the source electrode is connected with N configuration capacitors in the voltage configuration unit;
the source of the PMOS tube MP1 is connected with the source of the NMOS tube Mn2, the voltage configuration unit comprises N configuration capacitors C B1、CB2 -C BN, the drain is connected with the drain of the NMOS tube Mn3 and the input end of the switch sampling unit, the grid and the grid of the NMOS tube Mn3 respectively receive the reverse clock signal from the clock generation unit
The source electrode of the NMOS tube Mn3 is grounded, and the drain electrode is used as the output end of the charge pump unit.
4. A clocked charge pump circuit for configuring an output voltage as claimed in claim 3, wherein:
The switch sampling unit comprises a switch tube Mn sample and a switch capacitor C sample; wherein,
The grid electrode of the switch tube Mn sample receives the switch tube starting voltage V CBS output by the charge pump unit, the drain electrode receives the input voltage V in, the grid electrode is connected with the switch capacitor C sample, and the sampling voltage V sample is output;
the other end of the switch capacitor is grounded.
5. A clocked charge pump circuit for configuring an output voltage as defined in claim 4, wherein:
the enable signals C 1、C2 to C N of the N capacitors are set based on a preset range of the switching tube start voltage V CBST.
6. A clocked charge pump circuit for configuring an output voltage as defined in claim 5, wherein:
The capacitance values of the N configuration capacitances C B1、CB2 to C BN are all equal.
7. A clocked charge pump circuit for configuring an output voltage as defined in claim 6, wherein:
When the level of M driving signals in the driving signals of the N capacitors is the power supply voltage V dd and the level of N-M driving signals is always 0V, the level state of the output voltage V B of the charge pump unit is stabilized after the clock charge pump circuit works normally
Wherein m= [1,2, …, N ].
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| CN109617395A (en) * | 2018-12-27 | 2019-04-12 | 西安紫光国芯半导体有限公司 | A kind of method and circuit, charge pump improving charge pump transfer efficiency |
| CN109818485A (en) * | 2017-11-22 | 2019-05-28 | 美国亚德诺半导体公司 | Reconfigurable low-power and low-power grid guide circuit |
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| US8294509B2 (en) * | 2010-12-20 | 2012-10-23 | Sandisk Technologies Inc. | Charge pump systems with reduction in inefficiencies due to charge sharing between capacitances |
| CN105932873B (en) * | 2016-06-17 | 2018-05-25 | 苏州昆泰芯微电子科技有限公司 | A kind of charge pump of low-power consumption high output voltage |
| CN108551257B (en) * | 2018-04-27 | 2019-12-27 | 电子科技大学 | Charge pump structure |
| CN112448576B (en) * | 2020-11-16 | 2022-10-25 | 上海唯捷创芯电子技术有限公司 | Positive and negative voltage charge pump circuit, chip and communication terminal |
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| CN109818485A (en) * | 2017-11-22 | 2019-05-28 | 美国亚德诺半导体公司 | Reconfigurable low-power and low-power grid guide circuit |
| CN109617395A (en) * | 2018-12-27 | 2019-04-12 | 西安紫光国芯半导体有限公司 | A kind of method and circuit, charge pump improving charge pump transfer efficiency |
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