CN115798373A - Drive calibration circuit, method, device and equipment - Google Patents
Drive calibration circuit, method, device and equipment Download PDFInfo
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- CN115798373A CN115798373A CN202211422255.8A CN202211422255A CN115798373A CN 115798373 A CN115798373 A CN 115798373A CN 202211422255 A CN202211422255 A CN 202211422255A CN 115798373 A CN115798373 A CN 115798373A
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Abstract
The utility model provides a drive calibration circuit, method, device and equipment, at first through first time confirm module and second time confirm module, confirm the first time length that the unit interval of clock signal corresponds, and the second time length between the second change edge of the first change edge between the data signal and clock signal among the unit interval of clock signal respectively, later through the calibration module to data signal or clock signal carry out the calibration to make the time offset between data signal and clock signal in predetermineeing the within range, guaranteed drive circuit's reliability and accuracy.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a driving calibration circuit, a method, an apparatus, and a device.
Background
As the resolution and size of the Display screen increase, the distance between the Timing Controller (TCON) of the Display screen and the Display Driver Integrated Circuit (DDIC) also increases, and the influence of the corresponding external noise or parasitic capacitance on the signal input to the DDIC also becomes large, which may cause a problem of insufficient margin (margin) between the clock (clk) channel and the data channel of the DDIC.
Disclosure of Invention
The present disclosure provides a driving calibration circuit, method, apparatus and device. The specific scheme is as follows:
an embodiment of an aspect of the present disclosure provides a driving calibration circuit, including:
the device comprises a first time determining module, a second time determining module and a calibrating module;
the clock input end and the signal input end of the first time determination module are used for inputting clock signals, and the output end of the first time determination module is connected with the first input end of the calibration module so as to output a first time length corresponding to a unit interval of the clock signals to the calibration module;
a clock input end of the second time determination module is used for inputting a clock signal, a signal input end of the second time determination module is used for inputting a data signal, and an output end of the second time determination module is connected with a second input end of the calibration module so as to output a second time length between a first change edge of the data signal and a second change edge of the clock signal within the unit interval to the calibration module;
the calibration module is configured to calibrate the data signal or the clock signal according to the first time length and the second time length, so that a time offset between the data signal and the clock signal is within a preset range, and output the calibrated data signal and the calibrated clock signal.
An embodiment of one aspect of the present disclosure provides a driving calibration method, including:
determining a first time length corresponding to a unit interval of a clock signal;
determining a second time length between a first change edge of a data signal and a second change edge of the clock signal in the unit interval;
and calibrating the data signal or the clock signal according to the first time length and the second time length so as to enable the time offset between the data signal and the clock signal to be within a preset range.
Another embodiment of the present disclosure provides a driving calibration apparatus, including:
the first determining module is used for determining a first time length corresponding to a unit interval of a clock signal;
a second determining module, configured to determine a second time length between a first change edge of the data signal and a second change edge of the clock signal in the unit interval;
and the processing module is used for calibrating the data signal or the clock signal according to the first time length and the second time length so as to enable the time offset between the data signal and the clock signal to be within a preset range.
Another embodiment of the present disclosure provides a display driving integrated circuit DDIC including the driving calibration circuit according to the above-mentioned aspect.
Another embodiment of the present disclosure provides an apparatus, including a DDIC and a display panel connected to each other;
wherein the DDIC performs the method of the second aspect to calibrate the data signal or the clock signal and drive the display panel to display based on the calibrated data signal and the calibrated clock signal.
According to the drive calibration circuit, the drive calibration method, the drive calibration device and the drive calibration equipment, firstly, a first time length corresponding to a unit interval of a clock signal and a second time length between a first change edge between data signals and a second change edge of the clock signal are respectively determined through a first time determination module and a second time determination module, and then the data signals or the clock signals are calibrated through the calibration module, so that the time offset between the data signals and the clock signals is within a preset range, and the reliability and the accuracy of the drive circuit are guaranteed.
Additional aspects and advantages of the disclosure will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosure.
Drawings
The above and/or additional aspects and advantages of the present disclosure will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic diagram of a clock signal and a data signal provided by an embodiment of the disclosure;
fig. 2 is a schematic structural diagram of a driving calibration circuit according to an embodiment of the disclosure;
fig. 3 is a schematic structural diagram of another driving calibration circuit according to an embodiment of the disclosure;
FIG. 4 is a schematic diagram of another clock signal and data signal provided by the embodiments of the present disclosure;
fig. 5 is a schematic flow chart of a driving calibration method according to an embodiment of the disclosure;
FIG. 6 is a schematic diagram of another clock signal and data signal provided by the embodiments of the present disclosure;
fig. 7 is a schematic structural diagram of a driving calibration apparatus according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of an apparatus provided in an embodiment of the present disclosure.
Detailed Description
Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and intended to be illustrative of the present disclosure, and should not be construed as limiting the present disclosure.
For convenience of understanding, the terms of art referred to in this disclosure are explained first below.
1. Mobile Industry Processor Interface (MIPI),
MIPI is an open standard initiated by the MIPI alliance that is established for mobile application processors. It is not a single interface or protocol but contains a set of protocols or standards to meet the unique requirements of different subsystems in the mobile phone, such as camera interface CSI, display interface DSI, etc.
2. Display Driver Integrated Circuit (DDIC)
The DDIC is an integrated circuit for driving a display panel, and can receive image data from a host, also called an Application Processor (AP), through the MIPI, and drive the display panel to display after calibrating an image data signal or a clock signal based on a timing relationship between the image data signal and a generated clock signal.
Generally, a single physical layer (PHY) of the MIPI includes one clock lane (clk lane) and one or more data lanes (data lanes), and in the present disclosure, a description is given of a proposed drive calibration method and circuit, for example, by taking an example where 4 data lanes are included in one PHY.
3. Unit interval of clock signal (clock unit interval)
The unit interval of the clock signal is used for describing the time length of the clock signal in which the level is kept unchanged. For example, a certain time period during which the clock signal is continuously at a high level may be referred to as a unit interval, or a certain time period during which the clock signal is continuously at a low level may be referred to as a unit interval. In the disclosure, it is considered that as the size of the display screen increases, the distance between the TCON and the DDIC also increases, and the influence of parasitic capacitance between the TCON and the DDIC and the like on the signal input to the DDIC may cause a margin shortage between the clk channel and the data channel of the DDIC.
Fig. 1 is a schematic diagram of a clock signal and a data signal according to an embodiment of the disclosure. As shown in fig. 1a, the margin between the data signal and the clock signal may refer to a setup margin (setup margin) in fig. 1 or a hold margin (hold margin) in fig. 1 a. As can be seen from fig. 1a, the sum of setup margin and hold margin is equal to the length of a unit interval of the clock signal.
In fig. 1a, taking the example that the MIPI includes 4 DATA lanes (DATA lanes), the relationship between setup margin and hold margin between the DATA signal in each DATA lane and the clock signal in the clock lane (CLK lane) is shown. 1 st DATA lane represents the DATA signal in the first DATA channel, 2 nd DATA lane represents the DATA signal in the second DATA channel, 3 rd DATA lane represents the DATA signal in the third DATA lane, 4 th DATA lane represents the DATA signal in the fourth DATA channel. As can be seen from the figure, 2 nd The DATA signal in DATA lane corresponds to a smaller setup margin (low), 4 th The DATA signal in DATA lane corresponds to a small hold margin.
Generally, MIPI starts transmitting data signals when a clock signal triggering edge arrives (e.g., from low to high). If the time offset between the data signal and the clock signal is as shown in fig. 1a, i.e. the setup margin is large, the hold margin becomes small, and at this time, data in the data channel of the MIPI may not be reliably written into the frame memory; if the setup margin is small, the hold margin becomes large, which may result in the data in the frame memory not being completely read and being overwritten with new image data. That is, when either of the setup margin and the hold margin is small, it may cause page abnormality on the display screen, and therefore, it is necessary to maintain a certain time offset, i.e., a margin, between the clock signal and the data signal.
Therefore, the present disclosure provides a driving calibration circuit, method, device and apparatus. The clock signal or the data signal is calibrated based on the first time length corresponding to the unit interval of the clock signal and the second time length between the data signal and the clock signal in the unit interval, so that the allowance between the data signal and the clock signal is ensured to be within a preset range, and the reliability and the accuracy of the driving circuit are ensured.
The driving calibration method provided by the present disclosure may be performed by a driving calibration apparatus provided by the present disclosure, which may be configured in or used with a DDIC, and the present disclosure does not limit this.
The following describes a driving calibration circuit, a method, a device and an apparatus provided by the present disclosure in detail with reference to the accompanying drawings.
Fig. 2 is a schematic structural diagram of a driving calibration circuit according to an embodiment of the disclosure. As shown in fig. 2, the present disclosure provides a drive calibration circuit including: a first time determination module 11, a second time determination module 12 and a calibration module 13.
A clock input end and a signal input end of the first time determination module 11 are both used for inputting a clock signal, and an output end of the first time determination module 11 is connected with a first input end of the calibration module 13 so as to output a first time length corresponding to a unit interval of the clock signal to the calibration module 13;
a clock input end of the second time determination module 12 is used for inputting a clock signal, a signal input end of the second time determination module 12 is used for inputting a data signal, and an output end of the second time determination module 12 is connected with a second input end of the calibration module 13 so as to output a second time length between a first change edge of the data signal and a second change edge of the clock signal within the unit interval to the calibration module 13;
the calibration module 13 is configured to calibrate the data signal or the clock signal according to the first time length and the second time length, so that a time offset between the data signal and the clock signal is within a preset range, and output the calibrated data signal and the calibrated clock signal.
The first changing edge and the second changing edge may be valid edges of the data signal and the clock signal, respectively. For example, the first change edge is a change edge when the data signal changes from a low level to a high level, and the second change edge is a change edge when the clock signal changes from a high level to a low level; or, the first change edge is a change edge when the data signal changes from high level to low level, and the second change edge is a change edge when the clock signal changes from low level to high level; alternatively, the first change edge is a change edge when the data signal changes from a low level to a high level, the second change edge is a change edge when the clock signal changes from a low level to a high level, and the like, which is not limited in this disclosure.
It should be noted that, as can be seen from fig. 1a, if the first variation edge is the same as the second variation edge, the second time length is setup margin, and if the first variation edge is different from the second variation edge, the second time length is setup margin.
In addition, the preset range is a numerical value or a data range, and when the time interval between the first change edge of the data signal and the second change edge of the clock signal is within the preset range, the data signal can be reliably written into the frame memory, and the read-write pointer corresponding to the frame memory cannot be overlapped.
In the present disclosure, after receiving the data signal, the driving calibration circuit firstly inputs the clock signal into the first time determination module 11, and then the first time determination module 11 can determine the first time length corresponding to the unit interval of the clock signal. Meanwhile, the data signal is input into the second delay module 12, and then the second time determination module 12 can determine the second time length between the first change edge of the data signal and the second change edge of the clock signal in the unit interval.
The calibration module 15, after receiving the first time length and the second time length, may determine a time offset between the data signal and the clock signal according to the first time length and the second time length, and further calibrate the data signal or the clock signal based on the expected time offset, so that the time offset between the calibrated data signal and the clock signal is within a preset range. That is, enough margin is ensured between the calibrated data signal and the clock signal, so as to ensure the reliability and accuracy of driving.
Optionally, the calibration module 15 may delay the data signal or delay the clock signal according to the expected time offset and the actual time offset between the data signal and the clock signal, so that the time offset between the processed clock signal and the data signal is within a preset range.
For example, if the setup margin between the data signal and the clock signal is small, the clock signal may be delayed; alternatively, if the hold margin between the data signal and the clock signal is small, the data signal may be delayed. So that the time offset between the calibrated data signals (e.g., dout1, dout2, dout3, dout4, etc.) and the clock signal (Clk out) is shown in fig. 1 b.
According to the driving calibration circuit, firstly, the first time length corresponding to the unit interval of the clock signal and the second time length between the first change edge between the data signals and the second change edge between the clock signals are respectively determined through the first time determination module and the second time determination module, and then the data signals or the clock signals are calibrated through the calibration module, so that the time offset between the data signals and the clock signals is within a preset range, and the reliability and the accuracy of the driving circuit are guaranteed.
The driving calibration circuit provided by the present disclosure is further described below with reference to fig. 3. Fig. 3 is a schematic structural diagram of another driving calibration circuit according to an embodiment of the disclosure. As shown in fig. 3, the present disclosure provides a drive calibration circuit including: a first time determination module 11 (not shown), a second time determination module 12 (not shown), and a calibration module 13.
The first time determining module 11 includes a first delay unit 111 and a first time calculating unit 112, and the second time determining module 12 includes a second delay unit 121 and a second time calculating unit 122.
An input end of the first delay unit 111 is connected to a signal input end of the first time calculation unit 112 and a clock input end of the second time calculation unit 122, respectively, and configured to input a clock signal;
the output end of the first delay unit 111 is connected with the signal input end of the first time calculation unit 112;
the input end of the second delay unit 121 is used for inputting a data signal, and the output end of the second delay unit 121 is connected to the signal input end of the second time calculating unit 122;
the output end of the first time calculation unit 112 is connected to the calibration module 13 to output a first time length corresponding to the unit interval of the clock signal to the calibration module 13;
the output end of the second time calculating unit 122 is connected to the calibration module 13, so as to output a second time length between the first change edge of the data signal and the second change edge of the clock signal to the calibration module 13 within the unit interval, and then the calibration module 13 may calibrate the data signal or the clock signal according to the first time length and the second time length, so as to make the time offset between the data signal and the clock signal within a preset range, and output the calibrated data signal and the calibrated clock signal.
The first delay unit 111 and the second delay unit 121 may be the same or different. That is, the delay time length of the first delay unit 111 and the delay time length of the second delay unit 121 may be the same or different, which is not limited in this disclosure.
Optionally, the first delay unit 111 and the second delay unit 121 may be any device that can implement a delay function, such as a timer or a counter, and the implementation form of the present disclosure is not limited.
In this disclosure, the delay durations respectively corresponding to the first delay unit 111 and the second delay unit 121 may be values determined through experiments. For example, the first delay unit 111 is a counter with a count value N, and the second delay unit is a counter with a 121-bit count value M. That is, after the clock signal is input to the input terminal, the first delay unit 111 counts N number of clock signals, and outputs the clock signal through the output terminal. After the data signals are input at the input end, the second delay unit 121 counts M number of the data signals, and outputs the data signals through the output end. I.e. the clock signal and the data signal are delayed by N time units and M time units, respectively. Alternatively, the first time calculation unit 112 and the second time calculation unit 122 may be any functional device that can output a signal that is in-phase or in-phase with the input signal when the active clock edge triggers, for example, may be a D flip-flop or the like.
Considering that the distance between TCON and DDIC increases, external noise or parasitic capacitance introduced into the circuit increases, thereby affecting the signal input into DDIC. Therefore, in order to determine the time offset between the clock signal and the data signal actually input into the MIPI port, the clock signal and the data signal are respectively delayed by using the delay unit, so that the phase of the clock signal and the phase of the data signal after the delay are respectively the same as or opposite to the phase of the clock signal before the delay, and then the clock signal and the data signal are input into the time calculation unit. Because the time calculating unit outputs the same phase or opposite phase signal with the input signal when the input clock signal is valid, the time offset condition of the clock signal and the data signal before time delay can be determined according to the time sequence of the signal output by the time calculating unit and the corresponding time delay coefficients of the first time delay unit 111 and the second time delay unit 121.
Fig. 4 is a schematic diagram of another clock signal and a data signal provided by the embodiment of the disclosure. As shown in fig. 4a, after the clock signal is delayed by N time units, the clock signal and the original clock signal can be in opposite phases, so that the first time calculation unit 112 can determine the first time length. As shown in fig. 4b, after delaying the data signal by M time units, the data signal and the original clock signal can be signals with opposite phases, so that the second time calculation unit 122 can determine the second time length.
That is to say, the delay coefficient corresponding to the first delay unit 111 needs to be set to N, the delay coefficient corresponding to the second delay unit 121 needs to be set to M, the first time calculation unit 112 and the second time calculation unit 122 can accurately calculate the first time length corresponding to the unit interval of the clock signal and the second time length between the clock signal and the data signal, and then the calibration module 13 can determine the time offset between the clock signal and the data signal based on the first time length and the second time length.
In this disclosure, as shown in fig. 3, the driving calibration circuit may further include: and the control module 14 is respectively connected with the output end of the first time calculation unit 112, the output end of the second time calculation unit 122 and the control end of the calibration module 13.
The control module 14 is configured to control the calibration module 13 to calibrate the data signal or the clock signal according to the first time length output by the first time calculating unit 112 and the second time length output by the second time calculating unit 122, and output the calibrated data signal and the calibrated clock signal.
That is, in the present disclosure, the control module 14 first determines the signal to be calibrated and the specific time offset to be calibrated according to the first time length and the second time length respectively calculated by the first time calculation unit 112 and the second time calculation unit 122, and then controls the calibration module 13 to calibrate the signal to be calibrated.
Optionally, the calibration module 13 may also be composed of any device that can delay a signal, for example, a counter, a timer, or the like, which is not limited in this disclosure.
In practical use, if the clock signal delayed by the first delay unit 111 is not completely in phase or in phase with the original clock signal, or the data signal delayed by the second delay unit 121 is not completely in phase or in phase with the original clock signal, the first time calculation unit 112 and the second time calculation unit 122 may not accurately obtain the first time length and the second time length. Therefore, in the present disclosure, the delay coefficients corresponding to the first delay unit 111 and the second delay unit 121 may also be adjusted according to actual situations.
As shown in fig. 3, the control module 14 is further connected to the first delay unit 111 and the second delay unit 121, and is configured to adjust delay coefficients of the first delay unit 111 and the second delay unit 121.
For example, if the original delay coefficient of the first delay unit 111 is K, and the control module 14 determines that the delay coefficient required by the clock signal is M after calculating according to the first time length and the second time length, the delay coefficient corresponding to the first delay unit 111 may be adjusted to M.
The drive calibration circuit provided by the disclosure firstly utilizes a delay unit with a fixed delay coefficient to carry out delay processing on a data signal and a clock signal, then utilizes a time calculation unit to calculate a first time length corresponding to a unit interval of the clock signal and a second time length between a first change edge between the data signal and a second change edge of the clock signal, and then determines a signal to be calibrated and a calibration quantity according to the first time length and the second time length by a control module, and controls the calibration module to calibrate the data signal or the clock signal, so that the time offset between the data signal and the clock signal is in a preset range, and the reliability and the accuracy of the drive circuit are ensured.
Fig. 5 is a schematic flowchart of a driving calibration method according to an embodiment of the disclosure. The method may be performed by a DDIC provided by the present disclosure, or by a driving calibration circuit provided by the present disclosure, or by a control module in the driving calibration circuit, etc., which is not limited by the present disclosure. For convenience, the following embodiments of the present disclosure are explained with an example in which the driving calibration method is performed by a DDIC.
As shown in fig. 5, the drive calibration method includes, but is not limited to, the following steps:
Step 502 determines a second time duration between a first transition edge of the data signal and a second transition edge of the clock signal within the unit interval.
The meaning and description of the unit interval, the first variation edge, the second variation edge, the preset range, and the like of the clock signal may refer to the detailed description of any embodiment of the present disclosure, and are not repeated herein.
In this disclosure, after determining the first time length and the second time length, the DDIC may determine the signal to be calibrated and the corresponding amount to be calibrated according to the relationship between the first time length and the second time length, and then calibrate the signal to be calibrated, so that the time offset between the calibrated data signal and the clock signal is within a preset range.
Specifically, for example, the first time length and the second time length are determined, the DDCI may respectively delay the clock signal and the data signal by using the delay unit, then obtain the delayed signal by using the clock signal that is not delayed as the trigger clock, and determine the time offset between the data signal and the clock signal before the delay according to the phase of the delayed signal.
Optionally, the clock signal may be input to the signal input end of the first time calculation unit through the first delay unit, and then the clock signal is input to the clock input end of the first time calculation unit, so as to obtain the output signal of the first time calculation unit; under the condition that the output signal of the first time calculation unit and the clock signal do not meet a first relation, updating a delay coefficient of the first delay module until the output signal of the first time calculation unit and the clock signal meet the first relation; and determining the first time length according to the first delay coefficient of the first delay unit.
The possible implementation forms of the first delay unit and the first time calculating unit may refer to the detailed description of any embodiment of the disclosure, and are not described herein again.
In addition, the output signal of the first time calculating unit and the input signal of the first time unit may be in-phase or inverse phase, so that the first relationship reflects the phase relationship between the delayed clock signal and the original clock signal. Optionally, the first relationship may be in-phase or anti-phase, which is not limited by the present disclosure.
For example, if the first relationship is an inverse relationship, the first delay unit is a counter, and the first time calculating unit is a D flip-flop. After the clock signal is delayed by the first delay unit, if the product of the first delay coefficient and the time unit of the first delay unit is equal to the duration of the unit interval of the clock signal, that is, the clock signal is delayed by one unit interval, the signal output by the first time calculation unit and the clock signal can satisfy an inverse correlation. If the clock signal is not delayed by one unit interval or the delayed time length is longer than one unit interval, the signal output by the first time calculation unit and the clock signal do not satisfy the inverse correlation relationship.
For example, as shown in FIG. 4a, if the delayed clock signal is "CLK @ 3" in FIG. 4a th The delay signal, that is, the clock signal is delayed by 3 time units of the first delay unit, and then the delayed clock signal is output by the first time calculating unit, and the original clock signal does not necessarily satisfy the inverse correlation relationship, so that the first delay coefficient of the first delay unit can be modified until the delayed signal is as "clk @ n" in fig. 4a th delay "signal.
Similarly, the data signal can also be input into the signal input end of the second time calculation unit through the second delay unit; inputting the clock signal into a clock input end of a second time calculation unit to obtain an output signal of the second time calculation unit; under the condition that the output signal of the second time calculation unit and the data signal do not meet a second relation, updating the delay coefficient of the second delay unit until the output signal of the second time calculation unit and the data signal meet the second relation; and finally, determining a second time length according to a second delay coefficient of the second delay unit.
The possible implementation forms of the second delay unit and the second time calculating unit may refer to the detailed description of any embodiment of the disclosure, and are not described herein again.
In addition, the output signal of the second time calculating unit and the input signal of the second time unit may be in-phase or reverse phase, so that the second relationship reflects the phase relationship between the delayed data signal and the original clock signal. Optionally, the second relationship may be in-phase or anti-phase, which is not limited by the present disclosure.
For example, if the second relationship is an inverse relationship, the second delay unit is a counter, and the second time calculating unit is a D flip-flop. After the data signal is delayed by the second delay unit, if the product of the second delay factor and the time unit of the second delay unit is equal to the setup margin between the clock signal and the data signal, that is, the data signal is delayed and then is inverted with respect to the clock signal, the signal output by the second time calculating unit and the original clock signal can satisfy an inverse relationship. If the delayed data signal is not inverted with respect to the original clock signal, for example, the delayed time is shorter than the setup margin or longer than the setup margin, the signal output by the first time calculating unit and the clock signal do not satisfy the inverse relationship.
For example, as shown in FIG. 4b, if the delayed DATA signal is "DATA @ 2" in FIG. 4b nd The delay signal, that is, the data signal is delayed by the time unit of 2 second delay units, and then the delayed data signal output by the second time calculation unit and the original clock signal do not necessarily satisfy the inverse correlation relationship, so that the second delay unit's second delay unit can be modifiedDelaying the coefficient until the delayed signal is as "DTAT @ M" in FIG. 4a th delay "signal.
Optionally, if the first delay unit is the same as the second delay unit, that is, the time unit of the first delay unit is the same as the time unit of the second delay unit, for example, both are X picoseconds (ps), the DDIC may also calibrate the data signal or the clock signal according to the first delay coefficient and the second delay coefficient.
For example, if the predetermined range takes a value of half of the unit interval of the clock signal. The DDIC may then calibrate the data signal or the clock signal according to the following rules:
under the condition that the second delay coefficient is larger than the third delay coefficient, delaying the data signal according to the difference value of the second delay coefficient and the third delay coefficient and the time unit of the second delay unit; or,
when the second delay coefficient is smaller than the third delay coefficient, delaying the clock signal according to the difference value between the third delay coefficient and the first delay coefficient and the time unit of the second delay unit; or,
under the condition that the second delay coefficient is equal to the third delay coefficient, keeping the data signal and the clock signal unchanged;
and the third delay coefficient is half of the first delay coefficient.
For example, fig. 6 is a schematic diagram of another data signal and clock signal provided by the embodiment of the present disclosure. The first delay coefficient corresponding to the unit interval of the clock signal is N, the second delay coefficient corresponding to the time when the data signal meets the second relation after being delayed is M, and the third delay coefficient and the preset range are both N/2. As shown in fig. 6, if the DATA signal is "DATA1" in fig. 6, that is, M > N/2, it can be determined from fig. 6 that the time length of the DATA signal that needs to be delayed can be determined according to equation (1):
M-(M-N/2)＝N/2 (1)
if the DATA signal is "DATA2" in fig. 6, that is, M < N/2, it can be determined from fig. 6 that the clock signal can be delayed, and the time length of the clock signal that needs to be delayed can be determined according to equation (2):
M+(N/2-M)＝N/2 (2)
it should be noted that, the numerical value determined by equation (1) or (2) is the number of delay units that need to be used when performing delay by using the first delay unit or the second delay unit, or the number of times that the delay unit needs to count, and the specific delay time length, and also needs to be determined according to the numerical value determined by equation (1) or (2) and the time unit corresponding to the first delay unit (or the second delay unit). For example, the time unit corresponding to the first delay unit (or the second delay unit) is X ps, then the time offset of the data signal or the clock signal to be calibrated is: (N/2) × X (ps).
Or, if the first delay unit is different from the second delay unit, that is, the time unit of the first delay unit is different from the time unit of the second delay unit, for example, the time unit of the first delay unit is Xps, the time unit of the second delay unit is Yps, where X and Y have different values. The DDIC may also calibrate the data signal or the clock signal according to the following rules:
under the condition that the second time length is greater than the third time length, delaying the data signal according to the difference value between the second time length and the third time length; or,
when the second time length is smaller than the third time length, delaying the clock signal according to the difference value between the third time length and the first time length; or,
under the condition that the second time length is equal to the third time length, keeping the data signal and the clock signal unchanged;
wherein the third time length is half of the first time length.
In this case, the calibration process and the implementation manner may refer to the detailed description of the above embodiments, and are not described herein again.
In this embodiment, in the driving process, a first time length corresponding to a unit interval of a clock signal is first determined, then a second time length between a first change edge of a data signal and a second change edge of the clock signal is determined, then a signal to be calibrated and a quantity to be calibrated are determined according to the first time length and the second time length, and then the signal to be calibrated is calibrated, so that a time offset between the data signal and the clock signal is within a preset range, and reliability and accuracy of a driving circuit are ensured.
Fig. 7 is a schematic structural diagram of a driving calibration apparatus according to an embodiment of the disclosure. As shown in fig. 7, the apparatus 700 includes: a first determining module 71, a second determining module 72 and a processing module 73.
The first determining module 71 is configured to determine a first time length corresponding to a unit interval of a clock signal;
a second determining module 72, configured to determine a second time length between a first change edge of the data signal and a second change edge of the clock signal in the unit interval;
the processing module 73 is configured to calibrate the data signal or the clock signal according to the first time length and the second time length, so that a time offset between the data signal and the clock signal is within a preset range.
Optionally, the first determining module 71 is specifically configured to:
inputting the clock signal into a signal input end of a first time calculation unit through a first delay unit;
inputting the clock signal into a clock input end of the first time calculation unit to obtain an output signal of the first time calculation unit;
under the condition that the output signal of the first time calculation unit and the clock signal do not meet a first relation, updating a delay coefficient of the first delay module until the output signal of the first time calculation unit and the clock signal meet the first relation;
and determining the first time length according to a first delay coefficient of the first delay unit.
Optionally, the second determining module 72 is specifically configured to:
inputting the data signal into a signal input end of a second time calculation unit through a second delay unit;
inputting the clock signal into a clock input end of the second time calculation unit to obtain an output signal of the second time calculation unit;
under the condition that the output signal of the second time calculation unit and the data signal do not satisfy a second relationship, updating the delay coefficient of the second delay unit until the output signal of the second time calculation unit and the data signal satisfy the second relationship;
and determining the second time length according to a second delay coefficient of the second delay unit.
Optionally, the first delay unit is the same as the second delay unit, and the processing module 73 is further configured to:
and calibrating the data signal or the clock signal according to the first delay coefficient and the second delay coefficient.
Optionally, the processing module 73 is specifically configured to:
when the second delay coefficient is larger than a third delay coefficient, delaying the data signal according to the difference value of the second delay coefficient and the third delay coefficient and the time unit of the second delay unit; or,
when the second delay coefficient is smaller than the third delay coefficient, delaying the clock signal according to the difference between the third delay coefficient and the first delay coefficient and the time unit of the second delay unit; or,
keeping the data signal and the clock signal unchanged if the second delay factor is equal to the third delay factor;
wherein the third delay coefficient is half of the first delay coefficient.
Optionally, the processing module 73 is specifically configured to:
under the condition that the second time length is greater than a third time length, delaying the data signal according to the difference value of the second time length and the third time length; or,
when the second time length is smaller than the third time length, delaying the clock signal according to a difference value between the third time length and the first time length; or,
keeping the data signal and the clock signal unchanged if the second time length is equal to the third time length;
wherein the third time length is half of the first time length.
According to the driving calibration device, in the driving process, the first time length corresponding to the unit interval of the clock signal is firstly determined, then the second time length between the first change edge of the data signal and the second change edge of the clock signal is determined, then the signal to be calibrated and the amount to be calibrated are determined according to the first time length and the second time length, and then the signal to be calibrated is calibrated, so that the time offset between the data signal and the clock signal is within the preset range, and the reliability and the accuracy of the driving circuit are guaranteed.
Based on the driving calibration circuit provided in the above embodiment, the embodiment of the present disclosure may further provide a display driving integrated circuit DDIC, and the above explanation on the page display method embodiment is also applicable to the DDIC of this embodiment, so that details are not described herein again.
Based on the DDIC provided by the above embodiments, the embodiments of the present disclosure may also provide an apparatus. Fig. 8 is a schematic structural diagram of an apparatus provided in an embodiment of the present disclosure. As shown in fig. 8, the device includes DDIC81 and display panel 82.
DDIC81 may include a driving calibration circuit as in the above embodiments, which calibrates the data signal or the clock signal to make the time offset between the data signal and the clock signal within a preset range, and then uses the calibrated data signal to drive display on display panel 82.
According to the device of the embodiment, before driving the display panel, the DDIC firstly determines the first time length corresponding to the unit interval of the clock signal, then determines the second time length between the first change edge of the data signal and the second change edge of the clock signal, then determines the signal to be calibrated and the amount to be calibrated according to the first time length and the second time length, and further calibrates the signal to be calibrated, so that the time offset between the data signal and the clock signal is within a preset range, and the reliability and the accuracy of the driving circuit are guaranteed.
In the description of the present specification, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, "a plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise.
Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure, and that changes, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present disclosure.
Claims (13)
1. A drive calibration circuit, comprising: the device comprises a first time determining module, a second time determining module and a calibrating module;
the clock input end and the signal input end of the first time determination module are used for inputting clock signals, and the output end of the first time determination module is connected with the first input end of the calibration module so as to output a first time length corresponding to a unit interval of the clock signals to the calibration module;
a clock input end of the second time determination module is used for inputting a clock signal, a signal input end of the second time determination module is used for inputting a data signal, and an output end of the second time determination module is connected with a second input end of the calibration module so as to output a second time length between a first change edge of the data signal and a second change edge of the clock signal within the unit interval to the calibration module;
the calibration module is configured to calibrate the data signal or the clock signal according to the first time length and the second time length, so that a time offset between the data signal and the clock signal is within a preset range, and output the calibrated data signal and the calibrated clock signal.
2. The circuit of claim 1, wherein the first time determination module comprises a first delay unit and a first time calculation unit, and the second time determination module comprises a second delay unit and a second time calculation unit;
the input end of the first delay unit is connected with the clock input end of the first time calculation unit and the clock input end of the second time calculation unit respectively, and is used for inputting a clock signal;
the output end of the first delay unit is connected with the signal input end of the first time calculation unit;
the input end of the second delay unit is used for inputting the data signal, and the output end of the second delay unit is connected with the signal input end of the second time calculation unit.
3. The circuit of claim 2, further comprising: the control module is respectively connected with the output end of the first time calculation unit, the output end of the second time calculation unit and the control end of the calibration module;
and the control module is used for controlling the calibration module to calibrate the data signal or the clock signal according to the first time length output by the first time calculation unit and the second time length output by the second time calculation unit, and outputting the calibrated data signal and the calibrated clock signal.
4. The circuit of claim 3,
the control module is further connected with the first delay unit and the second delay unit and used for adjusting delay coefficients of the first delay unit and the second delay unit.
5. A drive calibration method, comprising:
determining a first time length corresponding to a unit interval of a clock signal;
determining a second time length between a first change edge of a data signal and a second change edge of the clock signal in the unit interval;
and calibrating the data signal or the clock signal according to the first time length and the second time length so as to enable the time offset between the data signal and the clock signal to be within a preset range.
6. The method of claim 5, wherein the determining a first length of time corresponding to a unit interval of the clock signal comprises:
inputting the clock signal into a signal input end of a first time calculation unit through a first delay unit;
inputting the clock signal into a clock input end of the first time calculation unit to obtain an output signal of the first time calculation unit;
under the condition that the output signal of the first time calculation unit and the clock signal do not meet a first relation, updating a delay coefficient of the first delay module until the output signal of the first time calculation unit and the clock signal meet the first relation;
and determining the first time length according to a first delay coefficient of the first delay unit.
7. The method of claim 5, wherein said determining a second length of time between a first changing edge of a data signal and a second changing edge of the clock signal within the unit interval comprises:
inputting the data signal into a signal input end of a second time calculation unit through a second delay unit;
inputting the clock signal into a clock input end of the second time calculation unit to obtain an output signal of the second time calculation unit;
under the condition that the output signal of the second time calculation unit and the data signal do not satisfy a second relationship, updating the delay coefficient of the second delay unit until the output signal of the second time calculation unit and the data signal satisfy the second relationship;
and determining the second time length according to a second delay coefficient of the second delay unit.
8. The method of claim 6 or 7, wherein the first delay cell is the same as the second delay cell, and wherein the calibrating the data signal or the clock signal according to the first time length and the second time length comprises:
and calibrating the data signal or the clock signal according to the first delay coefficient and the second delay coefficient.
9. The method of claim 8, wherein the calibrating the data signal or the clock signal according to the first delay factor and the second delay factor comprises:
when the second delay coefficient is larger than a third delay coefficient, delaying the data signal according to the difference value of the second delay coefficient and the third delay coefficient and the time unit of the second delay unit; or,
when the second delay coefficient is smaller than the third delay coefficient, delaying the clock signal according to the difference between the third delay coefficient and the first delay coefficient and the time unit of the second delay unit; or,
keeping the data signal and the clock signal unchanged if the second delay coefficient is equal to the third delay coefficient;
wherein the third delay factor is half of the first delay factor.
10. The method of any of claims 5-7, wherein calibrating the data signal or the clock signal according to the first length of time and the second length of time comprises:
under the condition that the second time length is greater than a third time length, delaying the data signal according to the difference value of the second time length and the third time length; or,
when the second time length is smaller than the third time length, delaying the clock signal according to a difference value between the third time length and the first time length; or,
keeping the data signal and the clock signal unchanged if the second time length is equal to the third time length;
wherein the third time length is half of the first time length.
11. A drive calibration device, comprising:
the first determining module is used for determining a first time length corresponding to a unit interval of a clock signal;
a second determining module, configured to determine a second time length between a first change edge of the data signal and a second change edge of the clock signal in the unit interval;
and the processing module is used for calibrating the data signal or the clock signal according to the first time length and the second time length so as to enable the time offset between the data signal and the clock signal to be within a preset range.
12. A display driver integrated circuit DDIC comprising a driver calibration circuit as claimed in any one of claims 1 to 4.
13. An apparatus comprising a DDIC and a display panel connected to each other;
the DDIC is used for calibrating a data signal or a clock signal by performing the method according to any one of claims 5 to 10, and driving the display panel to display based on the calibrated data signal and clock signal.
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