CN115774575A - A RISC-V vector processing unit implementation method and architecture - Google Patents

Abstract

The invention discloses a method for realizing a RISC-V vector processing unit, which is realized in a coprocessor mode based on a RISC-V processor vector expansion set. The vector processing unit comprises four ports, namely a main processor interaction port, a vector instruction request port, a vector instruction feedback port and a vector instruction memory write port. The vector processing unit includes a 3-stage pipeline supporting sequential dispatch, out-of-order execution, out-of-order write back, including decode and dispatch, execution, write back, and commit, with fetching and partial decode being performed in a scalar processor. And when the decoding and dispatching are taken as a first-stage pipeline and a vector unit receives a vector instruction of a main processor, the vector instruction is decoded and judged for pipeline conflict, if no pipeline conflict exists, the vector instruction can be dispatched, the execution is taken as a second-stage pipeline for executing the vector instruction, and the write-back is taken as a third-stage pipeline for writing back the vector instruction, wherein the write-back comprises a write-back scalar register and a write-back vector register.

Description

A RISC-V vector processing unit implementation method and architecture

technical field

The present invention relates to the technical field of RISC-V vector extension, and specifically refers to a method and architecture for realizing a RISC-V vector processing unit.

Background technique

Data-level parallelism has achieved stability in multimedia, data streaming, and recent machine learning and deep learning applications and RISC-V vector extensions, and is now ready to approve version 1.0, and the implementation of RISC-V vector extensions is currently implemented in China relatively few.

At present, there are generally two ways to implement vector extension. One design adopts the form of coprocessor to expand around the application processor. Although it increases the complexity of the interface between scalar and vector parts, it has strong scalability. The execution modules of vector instructions and scalar instructions can be completely separated. The traditional vector architecture based on multi-channel design is used internally to divide the vector registers into blocks and connect multiple same channels for parallel execution. The width of each channel Same as the maximum data size, each channel provides a corresponding ALU, but the area and power consumed by this design are huge. The early RISC-V vector extension version is suitable for multi-channel technology, but some changes introduced by its new RISC-V vector extension version 1.0 will make the vector processing unit design using multi-channel technology face the problem of cross-channel data processing, using multi-channel Technology needs to add additional module design when solving the problem of cross-channel data, which will increase the complexity of the entire vector unit design, especially when increasing the number of channels.

The other is to integrate the vector processing unit into the scalar processor to avoid the interface between the scalar and vector parts. The internal operation unit is designed in SIMD pipeline mode, and the processor executes in sequence and is single-cycle. Instead of queuing multiple instructions into the execution lane, execute them one at a time, eliminating the need for scheduling instruction design, can execute instructions in multiple cycles depending on operation and vector length, can add pipelining to increase maximum frequency, internal vector The register design is the same as the scalar processor, but provides multiple data ports, and the data path width matches the length of the vector register. This design simplifies the data transfer to the ALU, because the data of one register is transferred per cycle, power consumption and The area is relatively small, but the performance gain from adding vector extensions is relatively low. This design combines the advantages of the two design methods. First, the vector expansion of the scalar processor is carried out in the form of a coprocessor. In the execution stage of the scalar processor, it is used as a functional unit to define the operation and realization of the vector instruction and cooperate with the scalar execution unit. The separation of vector instructions improves the execution rate of vector instructions and reduces the dependence on scalar processors. No matter what the scalar processor architecture is, as long as the scalar processor supports the coprocessor port design, it can be vector-extended. The second design uses SIMD pipeline design in the execution module, which can not only simplify data transmission, but also avoid the additional design caused by the multi-channel technology facing the problem of cross-lane data, which can reduce the implementation complexity and bring better results. Performance improvements.

Contents of the invention

According to the deficiencies of the prior art, the present invention proposes a RISC-V vector processing unit implementation method and architecture, which is built on a scalar RISC-V main processor in the form of a coprocessor.

In order to solve the problems of the technologies described above, the technical solution of the present invention is:

A method for implementing a RISC-V vector processing unit, comprising the steps of:

S1. In the vector instruction preparation stage, execute in the scalar processor, fetch the vector instruction, simply decode the vector instruction, judge whether the scalar source operand is needed, read the scalar register, and judge the scalar data correlation with the scalar processor FIFO , can be dispatched, save the vector instruction destination register index information that needs to be written back to the scalar register in the scalar processor FIFO, and generate a vector instruction request signal, waiting for the vector processing unit to respond;

S2. In the stage of vector instruction decoding and dispatching, judge whether to respond to the vector request signal of the main processor according to the state of the vector unit itself;

S3, vector instruction execution stage, this stage is used for the execution of vector instructions, through multiple cycle execution to indirectly realize the execution of all elements in the register group, the total bit width VLEN bits of each processing element, that is, the length of a vector register, each Each execution unit adopts pipeline design, that is, SIMD pipeline;

S4. In the phase of vector instruction write back and delivery, the vector instruction can be written back to the scalar register and the vector register. The vector written back to the scalar register needs to pass the vector instruction feedback port to generate feedback information to the scalar processor and wait for the scalar processor to respond. It can be directly written back to the scalar processor through the feedback port of the vector processing unit, the instruction information saved in the scalar processor is removed, and the delivery of the instruction is completed, and the vector instruction written back to the vector register is directly passed Arbitration completes the delivery of the vector instruction by writing it back to the vector register and removing the information that saved the instruction during the dispatch phase.

Preferably, in the step S2, if the response is received, the vector instruction and the source scalar operand are received, and then the vector instruction is completely decoded, the format of the decoding instruction and the vector register are read, and the pipeline conflict is judged to decide whether to dispatch The vector instruction.

Preferably, in the step S3, the execution unit includes a read-write unit, a functional unit, and a data processing unit, the read-write unit is used to read and write the source operand, and the functional unit is used to execute the operation to be done by the instruction, the data The processing unit processes the data of the functional unit to obtain data to be finally written back.

Preferably, the pipeline conflicts include data conflicts and resource conflicts.

Preferably, the judgment of the pipeline conflict includes:

For resource conflicts, read-after-write dependencies, and write-after-write dependencies, solve: block the currently dispatched instruction until the resource conflict is resolved;

For write-before-read correlation, true data correlation, solution: mode (1) instruction blocking register has no instruction, the vector instruction is the vector instruction just received, if the required source operation data is being written back, it can be stored in the vector register The module reads data through the data bypass, otherwise the instruction is saved in the vector instruction register, which is the same as the method (2) below; the method (2) is the vector instruction stored in the instruction blocking register for the vector instruction, and the dependency is released , the operand needs to be read from the vector register module again, if the data is being written back, the data can be read in the vector register module through data bypass, otherwise the value in the vector register module can be read;

In the write-back mode, the vector instructions written back to the scalar register are dispatched sequentially, executed sequentially, and written back sequentially. Only one vector instruction written back to the scalar register can be executed at a time, and the vector instructions written back to the vector register are dispatched sequentially. In-order execution, out-of-order write-back, and multiple instructions are supported according to the size of instruction execution.

The present invention provides a RISC-V vector processing unit implementation architecture, including:

The vector instruction decoding module decodes according to the vector instruction encoding rules of the RISC-V vector extension standard document 1.0, and generates different instruction type information and operand register index information;

The vector instruction dispatching module is used for the dispatch of vector instructions, and uses an instruction blocking register group to save vector instruction information related to data release in the vector unit that has pipeline conflicts in the scalar processor. Receive the instruction information of the vector decoding module, send it to the vector pipeline judgment module, judge whether there is a pipeline conflict, if not, the vector instruction can be dispatched, if there is a pipeline conflict, block the vector instruction, and save the decoding of the vector instruction Information and the operand read from the vector register to the instruction blocking register group, wait for the pipeline conflict to be resolved, dispatch it and remove the value stored in the instruction blocking register;

The vector pipeline conflict judgment module, which is used to judge the pipeline conflict and vector instruction delivery, uses an instruction execution register group to save the vector instruction information being executed, and the order of the executed instructions, when receiving the vector instruction information that the dispatch module needs to dispatch , judge whether there is a pipeline conflict with the vector instruction being executed, when there is a pipeline conflict, a signal that cannot be dispatched is generated to the dispatch module, and when there is no pipeline conflict, a signal that can be dispatched is generated to the dispatch module, and the instruction information and execution The order is kept in the instruction execution register bank. The delivery of the vector instruction, when the signal from the end of the vector instruction is received, the instruction information stored in the instruction execution register group will be removed, that is, the delivery of the instruction will be completed;

The vector register block includes multiple read register port groups, a general purpose register port group, additional read register port groups required to execute multiple instructions simultaneously, and a write-back port group. The read register port group includes four read ports, so The write-back port group includes two write-back ports, which contain 32 VLEN-length general-purpose registers. The read port logic generally reads data according to the index value of the input register, but a data bypass is added to the read port. When writing back to the data register When the index is the same as the index of the source operand to be read, it is directly sent to the output port instead of reading the register value and writing port logic. Generally, vector instructions only need to use one write-back port to write back, and an additional write-back port is for The write back double-width instruction, because its register index differs by 1, does not produce the situation of writing the same register file, it only needs to judge that the register index value is different in the write back logic;

The vector control state register module is added and designed according to the RISC-V vector extension standard document, which can be used to execute vector control state configuration instructions, change the length of the current vector, vector register grouping and vector element size, and output it to the execution unit ;

The vector execution module is divided into vector load and storage unit, vector integer operation unit, vector integer multiplication and addition operation unit, vector floating point operation unit, vector permutation operation unit, vector reduction simple element and vector mask unit according to the type of vector instruction;

The vector write-back module includes a write-back scalar register module and a write-back vector register module (VWBCK_VD).

As preferred: in the vector execution module: the vector integer operation unit is responsible for the operation instruction of vector integer addition, subtraction, multiplication and division, the vector integer multiplication and addition operation unit is responsible for the vector vector integer multiplication and addition operation instruction; the vector floating point operation unit is responsible for the vector floating point instruction operation. The vector replacement operation unit is responsible for the execution of vector replacement instructions; the vector reduction simple unit is responsible for the instructions of vector reduction instructions; the vector mask unit is responsible for the execution of vector mask instructions; the vector execution module adopts SIMD pipeline design, including read and write units, functions The unit, the data processing unit, and the read-write unit are designed with a state machine, which is divided into two states of 0 and 1. When the state machine is in the 0 state, it waits for the enable signal of the execution unit. If the execution unit is selected by the vector instruction, the enable signal will be generated. Signal, if there is an enable signal, it will jump to 1 state; write operation, save the instruction information to be operated by executing the instruction in the internal register, the instruction information includes register index, vector length, vector element width, and operation object; read The operation will judge whether the next operand needs to be read according to the length of the vector. When the state machine is in the 1 state, it will judge whether the instruction execution is over. If it continues to execute, it will maintain the 1 state. If it ends, it will jump to the 0 state. The functional unit is equivalent to The SIMD execution unit can support the execution of multiple vector elements with different bit widths. The maximum execution element bit width is VLEN. The data processing unit processes the output data of the functional units to obtain the final write-back data.

As a preference: in the vector write-back module: if the current vector instruction needs to be written back to the scalar register, it is directly written back through the feedback port of the vector processing unit; if the vector instruction needs to be written back to the vector register, only one instruction can be written back directly when executing , when two simultaneously executed instructions need to be written back, they are arbitrated according to the order of execution instructions stored in the instruction execution register group, the one dispatched first can be written back first, and the write-back data dispatched later is stored in its corresponding FIFO , until no data is written back, read from the FIFO and write back to the vector register. After the instruction is executed, the instruction execution register will judge whether the instruction execution is completed according to whether the corresponding FIFO is empty and the status of the execution module where the instruction is located. If it is completed, it will be removed. The instruction message is delivered.

The present invention has following characteristics and beneficial effect:

In this design, the vector expansion of the scalar processor is carried out in the form of a coprocessor. When designing the vector unit, only one instruction of this type is executed each time for the vector instruction written back to the scalar register, so that it can be written back in a strict sense. That is, the signal of the main processor is not required for arbitration write-back, which reduces the dependence on the scalar processor. Secondly, the vector instruction written back to the vector register is defined as a short-cycle instruction, so that the main processor does not need to write back to the vector register. The main processor gives feedback, completes the execution and delivery directly in the vector unit, improves the execution speed of the vector instruction, and enhances its scalability. When another RISC-V scalar processor supports the coprocessor port design, it can execute it. Vector expansion. Finally, the internal execution module design of the vector unit is a SIMD pipeline design. This design is superior to the multi-channel-based architecture design. The purpose is to minimize the pressure on the vector registers, do not need to divide the vector registers, simplify data transmission, and provide a unified execution method for vector instructions, avoiding cross-lane data The additional design brought by the problem reduces the implementation complexity and improves the performance.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is an architecture diagram of an implementation method of an embodiment of the present invention.

Fig. 2 is a schematic diagram of a decoding module in an embodiment of the present invention.

Fig. 3 is a schematic diagram of the dispatch module in the embodiment of the present invention.

FIG. 4 is a schematic diagram of a pipeline conflict judgment module in an embodiment of the present invention.

FIG. 5 is a schematic diagram of a vector register module in an embodiment of the present invention.

Fig. 6 is a schematic diagram of a vector control state module in an embodiment of the present invention.

Fig. 7 is a schematic diagram of the execution module in the embodiment of the present invention.

FIG. 8 is a schematic diagram of a write-back module in an embodiment of the present invention.

Fig. 9 is a schematic diagram of a vector unit in an embodiment of the present invention.

Detailed ways

It should be noted that, in the case of no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

The present invention provides a RISC-V vector processing unit implementation architecture, as shown in Figure 2-Figure 9, including a vector instruction decoding module: decode according to the vector instruction encoding rules of the RISC-V vector extension standard document 1.0, and generate Different instruction type information, operand register index information.

Vector instruction dispatching module: This module is used for dispatching vector instructions, and uses an instruction blocking register group to store vector instruction information related to data release in the vector unit that has pipeline conflicts in the scalar processor. Receive the instruction information of the vector decoding module, send it to the vector pipeline judgment module, judge whether there is a pipeline conflict, if not, the vector instruction can be dispatched, if there is a pipeline conflict, block the vector instruction, and save the decoding of the vector instruction Information and operands read from the vector registers to the instruction block register set, wait for the pipeline conflict to be resolved, dispatch it and remove the value held in the instruction block register.

Vector pipeline conflict judgment module: This module is used to judge pipeline conflicts and vector instruction delivery. It uses an instruction execution register group to save the vector instruction information being executed and the order of execution instructions. When receiving the vector instruction information that the dispatch module needs to dispatch , judge whether there is a pipeline conflict with the vector instruction being executed, when there is a pipeline conflict, a signal that cannot be dispatched is generated to the dispatch module, and when there is no pipeline conflict, a signal that can be dispatched is generated to the dispatch module, and the instruction information and execution The order is kept in the instruction execution register bank. When the vector instruction is delivered, the instruction information stored in the instruction execution register group will be removed when the signal from the end of the vector instruction is received, that is, the delivery of the instruction is completed.

Vector register block: Multiple read register port groups (one group containing four read ports), including one general purpose register port group and additional read register port groups required to execute multiple instructions simultaneously, one writeback port group (one group containing Two write-back ports), internally contains 32 general-purpose registers of VLEN length, the read port logic generally reads data according to the input register index value, but adds data bypass here at the read port, when the register index of the write-back data and the register index to be read When the source operand index is the same, it is directly sent to the output port instead of reading the register value. Write port logic. Generally, vector instructions only need to use one write-back port to write back. An additional write-back port is for write-back double-width instructions. Since the register index differs by 1, the same register file will not be written. It is only necessary to judge that the index values of the registers are different in the write-back logic.

The vector control state register module is added and designed according to the RISC-V vector extension standard document, which can be used to execute vector control state configuration instructions, change the length of the current vector, vector register grouping and vector element size, and output it to the execution unit .

Vector execution module: divided into vector load and storage unit (VLSU), vector integer operation unit (V_INT_ALU), vector integer multiplication and addition operation unit (V_INT_MAC), vector floating point operation unit (V_FP), vector permutation operation unit according to the type of vector instruction (V_PERMUTE), Vector Reduced Simple Elements (V_REDUCT), and Vector Masked Units (VMASK). The vector integer operation unit is responsible for the operation instruction of vector integer addition, subtraction, multiplication and division, and the vector integer multiplication and addition operation unit is responsible for the operation instruction of vector vector integer multiplication and addition. The vector floating-point operation unit is responsible for vector floating-point instruction operations. The vector permutation operation unit is responsible for the execution of vector permutation instructions. The vector reduction simple element is responsible for the instruction of the vector reduction instruction. The vector mask unit is responsible for the execution of vector mask instructions. The vector execution module adopts SIMD pipeline design, including read and write units, functional units, and data processing units. The reading and writing unit is designed with a state machine, which is divided into two states of 0 and 1. When the state machine is in the 0 state, it waits for the execution unit to enable the signal. If the vector instruction selects the execution unit, it will generate the enable signal. There is an enable signal It will jump to state 1. In the write operation, the instruction information (including register index, vector length, vector element width, and operation object) to be operated by the execution instruction is stored in the internal register, and in the read operation, it is judged whether the next operand needs to be read according to the vector length. When the state machine is in the 1 state, it will judge whether the execution of the instruction is over, if it continues to execute, it will maintain the 1 state, and if it ends, it will jump to the 0 state. The functional unit is equivalent to a SIMD execution unit, which can support the execution of multiple vector elements with different bit widths, and the maximum bit width of the execution element is VLEN. The data processing unit processes the output data of the functional unit to obtain the final write-back data.

The vector write-back module includes the write-back scalar register module (VWBCK_RD) and the write-back vector register module (VWBCK_VD). If the current vector instruction needs to be written back to the scalar register, it can be directly written back through the feedback port of the vector processing unit. If the vector instruction needs to be written back The vector register can be directly written back when only one instruction is executed. When two simultaneously executed instructions need to be written back, it is arbitrated according to the order of execution instructions saved in the instruction execution register group. The dispatched write-back data is stored in its corresponding FIFO until it is read from the FIFO and written back to the vector register when there is no data to write back. After the instruction is executed, the instruction execution register will judge whether the instruction execution is completed according to whether the corresponding FIFO is empty and the status of the execution module where the instruction is located. If it is completed, the instruction information will be removed to complete the delivery.

Among them, pipeline conflict judgment, for resource conflict, read-after-write dependency (WAR) and write-after-write dependency (WAW), resolve: block the currently dispatched instruction until the resource conflict is resolved. For read-after-write dependency (RAW), true data dependency, solve: (1) There is no instruction in the instruction blocking register, the vector instruction is the vector instruction just received, if the required source operation data is being written back, it can be in The vector register module reads data through the data bypass, otherwise the instruction is saved in the vector instruction register, the same as (2) below. (2) For the vector instruction stored in the instruction blocking register, after the dependency is released, it is necessary to read the operand from the vector register module again. If the data is being written back, it can pass the data in the vector register module. Bypass reads data, otherwise reads the value inside the vector register block.

In the write-back mode, the vector instructions written back to the scalar register are dispatched sequentially, executed sequentially, and written back sequentially. Only one vector instruction written back to the scalar register can be executed at a time. This is done in order not to change the scalar processor as much as possible and also The generality of the vector processing unit is realized as much as possible, and the vector instructions written back to the vector register are dispatched sequentially, executed out of order, and written back out of order, and multiple instructions can be executed according to the size of the instruction execution.

The present invention also provides a method for realizing the RISC-V vector processing unit, which is based on the vector extension set of the RISC-V processor and implemented in the form of a co-processor. The vector processing unit includes four ports, which are the main processor interaction port, the vector instruction request port, the vector instruction feedback port, and the vector instruction memory write port. The vector processing unit includes a 3-stage pipeline, supports in-order dispatch, out-of-order execution, and out-of-order write-back, including decoding and dispatch, execution, write-back, and delivery. Its instruction fetch and partial decoding are completed in the scalar processor. The decoding and dispatching are used as the first-stage pipeline. When the vector unit receives the vector instruction from the main processor, it decodes the vector instruction and judges the pipeline conflict. If there is no pipeline conflict, it can be dispatched. The execution is the second stage. The pipeline is used for the execution of vector instructions, including vector load and store unit (VLSU), vector integer operation unit (V_INT_ALU), vector integer multiply and add operation unit (V_INT_MAC), vector floating point operation unit (V_FP), vector permutation operation unit ( V_PERMUTE), Vector Reduced Simple Elements (V_REDUCT), and Vector Masked Units (VMASK). The write-back is used as the third-stage pipeline for the write-back of vector instructions, including writing back to scalar registers and writing back to vector registers.

Specifically, as shown in Figure 1, the decoding unit of the main processor decodes the opcode of the fetched instruction, judges whether it is a vector instruction, and judges whether a scalar source operand and write-back result are needed to a scalar register, If a scalar source operand is needed, it is read from the general-purpose register bank, and the source operand is read out. If it needs to be written back, the host processor stores the index information of the target register in the pipeline control module of the host processor until the write Back to finish. The main processor will maintain data dependencies. If the vector instruction has a data dependency with the instruction being executed (including scalar instructions and vector instructions that need to be written back to the scalar register), it will wait for the data dependency to be touched before the vector instruction An instruction dispatch to a vector processing unit includes the vector instruction req_inst, the values of the two scalar source operands (req_rs1, req_rs2), and the vector instruction request signal req_valid.

The vector processing unit judges whether to receive the vector instruction through the request channel according to the signals of the dispatch module (disp_ready) and the pipeline conflict judgment module (pipc_ready). If the vector instruction can be received, it will set req_ready to 1 to respond to the vector instruction request signal sent by the main processor, and then The vector instruction is fully decoded in the decoding module, and the execution unit required for the judgment of the instruction format is decoded, and two source operands (if the scalar source operand is the scalar source operand sent by the main processor, if necessary The value of the vector register needs to be read from the vector register) and the destination operand. Send the index value (dec_idx) of the vector register that needs to be read to the general port r0 of the vector register, and read vrf_rd_r0, and send it to the dispatch module or the vector state control module together with the information required for instruction execution (dec_info). According to the RISC-V vector extension instruction encoding, it will be divided into three categories, vector load and store instructions, vector state setting instructions (CSR setting instructions), and vector arithmetic instructions, where the vector state setting instructions will be sent directly to the Executed in the CSR module, there is no need to dispatch and check for pipeline conflicts in the vector unit, because they do not need to interact with the vector register VRF, whose two source and destination operands are scalar register indexes, which are already referenced in the host processor. It checks for pipeline conflicts. Also, for these instructions, a write back to the main processor (csr_wbck_dat) can be requested immediately. Before the vector setting instruction is executed, the control status register must be updated only when the preceding instruction is executed or executed. This operation is implemented in the vector unit by judging whether there is a blocked instruction. When there is an instruction blocked in the vector unit, the vector unit does not receive the instructions dispatched by the main processor, including CSR instructions, and only the instructions waiting for the dispatch of the main processor are already being executed. During or after execution, the CSR setting command can be received and the CSR value can be updated without affecting the previously executed commands. After the other instructions are decoded, they need to be sent to the execution module through the dispatch module.

The vector processing unit first sends the vector instruction information (disp_pipc_idx, disp_pipc_info) to the pipeline conflict module to judge the pipeline conflict in the dispatch module. If there is a conflict, the pipeline conflict module will set pipc_o_dep to 1, tell the dispatch module to block the dispatch of the instruction, and if the instruction is For true data dependency, it is necessary to set re_rd_rf to 1, wait for the pipeline conflict to be resolved, and re-read the vector register to obtain the source operand when dispatching the instruction.

In judging pipeline conflicts, the vector processing unit compares the vector information sent by the dispatch module with the information of the executing vector instructions stored inside, and judges whether there is a pipeline conflict. This module will generate control signals sel_rd_itag and sel_wbck_itag, sel_rd_itag is used to select the execution module to occupy the extra read port of the vector register and send the instruction information to the module that the vector instruction needs to execute. sel_wbck_itag is used to control writeback.

Receive the vector instruction information (disp_exu_idx, disp_exu_info, disp_exu_dat) from the dispatch module through the execution module, and read the vector state data csr_exu_dat of the current vector control state module, send it to the execution module of the vector instruction according to sel_rd_itag for execution, and finally write the output back data. The vector load and storage unit is responsible for the vector unit to access the internal memory of the scalar processor. The execution of the vector load instruction needs to set memory_read_ready and memory_read to 1, send the required address information memory_addr and the read element size memory_size, and the scalar processor receives the vector read access After the memory, memory_read_valid will be generated and the required read data memory_read_dat will be sent to the vector load and storage unit. The execution of the vector storage instruction needs to set memory_write_valid to 1 and memory_read to 0, send the required address information memory_addr and the element size memory_size to be written, and the scalar processor will generate memory_read_ready after receiving the vector read access memory and send the required write data memory_write_dat to the main processor's memory. For vector load and store units, load instructions and store instructions cannot be executed at the same time, unlike other execution units, each execution reads or writes a vector element size instead of a vector register width VLEN, but for vector modules (load instructions) write The return is written back with a VLEN, and each time a vector element is loaded, it is put into a register with a length of VLEN until it is full or read and written back. Other implementations include vector integer operation unit, vector integer multiplication and addition operation unit, vector floating point operation unit, vector permutation operation unit, vector reduction operation unit, vector integer operation unit is responsible for the operation instruction of vector integer addition, subtraction, multiplication and division, vector integer multiplication and addition The operation unit is responsible for the operation instructions of vector-vector integer multiplication and addition. The vector floating-point operation unit is responsible for vector floating-point instruction operations. The vector permutation operation unit is responsible for the execution of vector permutation instructions. The vector reduction operation unit is responsible for the instruction of the vector reduction instruction. The vector mask unit is responsible for the execution of vector mask instructions. The design of vector execution module adopts SIMD pipeline design, including read and write unit, function unit and data processing unit. The reading and writing unit is designed with a state machine, which is divided into two states of 0 and 1. When the state machine is in the 0 state, it waits for the execution unit to enable the signal. If the vector instruction selects the execution unit, it will generate the enable signal. There is an enable signal It will jump to state 1. Write operation, 0 state, save the instruction information (disp_exu_info), index information (disp_exu_idx) and csr_data to be operated by the execution command sent by the first dispatch module in the internal register, 1 state, the next operation that needs to be read The number is stored in a register. In the read operation, judge whether the next operand needs to be read according to the value of csr and the instruction, and read the next operand through the extra port r1 or r2 of the register. When the state machine is in the 1 state, it will judge whether the execution of the instruction is over, if it continues to execute, it will maintain the 1 state, and if it ends, it will jump to the 0 state. The functional unit is equivalent to the ALU, which is in charge of instructions, and the data processing unit processes the output data of the functional unit to obtain the final write-back data.

The output data of each functional unit of the execution module (vlsu_o, v_int_alu_o, v_int_mac_o, v_fp_o, v_permute_o, v_reduct_o, vmask_o) is divided into write back scalar register (wbck_rd) and write back vector register by the vector write back and delivery module (wbck_vd), since the instruction to write back to the scalar register is written back sequentially, it can be directly written back to the scalar processor through the feedback channel of the vector processing unit, and delivered by the scalar processor. For the vector instructions written back to the vector register, generally speaking, they can be written back directly, but when two simultaneously executed instructions need to be written back at the same time, at this time, it is necessary to arbitrate according to the dispatch order sel_wbck_itag. In order not to block the pipeline, the dispatched instruction writes back the data, caches it in the FIFO, waits for the dispatched instruction to write back or if there is no data to write back, then reads its data from the FIFO and writes it back, and waits for the vector instruction to be written back Wbck_sign will be generated, and the pipeline conflict module will judge whether the instruction is completed according to the status information exu_status of each module. If it is completed, the instruction information in the instruction saving register will be canceled to complete the delivery of the instruction.

The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, without departing from the principle and spirit of the present invention, various changes, modifications, replacements and modifications to these implementations, including components, still fall within the protection scope of the present invention.

Claims (8)

1. a RISC-V vector processing unit implementation method, is characterized in that, comprises the steps: S1. In the vector instruction preparation stage, execute in the scalar processor, fetch the vector instruction, simply decode the vector instruction, judge whether the scalar source operand is needed, read the scalar register, and judge the scalar data correlation with the scalar processor FIFO , can be dispatched, save the vector instruction destination register index information that needs to be written back to the scalar register in the scalar processor FIFO, and generate a vector instruction request signal, waiting for the vector processing unit to respond; S2. In the stage of vector instruction decoding and dispatching, judge whether to respond to the vector request signal of the main processor according to the state of the vector unit itself; S3, vector instruction execution stage, this stage is used for the execution of vector instructions, through multiple cycle execution to indirectly realize the execution of all elements in the register group, the total bit width VLEN bits of each processing element, that is, the length of a vector register, each Each execution unit adopts pipeline design, that is, SIMD pipeline; S4. In the phase of vector instruction write back and delivery, the vector instruction can be written back to the scalar register and the vector register. The vector written back to the scalar register needs to pass the vector instruction feedback port to generate feedback information to the scalar processor and wait for the scalar processor to respond. It can be directly written back to the scalar processor through the feedback port of the vector processing unit, the instruction information saved in the scalar processor is removed, and the delivery of the instruction is completed, and the vector instruction written back to the vector register is directly passed Arbitration completes the delivery of the vector instruction by writing it back to the vector register and removing the information that saved the instruction during the dispatch phase. 2. A kind of RISC-V vector processing unit implementation method according to claim 1, is characterized in that, in described step S2, if respond, then receive this vector instruction and source scalar operand, then carry out completely to vector instruction Decoding, decoding the format of the instruction and reading the vector register, and judging the pipeline conflict, and deciding whether to dispatch the vector instruction. 3. A kind of RISC-V vector processing unit realization method according to claim 1, it is characterized in that, in described step S3, described execution unit comprises read-write unit, function unit, data processing unit, described read-write The unit is used to read and write the source operand, the functional unit is used to execute the operation to be done by the instruction, and the data processing unit processes the data of the functional unit to obtain the final data to be written back. 4. A method for implementing a RISC-V vector processing unit according to claim 2, wherein said pipeline conflicts include data conflicts and resource conflicts. 5. a kind of RISC-V vector processing unit implementation method according to claim 2, is characterized in that, the judgment of described pipeline conflict comprises: For resource conflicts, read-after-write dependencies, and write-after-write dependencies, solve: block the currently dispatched instruction until the resource conflict is resolved; For write-before-read correlation, true data correlation, solution: mode (1) instruction blocking register has no instruction, the vector instruction is the vector instruction just received, if the required source operation data is being written back, it can be stored in the vector register The module reads data through the data bypass, otherwise the instruction is saved in the vector instruction register, which is the same as the method (2) below; the method (2) is the vector instruction stored in the instruction blocking register for the vector instruction, and the dependency is released , the operand needs to be read from the vector register module again, if the data is being written back, the data can be read in the vector register module through data bypass, otherwise the value in the vector register module can be read; In the write-back mode, the vector instructions written back to the scalar register are dispatched sequentially, executed sequentially, and written back sequentially. Only one vector instruction written back to the scalar register can be executed at a time, and the vector instructions written back to the vector register are dispatched sequentially. In-order execution, out-of-order write-back, and multiple instructions are supported according to the size of instruction execution. 6. realize the framework of a kind of RISC-V vector processing unit implementation method described in any one of claims 1-5, it is characterized in that, comprising: The vector instruction decoding module decodes according to the vector instruction encoding rules of the RISC-V vector extension standard document 1.0, and generates different instruction type information and operand register index information; The vector instruction dispatching module is used for the dispatch of vector instructions, and uses an instruction blocking register group to save vector instruction information related to data release in the vector unit that has pipeline conflicts in the scalar processor. Receive the instruction information of the vector decoding module, send it to the vector pipeline judgment module, judge whether there is a pipeline conflict, if not, the vector instruction can be dispatched, if there is a pipeline conflict, block the vector instruction, and save the decoding of the vector instruction Information and the operand read from the vector register to the instruction blocking register group, wait for the pipeline conflict to be resolved, dispatch it and remove the value stored in the instruction blocking register; The vector pipeline conflict judgment module, which is used to judge the pipeline conflict and vector instruction delivery, uses an instruction execution register group to save the vector instruction information being executed, and the order of the executed instructions, when receiving the vector instruction information that the dispatch module needs to dispatch , judge whether there is a pipeline conflict with the vector instruction being executed, when there is a pipeline conflict, a signal that cannot be dispatched is generated to the dispatch module, and when there is no pipeline conflict, a signal that can be dispatched is generated to the dispatch module, and the instruction information and execution The order is kept in the instruction execution register bank. The delivery of the vector instruction, when the signal from the end of the vector instruction is received, the instruction information stored in the instruction execution register group will be removed, that is, the delivery of the instruction will be completed; The vector register block includes multiple read register port groups, a general purpose register port group, additional read register port groups required to execute multiple instructions simultaneously, and a write-back port group. The read register port group includes four read ports, so The write-back port group includes two write-back ports, which contain 32 VLEN-length general-purpose registers. The read port logic generally reads data according to the index value of the input register, but a data bypass is added to the read port. When writing back to the data register When the index is the same as the index of the source operand to be read, it is directly sent to the output port instead of reading the register value and writing port logic. Generally, vector instructions only need to use one write-back port to write back, and an additional write-back port is for The write back double-width instruction, because its register index differs by 1, does not produce the situation of writing the same register file, it only needs to judge that the register index value is different in the write back logic; The vector control state register module is added and designed according to the RISC-V vector extension standard document, which can be used to execute vector control state configuration instructions, change the length of the current vector, vector register grouping and vector element size, and output it to the execution unit ; The vector execution module is divided into vector load and storage unit, vector integer operation unit, vector integer multiplication and addition operation unit, vector floating point operation unit, vector permutation operation unit, vector reduction simple element and vector mask unit according to the type of vector instruction; The vector write-back module includes a write-back scalar register module and a write-back vector register module (VWBCK_VD). 7. A kind of RISC-V vector processing unit implementation framework according to claim 6, is characterized in that, In the vector execution module: the vector integer operation unit is responsible for the operation instruction of vector integer addition, subtraction, multiplication and division, the vector integer multiplication and addition operation unit is responsible for the vector vector integer multiplication and addition operation instruction; the vector floating point operation unit is responsible for the vector floating point instruction operation. The vector replacement operation unit is responsible for the execution of vector replacement instructions; the vector reduction simple unit is responsible for the instructions of vector reduction instructions; the vector mask unit is responsible for the execution of vector mask instructions; the vector execution module adopts SIMD pipeline design, including read and write units, functions The unit, the data processing unit, and the read-write unit are designed with a state machine, which is divided into two states of 0 and 1. When the state machine is in the 0 state, it waits for the enable signal of the execution unit. If the execution unit is selected by the vector instruction, the enable signal will be generated. Signal, if there is an enable signal, it will jump to 1 state; write operation, save the instruction information to be operated by executing the instruction in the internal register, the instruction information includes register index, vector length, vector element width, and operation object; read The operation will judge whether the next operand needs to be read according to the length of the vector. When the state machine is in the 1 state, it will judge whether the instruction execution is over. If it continues to execute, it will maintain the 1 state. If it ends, it will jump to the 0 state. The functional unit is equivalent to The SIMD execution unit can support the execution of multiple vector elements with different bit widths. The maximum execution element bit width is VLEN. The data processing unit processes the output data of the functional units to obtain the final write-back data. 8. A kind of RISC-V vector processing unit implementation framework according to claim 6, is characterized in that, In the vector write-back module: if the current vector instruction needs to be written back to the scalar register, it is directly written back through the feedback port of the vector processing unit; if the vector instruction needs to be written back to the vector register, only one instruction can be written back directly when executing, for two When two simultaneously executed instructions need to be written back, arbitration is performed according to the order of execution instructions stored in the instruction execution register group. The dispatched ones can be written back first, and the written-back data dispatched later will be stored in the corresponding FIFO until there is no more When the data is written back, it is read from the FIFO and written back to the vector register. After the instruction is executed, the instruction execution register will judge whether the instruction execution is completed according to whether the corresponding FIFO is empty and the status of the execution module where the instruction is located. If it is completed, the instruction information will be removed. Complete the delivery.

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