CN101021778A - Computing group structure for superlong instruction word and instruction flow multidata stream fusion - Google Patents

Abstract

The invention discloses a calculation group structure combining super long instruction word and single instruction stream and multiple data streams. The main controller is responsible for the movement of instructions and data. The instructions are loaded into the microcontroller, the data is loaded into the data buffer and receives its output; the data buffer receives the data from the main controller, provides operands for the calculation group and receives its calculation results, and finally outputs to The main controller; the micro-controller receives the super-long instruction word sequence of the main controller, broadcasts it to the calculation group and executes it in parallel in each processing unit after decoding; The instruction sequence is the same, and the data is taken from a different unit of the data buffer. The invention can support data-level parallelism and instruction-level parallelism simultaneous development, and can improve the processing performance of computing-intensive applications in various ways by combining ultra-long instruction word, single instruction stream, multiple data streams and software pipelining technology.

Description

Computational group structure based on fusion of VLW and SIMD

technical field

The invention mainly relates to instruction processing technology in microprocessor design, especially applied to processors oriented to calculation-intensive calculations, and particularly refers to a calculation group structure in which ultra-long instruction words and single instruction stream and multiple data streams are fused.

Background technique

Instruction Level Parallelism (ILP for short) is the main way to develop parallelism in microprocessor design. Unrelated instructions can be executed in parallel to improve the efficiency of processor execution, such as superscalar technology and super long Instruction word technology (Very Long Instruction Word, referred to as VLIW). VLIW technology configures multiple functional components on the hardware, and they can execute instructions in parallel. The compiler is responsible for organizing the program into a sequence of super long instruction words. Each new instruction word contains multiple original instructions that can be executed in parallel. Mapping to functional components for processing, so as to achieve the purpose of developing instruction-level parallelism, without complex hardware detection correlation and launch logic. In computing-intensive applications such as multimedia and scientific computing, there is also a large amount of data-level parallelism (DLP for short), and data of the same type or structure often needs to perform the same one or a series of operations. The data-level parallelism in such programs can be effectively exploited by using special instruction processing techniques, thereby improving the execution performance of the processor.

First, data-level parallelism development can be transformed into instruction-level parallelism development. Software pipelining is an effective compilation and scheduling method for developing instruction-level parallelism. The compiler reschedules instructions from different cycle cycles that do not have data correlation through loop unrolling to form a new loop body, thereby increasing the number of processors in the processor. The number of instructions that can be executed in parallel to solve data dependencies. The data correlation between instructions in a program containing a large amount of data-level parallelism is mainly the correlation between storage and calculation, and software pipelining technology can easily resolve this correlation. Software pipelining can be used simultaneously with superscalar or VLIW techniques to develop ILP.

Vector processing technology is an effective method to improve the batch data processing performance of the processor. Using the idea of time overlap, data parallelism is transformed into instruction parallelism. By vectorizing the loop statements used to process the same operation, it can not only reduce the The amount of code can be reduced, and the control correlation between loop iterations can be hidden in the vector instructions to improve the execution efficiency of the hardware. Vector link technology can effectively reduce the storage capacity of intermediate results on the basis of vector processing, and relieve the allocation pressure of vector registers.

Single Instruction, Multiple Data (SIMD) technology is a resource duplication technology that develops data-level parallelism by configuring multiple parallel processing units or dividing a processing unit into multiple data paths. The control signal of one instruction can control multiple computing components to work simultaneously, but the processed data comes from multiple data streams. Both Intel's IA-32 instruction set and IA-64 instruction set have instruction extensions for SIMD, which can improve the performance of numerical computing applications.

It can be seen that the current parallel development of computing-intensive applications such as multimedia and scientific computing is mainly based on independent instruction-level parallelism or data-level parallel development. In the case of continuous expansion of application scale and increasing complexity, parallelization using the above method The difficulty becomes larger, and the performance gain obtained is also continuously reduced. How to support the simultaneous development of data-level parallelism and instruction-level parallelism on the hardware structure is a new idea to solve such problems.

Contents of the invention

The technical problem to be solved by the present invention is that: in view of the problems existing in the prior art, the present invention provides a development that can support data-level parallelism and instruction-level parallelism at the same time, and can combine ultra-long instruction word technology, single instruction stream multiple data Streaming technology and software pipelining technology further improve the execution performance of computing-intensive applications on processors in multiple ways. The computing group structure of the fusion of ultra-long instruction words and single instruction stream multiple data streams.

In order to solve the above-mentioned technical problems, the solution proposed by the present invention is: a computing group structure in which ultra-long instruction words and single instruction streams and multiple data streams are fused, and is characterized in that it includes a main controller, data buffer, SIMD computing group and The microcontroller, the data buffer and the microcontroller are respectively connected to the main controller, and the data buffer and the microcontroller are connected through the SIMD computing group. Into the storage unit in the microcontroller, control the start and pause of the SIMD calculation group, transfer the required source operation data into the data buffer, and receive the final calculation result in the data buffer; the data buffer unit receives the data transmitted from the main controller, And store it in a specific organizational way, provide the source operands required by the calculation for the SIMD calculation group, receive the output result of the calculation group after the calculation, and output the final result to the main controller; the microcontroller part receives the super data provided by the main controller After decoding the long instruction word sequence, each operation is dispatched in the form of broadcast and mapped to the corresponding processing unit F of each processing unit of the SIMD computing group to execute in parallel; the SIMD computing group is a plurality of parallel operations organized in the form of SIMD Each processing unit has the same structure and is configured with multiple processing components. The executed instruction sequences all come from the microcontroller, but the required calculation data come from different positions of the data buffer.

The SIMD computing group is a group of processing unit PEs with the same structure, all PEs have the same structure, and simultaneously execute the same instruction or instruction sequence from the microcontroller in SIMD mode; each PE contains multiple arithmetic and logic Operation processing unit Fn and local register files, logic operation processing unit Fn supports super-long instruction word execution, can process multiple different types of operations in parallel at the same time, each logic operation processing unit Fn has a separate local register file, directly for The processing unit provides operands and stores calculation results.

Compared with the existing technology, due to the large amount of data calculation in computing-intensive applications such as multimedia and scientific computing, and data of the same type or structure often need to perform the same one or a series of operations. Therefore, in the microprocessor facing this type of application, the hardware structure proposed by the present invention has the following advantages by configuring:

(1) The calculation group structure of the fusion of ultra-long instruction word technology and single instruction stream multiple data stream technology proposed by the present invention avoids storage Bandwidth waste, using resource repetition and compilation scheduling strategies to develop data-level parallelism and instruction-level parallelism at the same time, can improve the execution efficiency of applications on processors;

(2) Simultaneously develop DLP and ILP. Since it supports the execution of VLIW programs in the form of SIMD, the collaborative development of instruction-level parallelism and data-level parallelism in the program greatly improves the throughput of the processor for executing such applications;

(3) High hardware efficiency. Multiple PEs share a set of instruction control logic, fetching, decoding, dispatching, and mapping, while the operands come from different data streams. This SIMD execution method uses the control path of one instruction to achieve what can only be achieved by a multi-processor system. Data throughput rate improves hardware efficiency;

(4) The hardware implementation complexity is low. Since compilation can determine the operation delay of various instructions, the work of parallel development is completely completed by the compiler, which avoids complex hardware detection logic and pipeline interlock logic, and reduces the complexity of hardware implementation;

(5) Alleviate the storage bandwidth bottleneck. Due to the use of local registers inside PE, the intermediate results generated by instruction operations do not need to occupy external data buffers, which relieves the bandwidth pressure of external storage and speeds up the speed of operand reading;

In summary, the hardware structure proposed by the present invention combines the advantages of VLIW and SIMD development program parallelism, and is suitable for use in processors for computing-intensive applications, but it is not limited to such processors, and others need to be developed at the same time Processors of various parallelisms may also be employed.

Description of drawings

Fig. 1 is a schematic diagram of a frame structure of the present invention;

Fig. 2 is a schematic diagram of the calculation group structure of VLIW and SIMD fusion among the present invention;

Fig. 3 is a schematic flow chart of instruction processing in the present invention.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

Referring to Fig. 1, the computing group structure of the fusion of ultra-long instruction word and single instruction stream and multiple data streams of the present invention includes a main controller, data buffer, SIMD computing group and microcontroller. Among them, the main controller is responsible for the preparation of instructions and data, transfers the instructions that need to be executed by the SIMD computing group into the storage unit in the microcontroller, controls the start and pause of the SIMD computing group, transfers the required source operation data into the data buffer, and receives The final calculation result in the data buffer; the data buffer component receives the data transmitted from the main controller and stores it in a specific organization, providing the SIMD calculation group with the source operands required for calculation, and receiving the output result of the calculation group after the calculation is completed , the final result is output to the main controller; the microcontroller component receives the super-long instruction word sequence provided by the main controller, and after decoding, dispatches and maps each operation to each processing unit of the SIMD computing group in the form of broadcasting (Processing Element, referred to as PE) corresponding processing unit F executes in parallel; SIMD calculation group is a plurality of parallel processing units organized in the form of SIMD, each processing unit has the same structure, and is equipped with multiple processing units, and the executed instruction sequences are all from the microcontroller, but the required computational data comes from a different location in the data buffer.

Figure 2 is a diagram of the computing group structure of the integration of VLIW and SIMD. A SIMD computing group is a group of processing units PE (PE0, PE1, ..., PEN) with the same structure. All PEs have exactly the same structure and execute the same instruction or sequence of instructions from the microcontroller simultaneously in a SIMD manner. Each PE contains multiple arithmetic and logical operation processing units (F1, F2, ..., Fn) and local register files. The processing units F1, F2, . . . , Fn support the execution of very long instruction words, and can simultaneously process multiple operations of different types in parallel (such as addition, multiplication, multiply-add, logic operations, etc.). Each processing element has a separate local register file, which directly provides operands and saves calculation results to the processing element. The operand is first read from the data buffer into the local register. Since the host controller has already transferred the operand into the data buffer before starting the microcontroller for decoding, dispatching, and mapping execution, the operand is transferred from the data buffer to the PE local register. The delay is fixed. There is a network connection between each local register file inside the processing unit, and the intermediate temporary data generated by calculation can be exchanged. The operand of each processing unit is directly read from its own local register, so the processing unit does not exist when executing instructions. Unexpected stalls due to data not ready. Therefore, the delay required for VLW to execute any operation on all PEs is consistent and knowable, and the compiler can fully develop instruction-level parallelism, generate VLW instruction sequences, and use software pipelining technology to reorganize The loop in the program resolves the data dependencies between very long instruction words without hardware intervention. At the same time, there is also an interconnection network between PEs, which can perform necessary synchronization and data exchange.

Take the following pseudocode program as an example:

//data preparation

load(datal[m], meml);

load(data2[m], mem2);

//data processing

for(i from l to m)

func(datal[i], data2[i], data3[i], data4[i]);

func(data3[i], data4[i], data5[i], data6[i]);

//write data back to external memory or network interface

send(data5[m], mem3);

send(data6[m], chan0);

//Data processing function definition, input in_a and in_b, output out_c and out_d

func(in_a, in_b, out_c, out_d){

//The first super long instruction word instruction I ₁

OP ₁₁ //The execution unit is F1

OP ₁₂ //The execution unit is F2

…

OP _1n ;;//The execution unit is Fn,;; is the super long instruction word boundary mark

//The second super long instruction word instruction I ₂

OP ₂₁

OP ₂₂

…

OP _2n ;;

…

}

This program describes the process of performing a series of operations (two func functions) in sequence on a series of data (data1, data2) with the same structure, and producing a new series of data (data5, data6). The main body is a for loop. Among them, there is a read-after-write data correlation between the second func function of the for loop and the first func function. In the traditional instruction processing technology, the efficiency of program execution, that is, parallelism, is limited by this correlation. A large amount of temporary data (data3, data4) will be generated. If the register resource is insufficient, it must be swapped out to the memory for storage, and then read into the register when necessary, wasting storage bandwidth. Adopting the hardware structure proposed by the present invention can effectively avoid these bottlenecks, and the execution process of this program on the present invention is:

1. Execute the load command, the main controller controls the flow of the data flow, starts the data buffer, transfers the data sequence data1 and data2 required for program execution from the external memory, and stores them in the data buffer according to the fixed index address;

2. The main controller transmits the ultra-long instruction word sequence (the first func function) in the program to the instruction cache part in the microcontroller;

3. The microcontroller decodes the ultra-long instruction word instructions I ₁ , I _{2 ,} etc., decodes n micro-operations (OP _i1 , OP _i2 ,..., OP _in ) in each shot, and distributes them to n of N PEs in parallel. Execute on processing components:

(a) Data loading operation control data (in_a, in_b) is read from the data buffer into the local register of the PE;

(b) Data write-back operation control data (out_c, out_d) is written back to the data buffer from the local register of the PE;

(c) The source operands of the arithmetic and logic operations are taken from their respective local registers, and the execution results are written back to their respective local registers;

(d) Data can move between local registers through the interconnection network within the PE, or across PEs through the interconnection network between PEs;

4. Execute the second func function and repeat steps 2 and 3;

5. Execute the send command, the main controller controls the flow of the data stream, starts the data buffer and writes the data sequence data5 and data6 back to the external memory or the designated network port;

Each micro-operation has a fixed and predictable execution delay. All PEs start to execute and end at the same time. The SIMD method is used between PEs, and the VLIW method is used for parallelism inside PEs.

Fig. 3 is a flowchart of instruction processing in the present invention. After the instruction is decoded by the main controller, it is judged whether it is a data preparation instruction or a data processing instruction. If it is a data preparation command, it is sent to the data buffer for execution, and the data buffer judges whether it is a write command or a read command. The read instruction reads a whole block of data from the external memory according to the data address and fetch length given by the instruction, and stores it in the data buffer according to the fixed index address; the write instruction outputs the specified data block in the data buffer to the specified location (external storage or network port). If it is a data processing instruction, a corresponding super long instruction word instruction sequence is fetched from the external memory into the microcontroller, and the microcontroller decodes, dispatches and executes instructions one by one. The micro-operation translated by each VLW instruction is assigned to N PEs at the same time, and mapped to the corresponding processing unit F. The required data comes from the data buffer, and the PEs are executed in SIMD mode. After processing a super-long instruction word instruction, the microcontroller starts decoding and dispatching the next instruction; after executing a sequence of instructions, the main controller starts reading and processing the next sequence.

Claims (2)

1. A computing group structure in which ultra-long instruction words and single instruction streams and multiple data streams are fused, and is characterized in that: it includes a main controller, a data buffer, a SIMD computing group and a microcontroller, and the data buffer and the microcontroller are respectively connected to the The main controller is connected, and the data buffer and the microcontroller are connected through the SIMD calculation group. The main controller is responsible for the preparation of instructions and data, and transfers the instructions that need to be executed by the SIMD calculation group to the storage unit in the microcontroller to control the SIMD calculation. The start and pause of the group, the required source operation data are transferred to the data buffer, and the final calculation result in the data buffer is received; the data buffer component receives the data transmitted from the main controller, and stores it in a specific organization mode, and calculates for SIMD The group provides the source operands required for calculation. After the calculation, the output result of the calculation group is received, and the final result is output to the main controller; Each operation is dispatched and mapped to the corresponding processing units of each processing unit of the SIMD computing group to execute in parallel; the SIMD computing group is a plurality of parallel processing units with the same structure, and each processing unit is equipped with multiple processing units. The sequence of instructions all come from the microcontroller, but the required computational data comes from different locations in the data buffer. 2. According to claim 1, the computing group structure combining ultra-long instruction word and single instruction stream and multiple data streams is characterized in that: the SIMD computing group is a group of processing units PE with the same structure, and the structures of all PEs are the same. Exactly the same, execute the same instruction or instruction sequence from the microcontroller in SIMD mode; each PE contains multiple arithmetic and logical operation processing units Fn and local register files, and the logical operation processing unit Fn supports super long instruction words Execution, multiple different types of operations can be processed in parallel at the same time, each logical operation processing unit Fn has a separate local register file, directly provides operands for the processing unit and saves the calculation results.

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