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CN115621219A - Electronic package and manufacturing method thereof - Google Patents

Electronic package and manufacturing method thereof Download PDF

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Publication number
CN115621219A
CN115621219A CN202110838654.1A CN202110838654A CN115621219A CN 115621219 A CN115621219 A CN 115621219A CN 202110838654 A CN202110838654 A CN 202110838654A CN 115621219 A CN115621219 A CN 115621219A
Authority
CN
China
Prior art keywords
layer
electronic
electronic component
groove
active surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110838654.1A
Other languages
Chinese (zh)
Inventor
柯仲禹
陈亮斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN115621219A publication Critical patent/CN115621219A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/467—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing gases, e.g. air
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention relates to an electronic packaging piece and a manufacturing method thereof, which comprises embedding a first electronic element in a packaging layer, wherein the first electronic element is provided with an action surface and an non-action surface which are opposite, at least one groove is formed on the non-action surface so as to enable the groove to extend and communicate with the side surface of the packaging layer, the groove is exposed out of the packaging layer and serves as an air channel, and a metal layer is formed on the non-action surface of the first electronic element so as to conduct heat generated by the first electronic element in operation into the air channel through the design of the groove.

Description

Electronic package and manufacturing method thereof
Technical Field
The present invention relates to a semiconductor package process, and more particularly, to an electronic package with a heat dissipation mechanism and a method for fabricating the same.
Background
With the rapid development of portable electronic products in recent years, the development of various related products is also oriented to high density, high performance, light weight, thin weight, short weight and small size, and therefore, various integrated multifunctional packaging styles are developed in the industry to meet the requirements of light weight, small size and high density of electronic products. For example, wireless communication technology is widely applied to various consumer electronic products to receive or transmit various wireless signals, wherein a planar Antenna (Patch Antenna) is widely used in a wireless communication module of an electronic product such as a mobile phone (cell phone), a Personal Digital Assistant (PDA) and the like due to its characteristics of small size, light weight and easy manufacturing.
Fig. 1 is a schematic cross-sectional view of a conventional electronic device 1. The electronic device 1 includes a circuit structure 10 combined with a plurality of solder balls 13, a plurality of semiconductor chips 11,12 disposed on the circuit structure 10 and electrically connected to the circuit structure 10, a package layer 16 covering the semiconductor chips 11,12, and an antenna structure 17 disposed on an outer surface of the package layer 16, such that the antenna structure is combined on the package layer 16 through a dielectric layer 14, and the circuit structure 10 is mounted on a circuit board (not shown) through the solder balls 13.
However, in the conventional electronic device 1, the heat generated by the semiconductor chips 11 and 12 during operation needs to be conducted to the external environment through the packaging layer 16 (or conducted to the external environment through the dielectric layer 14 of the circuit structure 10 and the antenna structure 17), and thus the heat is easily collected and the heat dissipation requirement cannot be achieved.
Therefore, how to overcome the above problems of the prior art has become an urgent problem.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides an electronic package and a method for fabricating the same, so as to satisfy the requirement of heat dissipation.
The electronic package of the present invention comprises: a packaging layer; the first electronic element is embedded in the packaging layer and provided with an active surface and an inactive surface which are opposite to each other, and at least one groove is formed on the inactive surface and is extended to be communicated with the side surface of the packaging layer, so that the groove is exposed out of the packaging layer and serves as an air channel; and a metal layer disposed on the non-active surface of the first electronic component.
The invention also provides a manufacturing method of the electronic packaging piece, which comprises the following steps: the packaging layer is used for coating a first electronic element, so that the first electronic element is embedded in the packaging layer, wherein the first electronic element is provided with an action surface and an inactive surface which are opposite to each other, and at least one groove is formed on the inactive surface, so that the groove extends to be communicated with the side surface of the packaging layer, and is exposed out of the packaging layer and used as an air channel; and forming a metal layer on the non-active surface of the first electronic element.
In the electronic package and the manufacturing method thereof, the metal layer extends along the wall surface of the groove.
In the electronic package and the method for manufacturing the same, a second electronic component is stacked on the active surface of the first electronic component.
In an embodiment, the electronic package further includes a plurality of conductive elements formed in the package layer, such that the plurality of conductive elements are exposed from the package layer. For example, the method further comprises mounting the plurality of conductive elements on a circuit board such that the air channel is located between the circuit board and the non-active surface of the first electronic component.
In the electronic package and the manufacturing method thereof, the heat conducting element is disposed partially or entirely in the groove.
In the electronic package and the method for manufacturing the same, at least one heat dissipation layer covering the recess is formed on the non-active surface.
In view of the above, in the electronic package and the method for fabricating the same of the present invention, the design of forming at least one groove on the non-active surface of the first electronic component is mainly used to directly conduct the heat generated by the first electronic component into the air channel, so that compared with the prior art, the heat generated by the first electronic component during operation can be conducted to the external environment without passing through the package layer, and thus the heat accumulation problem is not generated, and the heat dissipation requirement is satisfied.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional electronic device.
Fig. 2A to 2F are schematic cross-sectional views illustrating a method for manufacturing an electronic package according to the present invention.
Fig. 2E-1 is a cross-sectional view corresponding to fig. 2E.
Fig. 3A and 3B are schematic cross-sectional views of other different embodiments corresponding to fig. 2F.
Description of the reference numerals
1: electronic device
10: circuit structure
11,12 semiconductor chip
13 solder ball
14 dielectric layer
16,26 encapsulation layer
17,27 antenna structure
2,3,4: electronic package
20 bearing structure
20a first side
20b second side
200 line layer
21 first electronic component
21a acting surface
21b non-active surface
210 conductive bump
211 primer
212 electrode pad
22 second electronic component
23 conductive element
25 metal layer
250: groove
26a surface
26c side surface
260 through the hole
35 heat conducting element
45 heat dissipation layer
8: circuit board
S, an air channel.
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.
It should be understood that the structures, ratios, sizes, etc. shown in the drawings are only used for matching the disclosure of the present disclosure to understand and read by those skilled in the art, and are not used to limit the conditions for implementing the present disclosure, so that the present disclosure has no technical essence, and any modifications of the structures, changes of the ratio relationships, or adjustments of the sizes, should still fall within the scope of the present disclosure without affecting the functions and the achievable objects of the present disclosure. In addition, the terms "above", "first", "second" and "a" as used in the present specification are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship may be made without substantial technical changes.
Fig. 2A to 2F are schematic cross-sectional views illustrating a method for manufacturing an electronic package 2 according to the present invention.
As shown in fig. 2A, a package module is provided, which includes a carrier structure 20, a second electronic component 22 embedded in the carrier structure 20, and an antenna structure 27 disposed on the carrier structure 20.
The carrier structure 20 is, for example, a package substrate (substrate) having a core layer and a circuit structure or a circuit structure without a core layer (core), and a plurality of circuit layers 200, such as a fan-out (fan out) redistribution layer (RDL), are formed on an insulating material.
In the present embodiment, the carrier structure 20 has a first side 20a and a second side 20b opposite to each other, the material forming the circuit layer 200 is copper, and the insulating material is a dielectric material such as Polyoxadiazole (PBO), polyimide (PI), prepreg (PP), or solder resist such as green paint or ink.
The second electronic component 22 is an active component, such as a semiconductor chip, a passive component, such as a resistor, a capacitor, or an inductor, or a combination thereof.
In the present embodiment, the second electronic component 22 is a semiconductor chip, which can be electrically connected to the circuit layer 200 through a flip chip method, a wire bonding method, a direct contact with the circuit layer 200, or other suitable methods, without any particular limitation.
The antenna structure 27 is coupled to the second side 20b of the supporting structure 20.
In the present embodiment, the antenna structure 27 is fabricated by sputtering (sputtering), evaporation (vaporizing), electroplating, electroless plating, chemical plating or film (forming), etc. with a thin thickness. For example, the manufacturing process of the antenna structure 27 may be to form a patterned groove on the supporting structure 20, and then form a conductive material in the groove to serve as the antenna structure 27; alternatively, the antenna structure 27 can be formed by directly forming a patterned conductive material (without forming a groove) on the supporting structure 20 to serve as the antenna structure 27.
As shown in fig. 2B, a first electronic component 21 is disposed on the first side 20a of the supporting structure 20, and the first electronic component 21 is electrically connected to the circuit layer 200.
In the present embodiment, the first electronic component 21 is an active component, such as a semiconductor chip, a passive component, such as a resistor, a capacitor, or an inductor, or a combination thereof. For example, the first electronic component 21 has an active surface 21a and an inactive surface 21b opposite to each other, and the first electronic component 21 can be disposed on the circuit layer 200 in a flip-chip manner through a plurality of conductive bumps 210 such as solder material via electrode pads 212 of the active surface 21a and electrically connected to the circuit layer 200, and then the conductive bumps 210 are encapsulated by the underfill 211; alternatively, the electrode pads 212 of the first electronic element 21 can be electrically connected to the circuit layer 200 by wire bonding via a plurality of bonding wires (not shown); alternatively, the electrode pads 212 of the first electronic component 21 can be directly electrically connected to the circuit layer 200. However, the manner of electrically connecting the first electronic component 21 to the carrying structure 20 is not limited to the above.
As shown in fig. 2C, an encapsulation layer 26 is formed on the first side 20a of the carrier structure 20 to encapsulate the first electronic element 21. Next, a plurality of through holes 260 are formed in the encapsulation layer 26, so that a portion of the surface of the circuit layer 200 is exposed to the through holes 260.
In the present embodiment, the package layer 26 is an insulating material, such as Polyimide (PI), dry film (dry film), and molding compound (molding compound) such as epoxy resin (epoxy), but not limited thereto.
In addition, a planarization process may be performed to make the surface 26a of the encapsulation layer 26 flush with the inactive surface 21b of the first electronic component 21, so that the inactive surface 21b of the first electronic component 21 is exposed from the surface 26a of the encapsulation layer 26. For example, the planarization process removes a portion of the material of the first electronic element 21 and a portion of the material of the encapsulation layer 26 by polishing.
As shown in fig. 2D, a conductive element 23 is formed in the through holes 260, so that the conductive element 23 is electrically connected to the circuit layer 200.
In the present embodiment, the conductive element 23 is a spherical conductor such as a solder ball, a columnar conductor such as a copper pillar, a solder bump, or a nail-shaped conductor (stud) made by a wire bonding machine, but is not limited thereto. For example, the conductive elements 23 protrude from the surface 26a of the encapsulation layer 26, so that the conductive elements 23 are exposed from the surface 26a of the encapsulation layer 26.
As shown in fig. 2E, at least one groove 250 is formed on the non-active surface 21b of the first electronic component 21, a metal layer 25 is formed on the non-active surface 21b, and the metal layer 25 extends along the wall surface of the groove 250, so that an air channel S is formed on the non-active surface 21b of the first electronic component 21, thereby forming the electronic package 2 of the present invention.
In the present embodiment, the non-active surface 21b of the first electronic component 21 and a portion of the material of the package layer 26 are removed by etching, as shown in the cross-sectional view of fig. 2E-1, to form a plurality of grooves 250 communicating with two opposite sides 26c of the package layer 26, so that the air channel S can be used for heat dissipation. It should be noted that the metal layer 25 does not fill the recess 250.
In addition, the metal layer 25 is formed on the non-active surface 21b of the electronic component 21 and the wall surface of the groove 250 by plating, sputtering or other coating methods.
In the subsequent process, as shown in fig. 2F, the electronic package 2 is mounted on a circuit board 8 by the conductive elements 23, and the metal layer 25 contacts the circuit board 8.
Therefore, the manufacturing method of the present invention forms at least one groove 250 on the non-active surface 21b of the first electronic component 21 to directly conduct the heat generated by the first electronic component 21 into the air channel S formed by the groove 250, so that when the electronic package 2 is mounted on the circuit board 8, the heat generated during the operation of the first electronic component 21 can be conducted to the external environment through the air channel S without passing through the package layer 26 (in other words, the heat between the first electronic component 21 and the circuit board 8 can be dissipated through the air channel S), thereby avoiding the heat collection problem, satisfying the heat dissipation requirement, and greatly improving the heat dissipation efficiency.
In addition, as shown in fig. 3A, in the electronic package 3 according to another embodiment of the present invention, at least one heat conducting element 35, such as a copper pillar, may be formed partially or entirely in the groove 250, and the heat conducting element 35 is in contact with and bonded to the metal layer 25, but still forming the air channel S, so that when the electronic package 3 is mounted on the circuit board 8, the heat conducting element 35 is in contact with the circuit board 8 to facilitate heat dissipation. Further, as shown in fig. 3B, in the electronic package 4 according to another embodiment of the invention, a heat dissipation layer 45 may be formed on the metal layer 25 on the non-active surface 21B of the first electronic component 21 and the heat conductive element 35, so that the heat dissipation layer 45 covers the groove 250, but the air channel S is still formed, so that when the electronic package 4 is mounted on the circuit board 8, the heat dissipation layer 45 contacts the circuit board 8 to facilitate heat dissipation.
The present invention also provides an electronic package 2,3,4 comprising: an encapsulating layer 26, a first electronic element 21 and a metal layer 25.
The first electronic component 21 is embedded in the package layer 26, wherein the first electronic component 21 has an active surface 21a and an inactive surface 21b opposite to each other, and at least one groove 250 is formed on the inactive surface 21b, so that the groove 250 extends to communicate with the side surface 26c of the package layer 26, and the groove 250 is exposed out of the package layer 26 to serve as an air channel S.
The metal layer 25 is provided on the non-active surface 21b of the first electronic component 21.
In one embodiment, the metal layer 25 extends along the wall of the recess 250.
In one embodiment, the second electronic component 22 is stacked on the active surface 21a of the first electronic component 21.
In one embodiment, the electronic packages 2,3,4 further include a plurality of conductive elements 23 embedded in the package layer 26, and the plurality of conductive elements 23 are exposed from the package layer 26. For example, the conductive elements 23 are disposed on the circuit board 8, such that the air channel S is located between the circuit board 8 and the non-active surface 21b of the first electronic component 21.
In one embodiment, a plurality of heat conducting elements 35 are disposed partially or entirely in the groove 250.
In one embodiment, the non-active surface 21b has at least one heat dissipation layer 45 covering the recess 250.
In summary, the electronic package and the method for fabricating the same according to the present invention directly conduct the heat generated by the first electronic component into the air channel by the design of forming the groove on the inactive surface of the first electronic component, so that the heat generated by the first electronic component during operation can be conducted to the external environment without passing through the package layer, thereby avoiding the problem of heat accumulation and meeting the requirement of heat dissipation.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.

Claims (14)

1. An electronic package, comprising:
a packaging layer;
the first electronic element is embedded in the packaging layer and provided with an active surface and an inactive surface which are opposite to each other, and at least one groove is formed on the inactive surface and is extended to be communicated with the side surface of the packaging layer, so that the groove is exposed out of the packaging layer and serves as an air channel; and
and the metal layer is arranged on the non-action surface of the first electronic element.
2. The electronic package according to claim 1, wherein the metal layer extends along the wall of the recess.
3. The electronic package according to claim 1, wherein a second electronic component is stacked on the active surface of the first electronic component.
4. The electronic package according to claim 1, further comprising a plurality of conductive elements embedded in the encapsulation layer, wherein the plurality of conductive elements are exposed from the encapsulation layer.
5. The electronic package according to claim 4, wherein the plurality of conductive elements are disposed on a circuit board such that the air channel is located between the circuit board and the non-active surface of the first electronic component.
6. The electronic package according to claim 1, wherein part or all of the recess is provided with a heat conducting element.
7. The electronic package according to claim 1, wherein the non-active surface has at least one heat sink layer formed thereon covering the recess.
8. A method of fabricating an electronic package, comprising:
the packaging layer is used for coating a first electronic element, so that the first electronic element is embedded in the packaging layer, wherein the first electronic element is provided with an action surface and an inactive surface which are opposite to each other, and at least one groove is formed on the inactive surface, so that the groove extends to be communicated with the side surface of the packaging layer, and is exposed out of the packaging layer and used as an air channel; and
a metal layer is formed on the non-active surface of the first electronic component.
9. The method of claim 8, wherein the metal layer extends along the wall of the recess.
10. The method of claim 8, wherein a second electronic component is stacked on the active surface of the first electronic component.
11. The method of claim 8, further comprising forming a plurality of conductive elements in the encapsulation layer and exposing the plurality of conductive elements to the encapsulation layer.
12. The method of claim 11, further comprising attaching the plurality of conductive elements to a circuit board such that the air channel is between the circuit board and the non-active surface of the first electronic component.
13. The method of claim 8, wherein the heat conducting element is disposed partially or entirely in the recess.
14. The method as claimed in claim 8, wherein the method further comprises forming at least one heat sink layer on the non-active surface to cover the recess.
CN202110838654.1A 2021-07-13 2021-07-23 Electronic package and manufacturing method thereof Pending CN115621219A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW110125663 2021-07-13
TW110125663A TWI796726B (en) 2021-07-13 2021-07-13 Electronic package and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN115621219A true CN115621219A (en) 2023-01-17

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CN (1) CN115621219A (en)
TW (1) TWI796726B (en)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI257159B (en) * 2004-12-06 2006-06-21 Advanced Semiconductor Eng Chip package structure
TW200707676A (en) * 2005-08-09 2007-02-16 Chipmos Technologies Inc Thin IC package for improving heat dissipation from chip backside
TWI352409B (en) * 2007-04-13 2011-11-11 Chipmos Technologies Inc Qfn package structure with chips having pattern
TWI443785B (en) * 2011-07-27 2014-07-01 矽品精密工業股份有限公司 Semiconductor wafer, chip, semiconductor package having the chip and method of forming same
FR3061600B1 (en) * 2017-01-03 2020-06-26 Stmicroelectronics (Grenoble 2) Sas ELECTRONIC DEVICE COMPRISING A GROOVED CHIP
US11387164B2 (en) * 2019-08-28 2022-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof
CN112992691B (en) * 2021-04-23 2021-09-03 度亘激光技术（苏州）有限公司 Semiconductor device and soldering method thereof

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TWI796726B (en) 2023-03-21

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