CN115549587A - Low-temperature voltage-controlled oscillator circuit with low flicker noise, chip and quantum measurement and control system - Google Patents

Abstract

The embodiment of the invention provides a low-temperature voltage-controlled oscillator circuit with low flicker noise, a chip and a quantum measurement and control system, wherein in the low-temperature voltage-controlled oscillator circuit with low flicker noise, a double-layer inductive coupling structure and a transformer structure are adopted, so that a double-second harmonic resonance point and a third harmonic resonance point can be simultaneously constructed, the harmonic tuning technology is effectively maintained at low temperature, the harmonics can be accurately aligned, and the low-temperature flicker noise is successfully suppressed; meanwhile, the first differential mode capacitance regulating circuit and the second differential mode capacitance regulating circuit are used for respectively realizing fine adjustment and coarse adjustment of the frequency of the oscillator and realizing suppression of broadband low-temperature flicker noise.

Description

Low temperature voltage controlled oscillator circuit, chip and quantum measurement and control system with low flicker noise

technical field

The invention relates to the technical field of microelectronics, in particular to a low-flicker noise low-temperature voltage-controlled oscillator circuit, a chip and a quantum measurement and control system.

Background technique

A voltage controlled oscillator (Voltage Controlled Oscillator, VCO) refers to an oscillating circuit with a corresponding relationship between the output frequency and the input control voltage. The technical requirements for the voltage controlled oscillator mainly include: good frequency stability, high control sensitivity, wide frequency modulation range, frequency The bias has a linear relationship with the control voltage and is easy to integrate. The stability of the output frequency of the voltage-controlled oscillator mainly depends on the phase noise. The smaller the phase noise, the more stable the output frequency of the voltage-controlled oscillator and the higher the accuracy; while the phase noise It is further divided into flicker noise area and thermal noise area, representing the area dominated by flicker noise and the area dominated by thermal noise, respectively.

B.Patra et al pointed out in the article "Cryo-CMOS Circuits and Systems for Quantum Computing Applications" published in IEEE Journal of Solid-State Circuits, vol.53, no.1, pp.309–321, Jan. 2018: Extremely low temperature Under environmental conditions, the flicker noise of the CMOS process will deteriorate drastically, causing the low-temperature flicker noise corner (Flicker Noise Corner) of the VCO to deteriorate by more than 40 times compared with normal temperature. It will also be many times worse than normal temperature.

However, harmonic tuning technology is often used in VCO to suppress flicker noise. The schematic diagram of LC-VCO shown in Figure 1(a) is used to further illustrate the traditional harmonic tuning technology of VCO, which specifically refers to: two NMOS active transistors A negative resistance oscillator is formed in the form of a cross-coupled pair, and the coil inductance and capacitance above the cross-coupled pair form two or more LC resonant cavities, which are used to select the output frequency of the VCO circuit. As shown in Figure 1(b), the differential mode capacitor C _D and the common mode capacitor C _C and L form a resonant circuit, resonating at the fundamental frequency F0, and the common mode capacitor C _C and L form another common mode resonant circuit, Resonates at frequency F _CM . By adjusting the ratio of the common-mode capacitance C _C to the differential-mode capacitance C _D , when _{C C} /CD = 1/3, F _CM = 2F0, and the common-mode resonance frequency is just at the second harmonic of the fundamental frequency. The minimum phase noise (Phase Noise, PN) can be obtained when , as shown in Figure 1(c).

However, the parameters of passive devices (capacitors, inductors) will change in low temperature environment, so that the oscillation frequency of the LC resonator has a large difference between room temperature and low temperature; at low temperature, the oscillation frequency shifts to high frequency, resulting in additional resonance The cavity cannot resonate exactly at the harmonic frequency of the fundamental frequency, and the optimal phase noise cannot be obtained, that is, the harmonic tuning technology will fail at low temperature, the harmonic alignment will be misaligned, and the low temperature flicker noise cannot be successfully suppressed.

Therefore, it is urgent to design a voltage-controlled oscillator solution for low-temperature application scenarios with excellent phase noise performance.

Contents of the invention

The first aspect of the present invention provides a low-temperature voltage-controlled oscillator circuit with low flicker noise, which uses a double-layer inductive coupling structure and a transformer structure to realize the construction of a double-second harmonic resonance point, and can use harmonic tuning technology at low temperature Staying active allows the harmonics to be accurately aligned, resulting in successful suppression of cryogenic flicker noise.

In the first aspect of the present invention, a low-flicker noise low-temperature voltage-controlled oscillator circuit is provided, which includes: a double-layer inductive coupling structure, a transformer structure, a first oscillation frequency adjustment circuit, a second oscillation frequency adjustment circuit, a first MOS tube and a second MOS tube;

Wherein, one end of the upper layer inductor of the double-layer inductive coupling structure is coupled to the working voltage input end, one end of the lower layer inductor is coupled to the working voltage input end through the first capacitor, and the other end of the upper layer inductor and the lower layer inductor are jointly coupled to the transformer the center tap of the structure;

One end of the primary winding of the transformer structure is coupled to the gate of the first MOS transistor, the other end is coupled to the gate of the second MOS transistor, and one end of the secondary winding is coupled to the gate of the first MOS transistor a drain, the other end of which is coupled to the drain of the second MOS transistor; and, the center of the primary winding of the transformer structure is coupled to the second voltage input end;

The sources of the first MOS transistor and the second MOS transistor are respectively coupled to the ground terminal, the drain of the first MOS transistor is coupled to one end of the second capacitor, and the drain of the second MOS transistor is coupled to the other end of the second capacitor;

The first differential-mode capacitance adjustment circuit is connected in parallel with the second differential-mode capacitance adjustment circuit, and is arranged between the two ends of the primary winding of the transformer structure to adjust the primary winding connected to the transformer structure respectively. The differential mode capacitance of the winding, and then adjust the oscillation frequency of the voltage controlled oscillator circuit.

In some possible embodiments, the double-layer inductive coupling structure is composed of two stacked metal wires, the upper metal wire constitutes the upper layer inductor, the lower layer metal wire constitutes the lower layer inductor, and the The two stacked metal traces are configured as two symmetrical ring structures in the same plane.

In some possible embodiments, the low-flicker noise low-temperature voltage-controlled oscillator circuit of the present invention further includes a decoupling capacitor; wherein, the operating voltage input terminal is coupled to the positive plate of the decoupling capacitor, and the double-layer One end of the upper inductor of the inductive coupling structure is coupled to the positive plate of the decoupling capacitor, one end of the lower inductor is coupled to the positive plate of the decoupling capacitor through the first capacitor, and the negative plate of the decoupling capacitor is coupled to the ground end.

In some possible embodiments, the first differential mode capacitance adjustment circuit includes: a first fixed capacitance, a first variable capacitance, and a second variable capacitance; and the first variable capacitance and the second variable capacitance The variable capacitance is connected in parallel with the first fixed capacitance after being connected in series, and is arranged between the two ends of the primary winding of the transformer structure; wherein, the first variable capacitance is coupled to the connection node of the second variable capacitance To Capacitor Adjusted Voltage Input.

In some possible embodiments, the second differential mode capacitance adjustment circuit includes: a plurality of switched capacitor units; wherein, each of the switched capacitor units includes: a pair of fixed capacitors and a MOS transistor; and, the MOS The source of the tube is coupled to one end of the primary winding of the transformer structure through a fixed capacitance, and the drain of the MOS tube is coupled to the other end of the primary winding of the transformer structure through another fixed capacitance. The gate is coupled to the corresponding switch signal input end of the switched capacitor unit.

In some possible embodiments, the switched capacitor unit further includes: a first inverter, a second inverter, and a pair of resistors; wherein, the input terminal of the first inverter is coupled to the switched capacitor unit The corresponding switch signal input terminal, its output terminal is coupled to the input terminal of the second inverter, and the output terminal of the second inverter is coupled to the gate of the MOS transistor; one end of a resistor is coupled to the The other end of the source of the MOS transistor is coupled to the output end of the first inverter, one end of the other resistor is coupled to the drain of the MOS transistor, and the other end is coupled to the output end of the first inverter.

In some possible embodiments, the ratio of the variation range of the capacitance value of the second differential mode capacitance adjustment circuit to the capacitance value of the first capacitor is between 10:1 and 20:1.

In some possible embodiments, the low-flicker noise low-temperature voltage-controlled oscillator circuit of the present invention further includes: a plurality of switch resistor units; wherein, each switch resistor unit includes: a ground resistor and a MOS transistor, and , the sources of the first MOS transistor and the second MOS transistor are coupled to one end of the grounding resistor, the other end of the grounding resistor is coupled to the drain of the MOS transistor, and the source of the MOS transistor is coupled to the ground terminal, and the gate of the MOS transistor is coupled to the switch signal input terminal corresponding to the switch resistor unit.

In some possible embodiments, the low-flicker noise low-temperature voltage-controlled oscillator circuit of the present invention further includes: a first buffer and a second buffer; wherein, the input end of the first buffer is coupled to the transformer One end of the primary winding of the structure, the other end of which is coupled to the first frequency output, the input of the second buffer is coupled to the other end of the primary winding of the transformer structure, the other end of which is coupled to the second frequency output .

A second aspect of the present invention provides a chip comprising:

A silicon substrate; and, the low-flicker noise low-temperature voltage-controlled oscillator circuit of the first aspect of the present invention formed on the silicon substrate, wherein the low-flicker noise low-temperature voltage-controlled oscillator circuit is manufactured using a CMOS process .

The third aspect of the present invention provides a quantum measurement and control system, which includes the chip described in the second aspect of the present invention.

In this way, in the low-flicker noise low-temperature voltage-controlled oscillator circuit provided by the present invention, by adopting a double-layer inductive coupling structure and a transformer structure in the circuit, a double second harmonic resonance point and a third harmonic resonance point can be constructed at the same time. The harmonic tuning technology remains effective at low temperature, so that the harmonics can be accurately aligned, thereby successfully suppressing low-temperature flicker noise; at the same time, the first differential-mode capacitance adjustment circuit and the second differential-mode capacitance adjustment circuit are used to achieve fine adjustment and coarse adjustment of the oscillator frequency. tuned to achieve broadband low-temperature flicker noise suppression.

Description of drawings:

Figure 1 is a schematic diagram of the LC-VCO;

FIG. 2 is a structural diagram of a low-flicker noise low-temperature voltage-controlled oscillator circuit provided in an embodiment of the present invention;

FIG. 3 is a structural diagram of a low-flicker noise low-temperature voltage-controlled oscillator circuit provided in an embodiment of the present invention;

4 is a schematic diagram of the connection between a decoupling capacitor and a double-layer inductive coupling structure in an embodiment of the present invention;

5 is a schematic diagram of a double-layer inductive coupling structure in an embodiment of the present invention;

Fig. 6 is a schematic diagram of the magnetic field distribution when the double-layer inductive coupling structure works in the embodiment of the present invention;

FIG. 7 is a schematic diagram of harmonic impedance simulation of the low-flicker noise low-temperature voltage-controlled oscillator circuit shown in FIG. 3;

FIG. 8 is a simulation schematic diagram of the flicker noise angle in the full frequency band of the low-flicker noise low-temperature voltage-controlled oscillator circuit shown in FIG. 3;

9 is a schematic diagram of simulation of phase noise in the flicker noise dominant region of the low-flicker noise low-temperature voltage-controlled oscillator circuit shown in FIG. 3;

Fig. 10 is a schematic diagram of the composition of the reading system in the quantum measurement and control reading provided in the embodiment of the present invention.

detailed description

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. However, it should not be understood that the scope of the above subject matter of the present invention is limited to the following embodiments, and all technologies realized based on the content of the present invention belong to the scope of the present invention.

In one embodiment of the present invention, a low-flicker noise low-temperature voltage-controlled oscillator circuit 10 is provided, as shown in FIG. 2 , which includes: a double-layer inductive coupling structure 101, a transformer structure 102, and a first oscillation frequency adjustment circuit 103. The second oscillation frequency adjustment circuit 104, the first MOS transistor M1 and the second MOS transistor M2;

Wherein, one end of the upper layer inductor of the double-layer inductive coupling structure 101 is coupled to the working voltage input terminal VDD, one end of the lower layer inductor is coupled to the working voltage input terminal VDD through the first capacitor Chead, and the other end of the upper layer inductor and the lower layer inductor are jointly coupled to the center tap of said transformer structure 102;

One end of the primary winding of the transformer structure is coupled to the gate of the first MOS transistor M1, the other end is coupled to the gate of the second MOS transistor M2, and one end of the secondary winding is coupled to the first MOS transistor M1. The drain of the tube M1, the other end of which is coupled to the drain of the second MOS tube M2; moreover, the center of the primary winding of the transformer structure 102 is coupled to the second voltage input terminal V _GB ;

The sources of the first MOS transistor M1 and the second MOS transistor M2 are respectively coupled to the ground terminal, the drain of the first MOS transistor M1 is coupled to one end of the second capacitor Cdd, and the second MOS transistor M2 The drain is coupled to the other end of the second capacitor Cdd;

The first differential-mode capacitance adjustment circuit 103 is connected in parallel with the second differential-mode capacitance adjustment circuit 104, and is arranged between the two ends of the primary winding of the transformer structure 102, so as to respectively adjust and connect to the transformer. The differential mode capacitance of the primary winding of the structure 102, thereby adjusting the oscillation frequency of the voltage controlled oscillator circuit.

In this embodiment, the first differential-mode capacitance adjustment circuit 103 includes: a first fixed capacitor Cgg and two variable capacitors Cv; and the two variable capacitors Cv are connected in series and connected in parallel with the first fixed capacitor Cgg, And it is arranged between the two ends of the primary winding of the transformer structure 102; wherein, the connection node of the two variable capacitors Cv is coupled to the input terminal of the capacitor regulating voltage.

In this embodiment, the second differential mode capacitance adjustment circuit 104 includes: a plurality of switched capacitor units; wherein, each of the switched capacitor units includes: a pair of fixed capacitors CB and a MOS transistor; and, the MOS The source of the tube is coupled to one end of the primary winding of the transformer structure 102 through a fixed capacitance CB, and the drain of the MOS transistor is coupled to the other end of the primary winding of the transformer structure 102 through another fixed capacitance CB, so The gate of the MOS transistor is coupled to the switch signal input terminal SW corresponding to the switch capacitor unit.

Specifically, the switched capacitor unit further includes: a first inverter, a second inverter, and a pair of resistors; wherein, the input terminal of the first inverter is coupled to the corresponding switch signal input of the switched capacitor unit end, the output end of which is coupled to the input end of the second inverter, and the output end of the second inverter is coupled to the gate of the MOS transistor; one end of a resistor is coupled to the source of the MOS transistor , the other end of which is coupled to the output end of the first inverter, one end of the other resistor is coupled to the drain of the MOS transistor, and the other end is coupled to the output end of the first inverter. Through the above method, it is possible to ensure that the MOS switch is turned on and off normally.

Moreover, in order to widen the operating bandwidth of the VCO, the ratio of the capacitance value variation range of the second differential mode capacitance adjustment circuit 104 to the capacitance value of the first capacitance is between 10:1 and 20:1; The specific gravity increases the overall capacitance variation range of the second differential mode capacitance adjustment circuit 104, so that the working bandwidth of the VCO can be improved.

In this way, in the low-temperature voltage-controlled oscillator circuit with low flicker noise provided by the present invention, by adopting a double-layer inductive coupling structure and a transformer structure, a double second harmonic resonance point and a third harmonic resonance point can be constructed at the same time. The wave tuning technology remains effective, so that the harmonics can be accurately aligned, thereby successfully suppressing the low-temperature flicker noise; at the same time, the first differential-mode capacitance adjustment circuit and the second differential-mode capacitance adjustment circuit are used to realize fine adjustment and coarse adjustment of the oscillator frequency respectively, realizing Suppression of broadband cryogenic flicker noise.

In this embodiment, since the core circuit of the voltage-controlled oscillator is directly connected to the subsequent stage circuit (frequency divider), in order to isolate the impact of the latter stage circuit on the core circuit of the voltage-controlled oscillator, the first MOS transistor M1, the second A first buffer and a second buffer are provided at the gate output of the two MOS transistors M2; specifically, the input end of the first buffer is coupled to one end of the primary winding of the transformer structure, and the other end is coupled to the first A frequency output terminal V _GN , the input terminal of the second buffer is coupled to the other end of the primary winding of the transformer structure, and the other end is coupled to the second frequency output terminal V _GP .

In an embodiment provided by the present invention, a resistor array 105 is added on the basis of the embodiment shown in FIG. 2 . As shown in FIG. 3 , the resistor array 105 includes: a plurality of switch resistor units; wherein each switch The resistance unit includes: a grounding resistor and a MOS transistor, and the sources of the first MOS transistor and the second MOS transistor are commonly coupled to one end of the grounding resistor, and the other end of the grounding resistor is coupled to the MOS transistor. The drain of the transistor, the source of the MOS transistor are coupled to the ground terminal, and the gate of the MOS transistor is coupled to the switch signal input terminal SW corresponding to the switch resistance unit. Through the above method, the overall resistance value of the resistor array can be changed in a digitally controlled manner to control the overall current of the oscillator, and the power consumption can be adjusted at low temperature to obtain a better FOM.

In an embodiment provided by the present invention, as shown in FIG. 4 , the low-flicker noise low-temperature voltage-controlled oscillator circuit of the present invention further includes a decoupling capacitor 106; wherein, the operating voltage input terminal VDD is coupled to the decoupling capacitor 106 positive plate, one end of the upper inductance of the double-layer inductive coupling structure is coupled to the positive plate of the decoupling capacitor 106, and one end of the lower inductance is coupled to the positive plate of the decoupling capacitor 106 through the first capacitance, The negative plate of the decoupling capacitor 106 is coupled to the ground.

An embodiment provided by the present invention, as shown in FIG. 5, in this embodiment, the double-layer inductive coupling structure 101 is composed of two stacked metal traces, and the upper layer metal trace 101a constitutes the upper layer inductance The lower layer metal wires 101b form the lower layer inductor, and the two stacked metal wires are configured as two symmetrical ring structures in the same plane. When the low-flicker noise low-temperature voltage-controlled oscillator circuit is working, the magnetic field distribution of the double-layer inductive coupling structure 101 is shown in Figure 6, which balances the overall internal magnetic field and avoids being affected by the magnetic force, so that the first MOS transistor M1 and the second MOS transistor M1 The common-mode voltage amplitudes at the drains of the tube M2 are equal.

In the embodiment shown in Figure 2 or Figure 3 provided by the present invention, the specific structure of the transformer structure 102 is the same as A.Beckers et al. in 2017 47th European Solid-State Device Research Conference (ESSDERC), 2017, pp.62- The structure adopted to realize the VCO harmonic tuning technology by designing a transformer disclosed in "Cryogenic characterization of 28nm bulk CMOS technology for quantum computing" published in 1965 is the same, and will not be repeated here.

3 and 4, the primary winding Lp of the transformer structure 102 is connected to the gates of the first MOS transistor M1 and the second MOS transistor M2, and the secondary winding Ls is connected to the first MOS transistor M1 and the second MOS transistor. The drain of M2; when the secondary winding Ls is excited by the differential mode, the induced current in the primary winding Lp is strengthened in the same direction, and has a strong coupling coefficient; and when the secondary winding Ls is excited by the common mode, the induced current in the primary winding Lp is reversed to cancel, with a weak coupling coefficient. Therefore, the primary winding Lp does not participate in the common mode resonance.

During operation, the secondary winding Ls, the primary winding Lp, the differential mode capacitor CV, the capacitor array CB, and Cgg jointly generate a differential mode resonance of the fundamental frequency (f0) at the gates of the first MOS transistor M1 and the second MOS transistor M2; The resonant cavity formed by the double-layer inductive coupling structure 101, the secondary winding Ls and the first capacitor Chead have a common-mode resonance, and output at the drains of the first MOS transistor M1 and the second MOS transistor M2; at the same time, due to the double-layer inductance The resonant cavity formed by the coupling structure 101 has the upper and lower layers of inductance coupled to each other, which can realize common-mode resonance at two frequencies at the same time. The coupling coefficient of this structure is higher. Therefore, the two resonant frequencies are close enough at high frequencies. Near the subharmonic (2f0) forms a broadband common-mode (CM) resonance with double resonant peaks; at the same time, the secondary winding Ls, primary winding Lp, and differential-mode capacitance Cdd are at the drains of the first MOS transistor M1 and the second MOS transistor M2 Differential-mode resonance at the third harmonic (3f0) is realized at .

Finally, the harmonic impedance simulation diagram shown in Figure 7 is obtained, that is, a differential mode (DM) resonance is formed near the fundamental frequency (f0), and a broadband common mode (CM) with double resonance peaks is formed near the second harmonic (2f0). Resonance, forming a differential mode (DM) resonance near the third harmonic (3f0).

Further, as shown in Figure 8, by testing the flicker noise angle in the full frequency band, the red broken line is the test result at 293K normal temperature, and the blue broken line is the test result at 4K low temperature. Among them, 293K flicker noise angle: 150~600kHz; 4K flicker noise angle: 450~800kHz. The 4K low temperature is only 1.3 to 3 times worse than the 293K normal temperature, and in the whole frequency band, the flicker noise angle is suppressed and kept within 800kHz.

As shown in Figure 9, by testing the phase noise at a frequency offset of 100kHz (flicker noise dominant area), according to the simulation results, it can be known that in the flicker noise dominated area, if not suppressed, the flicker noise will deteriorate by 10 times at 4K low temperature, However, the broadband dual resonance peaks of this design are still effective at low temperatures, and flicker noise is suppressed in the entire frequency band.

An embodiment of the invention also provides a chip, which includes: a silicon substrate; An oscillator circuit, wherein the low-flicker-noise low-temperature voltage-controlled oscillator circuit is manufactured using a CMOS process.

An embodiment of the present invention also provides a quantum measurement and control system, which includes the chip provided in the embodiment of the present invention. Specifically, quantum computing is divided into two parts: the quantum chip (Qubit Chip) and the quantum measurement and control system (Controller). Among them, the Qubit Chip needs to work in the extremely low temperature region of 10mK (0.01 Kelvin above absolute zero) in a low-temperature refrigerator; the Controller It is used to read and control the quantum chip; moreover, the quantum measurement and control system includes two parts, the reading system and the control system, as shown in Figure 10, the reading system (Readout Chip) is composed of a frequency integration system - a phase-locked loop (Phase Locked Loop, PLL) and IQ receiver. The PLL generates a radio frequency signal, which is attenuated by an attenuator (Attenuator), and enters the qubit through a circulator. The gate reflected signal of qubit Q1 enters the first stage of the IQ receiver through the circulator——Low Noise Amplifier (LNA) after amplification, down-converted to quadrature component (I/Q), and then filtered ( Low PassFilter, LPF) and post-amplified readout.

Wherein, the function of the PLL in the reading system is to generate a stable radio frequency signal. The working process of the PLL is as follows: First, the voltage-controlled oscillator (Voltage Controlled Oscillator, VCO), the oscillator is the control object of the phase-locked loop, which freely oscillates at a certain frequency through the LC resonator to generate a radio frequency signal, and the output of the LPF The voltage signal controls the size of the internal capacitance of the VCO, so the VCO can output radio frequency signals in a certain frequency range; the VCO has two outputs, one of which provides frequency signals for the large system, and the other participates in the feedback of the PLL loop, as shown in the figure. After the VCO output is divided by the frequency division chain-two-stage ÷2 frequency division and a program-controlled frequency divider, the high-frequency signal components are frequency-divided into lower-frequency signals, and then fed back to the phase detector (Phase Detector, PD); the phase detector has two inputs, one input is the feedback signal of the output of the VCO in the PLL loop through the frequency division chain, and the other input is the reference clock (Reference) provided by the external environment. The reference clock is usually low in frequency. Therefore, a frequency division chain is required to divide the high frequency signal of the oscillator to a lower frequency by a specified frequency division multiple, so as to compare it with the reference clock. The function of the phase detector is to extract the phase difference between the feedback signal and the reference clock, and Convert the error signal into a form that can be processed by subsequent modules, including voltage signals, current signals, or digital signals; charge pumps (CP) and phase detectors are usually used in combination, and their main function is to convert phase differences into charges, and The charge is transmitted to the filter (LPF) in the loop for filtering, and a control voltage is generated to control the frequency and phase of the oscillator (VCO). This forms a very versatile PLL loop system.

At present, the quantum measurement and control system is being integrated from normal temperature (290K) to low temperature (4K) environment, avoiding the need for a large number of signal cables and crossing the temperature zone to connect the quantum measurement and control system to the quantum chip, so as to solve the problem of introducing a large amount of noise and bringing the complexity of interconnection problems such as reliability, high cost and unreliability. Therefore, applying the chip provided in the embodiment of the present invention as a voltage-controlled oscillator in the readout system (Readout Chip) can successfully suppress low-temperature flicker noise, and is especially suitable for the application scenario of integrating a quantum measurement and control system into a low-temperature (4K) environment .

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range.

Claims (11)

1. A low-temperature voltage-controlled oscillator circuit with low flicker noise, characterized in that it includes: a double-layer inductive coupling structure, a transformer structure, a first oscillation frequency adjustment circuit, a second oscillation frequency adjustment circuit, a first MOS tube, and a second oscillation frequency adjustment circuit. Two MOS tubes; Wherein, one end of the upper layer inductor of the double-layer inductive coupling structure is coupled to the working voltage input end, one end of the lower layer inductor is coupled to the working voltage input end through the first capacitor, and the other end of the upper layer inductor and the lower layer inductor are jointly coupled to the transformer the center tap of the structure; One end of the primary winding of the transformer structure is coupled to the gate of the first MOS transistor, the other end is coupled to the gate of the second MOS transistor, and one end of the secondary winding is coupled to the gate of the first MOS transistor a drain, the other end of which is coupled to the drain of the second MOS transistor; and, the center of the primary winding of the transformer structure is coupled to the second voltage input end; The sources of the first MOS transistor and the second MOS transistor are respectively coupled to the ground terminal, the drain of the first MOS transistor is coupled to one end of the second capacitor, and the drain of the second MOS transistor is coupled to the other end of the second capacitor; The first differential-mode capacitance adjustment circuit is connected in parallel with the second differential-mode capacitance adjustment circuit, and is arranged between the two ends of the primary winding of the transformer structure to adjust the primary winding connected to the transformer structure respectively. The differential mode capacitance of the winding, and then adjust the oscillation frequency of the voltage controlled oscillator circuit. 2. The low-flicker noise low-temperature voltage-controlled oscillator circuit according to claim 1, wherein the double-layer inductive coupling structure is composed of two stacked metal traces, and the upper-layer metal traces constitute the upper layer In the inductor, the lower layer metal traces constitute the lower layer inductor, and the two stacked metal traces are configured as two symmetrical ring structures in the same plane. 3. The low-flicker noise low-temperature voltage-controlled oscillator circuit according to claim 2, further comprising a decoupling capacitor; wherein the operating voltage input terminal is coupled to the positive plate of the decoupling capacitor, and the One end of the upper inductance of the double-layer inductive coupling structure is coupled to the positive plate of the decoupling capacitor, one end of the lower inductance is coupled to the positive plate of the decoupling capacitor through the first capacitor, and the negative plate of the decoupling capacitor is coupled to to ground. 4. The low-temperature voltage-controlled oscillator circuit with low flicker noise according to claim 1, wherein the first differential mode capacitance adjustment circuit comprises: a first fixed capacitance, a first variable capacitance and a second variable capacitance ; and the first variable capacitor is connected in series with the second variable capacitor and then connected in parallel with the first fixed capacitor, and is arranged between the two ends of the primary winding of the transformer structure; wherein, the first A connection node between the variable capacitor and the second variable capacitor is coupled to the capacitor adjustment voltage input terminal. 5. The low-temperature voltage-controlled oscillator circuit with low flicker noise as claimed in claim 1, wherein the second differential mode capacitance adjustment circuit comprises: a plurality of switched capacitor units; wherein each of the switched capacitor units comprises : a pair of fixed capacitors and a MOS tube; and, the source of the MOS tube is coupled to one end of the primary winding of the transformer structure through a fixed capacitor, and the drain of the MOS tube is coupled to the end of the primary winding through another fixed capacitor The other end of the primary winding of the transformer structure, the gate of the MOS transistor is coupled to the switch signal input end corresponding to the switched capacitor unit. 6. The low-flicker noise low-temperature voltage-controlled oscillator circuit according to claim 5, wherein the switched capacitor unit further comprises: a first inverter, a second inverter, and a pair of resistors; wherein, the The input end of the first inverter is coupled to the switch signal input end corresponding to the switched capacitor unit, the output end is coupled to the input end of the second inverter, and the output end of the second inverter is coupled to The gate of the MOS transistor; one end of a resistor is coupled to the source of the MOS transistor, the other end is coupled to the output of the first inverter, and one end of the other resistor is coupled to the drain of the MOS transistor, The other end is coupled to the output end of the first inverter. 7. The low-temperature voltage-controlled oscillator circuit with low flicker noise as claimed in claim 6, wherein the ratio of the capacitance value variation range of the second differential mode capacitance adjustment circuit to the capacitance value of the first capacitor is 10 : between 1 and 20:1. 8. The low-flicker-noise low-temperature voltage-controlled oscillator circuit according to any one of claims 1 to 7, further comprising: a plurality of switched resistance units; wherein each of said switched resistance units comprises: a grounding resistor and a MOS tube, and the sources of the first MOS tube and the second MOS tube are commonly coupled to one end of the grounding resistor, and the other end of the grounding resistor is coupled to the drain of the MOS tube, and the MOS tube The source of the transistor is coupled to the ground terminal, and the gate of the MOS transistor is coupled to the switch signal input terminal corresponding to the switch resistance unit. 9. The low-flicker noise low-temperature voltage-controlled oscillator circuit according to claim 8, further comprising: a first buffer and a second buffer; wherein the input end of the first buffer is coupled to the One end of the primary winding of the transformer structure, the other end of which is coupled to the first frequency output, the input of the second buffer is coupled to the other end of the primary winding of the transformer structure, and the other end of which is coupled to the second frequency output. 10. A chip, characterized in that it comprises: a silicon substrate; and, the low-flicker noise low-temperature voltage-controlled oscillator circuit according to any one of claims 1 to 9 formed on the silicon substrate, wherein the low-flicker noise low-temperature voltage-controlled oscillator circuit The circuit is made by CMOS technology. 11. A quantum measurement and control system, comprising: the chip according to claim 10.

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