CN115547995A - A three-dimensional silicon-based capacitor and its preparation method and integrated passive device - Google Patents

Abstract

The invention discloses a three-dimensional silicon-based capacitor, which comprises a groove structure etched on a silicon substrate, wherein conducting layers and dielectric layers are alternately deposited on the groove structure, different conducting layers are completely isolated by the dielectric layers, the groove structure comprises a silicon column array and a groove between the silicon column arrays, an isolating layer is filled in the groove, a first electrode layer is deposited on a top conducting layer and the isolating layer, and an outermost conducting layer deposited on the groove structure is in ohmic contact with the first electrode layer; and a redistribution layer is etched on the back of the silicon substrate, a second electrode layer is deposited, and the innermost conductive layer deposited on the groove structure forms ohmic contact with the second electrode layer through the redistribution layer. The scheme can ensure that the capacitor outputs higher capacitance value or bears higher voltage while reducing the volume of the capacitor.

Description

A three-dimensional silicon-based capacitor and its preparation method and integrated passive device

technical field

The invention relates to the technical field of integrated circuit manufacturing, in particular to a three-dimensional silicon-based capacitor, a preparation method thereof, and an integrated passive device.

Background technique

With the increasing integration of electronic products, traditional capacitors mostly use discrete devices, and their low capacitance values cannot meet high-voltage and high-power applications. At present, the research on integrated circuits is mainly focused on the integration of active devices, while the integration of passive devices is relatively lagging behind. Capacitors are an important passive device, and their integrated design is conducive to further reducing the volume of integrated circuits. .

As a new type of electronic component, silicon capacitors are made of silicon materials using semiconductor manufacturing processes. Due to the good stability of silicon materials, silicon capacitors also have good high-frequency characteristics and temperature characteristics, extremely low bias characteristics and high reliability. And most of the semiconductor industry uses silicon-based integrated circuits. Therefore, the integration of capacitors based on silicon capacitors can better meet the packaging requirements for capacitors in integrated circuits. Most of the existing silicon capacitors are only suitable for low voltage conditions, and the breakdown voltage is low.

Therefore, it is necessary to provide a three-dimensional silicon-based capacitor, which can increase the breakdown voltage of the capacitor, and can ensure a higher capacitance value while reducing the capacitance size, and is suitable for high-voltage and high-power usage scenarios, so as to solve the above existing technologies. problems in .

Contents of the invention

In view of the above problems, the present invention is proposed in order to provide a three-dimensional silicon-based capacitor, a manufacturing method thereof, and an integrated passive device that overcome the above problems or at least partially solve the above problems.

According to one aspect of the present invention, a three-dimensional silicon-based capacitor is provided, including a groove structure etched on a silicon substrate, conductive layers and dielectric layers are alternately deposited on the groove structure, and different conductive layers are passed through The dielectric layer is completely isolated, the trench structure includes the silicon pillar array and the trench between the silicon pillar array, the trench is filled with an isolation layer, and the first electrode layer is deposited on the top conductive layer and the isolation layer, so that the trench structure The deposited outermost conductive layer forms an ohmic contact with the first electrode layer; a redistribution layer is etched on the back of the silicon substrate and a second electrode layer is deposited, so that the innermost conductive layer deposited on the trench structure passes through the redistribution layer Ohmic contact is formed with the second electrode layer.

By etching a trench structure with a deep trench ratio on the silicon substrate, and alternately depositing a conductive layer-dielectric layer-conductive layer structure on the trench structure, the effective area of the capacitor plate can be increased and the capacitance value per unit area can be increased; By depositing a dielectric layer with a high dielectric constant between the conductive layers, the breakdown voltage of the capacitor can be increased, and the capacitance value of the capacitor can be increased without increasing the volume of the capacitor.

Optionally, in the above three-dimensional silicon-based capacitor, the trench structure has an aspect ratio of (2-50):1.

Optionally, in the above-mentioned three-dimensional silicon-based capacitor, the material of the conductive layer is any one of Cu, Al, Ta, graphite, CdS, CdSe, and composite materials.

Optionally, in the above-mentioned three-dimensional silicon-based capacitor, the dielectric constant of the dielectric layer is higher than a predetermined value, and the material of the dielectric layer and the isolation layer is one of SiO2, BaO, HfO2, ZrO2, Al2O3, BaZrO3, BaTiO3 or Several kinds.

According to another aspect of the present invention, a method for preparing a three-dimensional silicon-based capacitor is provided, including: etching a groove structure on the surface of a silicon substrate, the groove structure including a silicon pillar array and grooves between the silicon pillar arrays; Deposit a conductive layer on the surface of the trench structure, deposit a dielectric layer on the surface of the conductive layer, so that the dielectric layer completely covers the surface of the conductive layer, deposit a conductive layer on the surface of the dielectric layer, so that the conductive layer completely covers the surface of the dielectric layer, forming At least one conductive layer-dielectric layer-conductive layer structure; deposit the first electrode layer on the top conductive layer and the isolation layer, etch the redistribution layer and deposit the second electrode layer on the bottom of the silicon substrate, so that the deposition on the trench structure The outermost conductive layer and the first electrode layer form an ohmic contact, and the innermost conductive layer deposited on the trench structure forms an ohmic contact with the second electrode layer, thereby obtaining a three-dimensional silicon-based capacitor with a preset capacitance value.

Optionally, in the above method, the conductive layer and the dielectric layer are deposited by any one of physical vapor deposition, atomic layer deposition, high-density plasma enhanced chemical vapor deposition, and plasma enhanced chemical vapor deposition.

According to another aspect of the present invention, there is provided an integrated passive device comprising a three-dimensional silicon-based capacitor as described above and a resistor and/or a semiconductor device disposed on the backside of the silicon substrate of the three-dimensional silicon-based capacitor, the resistor or Semiconductor devices are produced by doping different concentrations of ions on the back of the silicon substrate.

According to the solution of the present invention, a three-dimensional capacitor microstructure with at least one conductive layer-dielectric layer-conductive layer structure is formed on the silicon substrate through a mature semiconductor etching process, which can greatly increase the effective area of the capacitor electrode, thereby improving Capacitance per unit area is improved, while reducing the size of the capacitor, it can ensure a high capacitance value, and can adapt to high-voltage, high-power usage scenarios; and due to the compatibility of the surface silicon process and the integrated circuit process, it can be used The integrated passive device of the three-dimensional silicon-based capacitor is directly mounted in the integrated circuit, which improves the anti-interference ability of the circuit. Moreover, the preparation process of the three-dimensional silicon-based capacitor is simple, and the production cost of the capacitor can be reduced.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the specific embodiments of the present invention are enumerated below.

Description of drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiment. The drawings are only for the purpose of illustrating a preferred embodiment and are not to be considered as limiting the invention. Also throughout the drawings, the same reference numerals are used to designate the same components. In the attached picture:

1 shows a schematic diagram of the microstructure of a three-dimensional silicon-based capacitor 100 having a conductive layer-dielectric layer-conductive layer structure according to an embodiment of the present invention;

FIG. 2 shows a schematic diagram of the microstructure of a three-dimensional silicon-based capacitor 200 with two conductive layer-dielectric layer-conductive layer structures according to an embodiment of the present invention;

FIG. 3 shows a schematic top view of a three-dimensional silicon-based capacitor 300 according to an embodiment of the present invention;

FIG. 4 shows a schematic flowchart of a method 400 for manufacturing a three-dimensional silicon-based capacitor according to an embodiment of the present invention.

detailed description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

As we all know, the capacitance value of a capacitor is determined by the following formula:

Among them, _ε0 is the vacuum permittivity, _εr is the relative permittivity, A is the effective area of the capacitor, and d is the distance between the two plates of the capacitor. To increase the capacitance value, you can start from three angles: choose a material with a high relative permittivity; increase the effective area between the conductive layers per unit area; reduce the distance between the two conductive layers. Since silicon capacitors are made of silicon materials using a semiconductor manufacturing process, it is beneficial to the integration of capacitor devices. Reducing the size of the capacitors allows them to be placed close to highly integrated high-performance system semiconductors, facilitating power optimization. In order to realize the integration of capacitor devices and increase the capacitance value of the capacitor without increasing the volume of the capacitor, this proposal proposes a three-dimensional silicon-based capacitor and its preparation method.

FIG. 1 shows a schematic diagram of the microstructure of a three-dimensional silicon-based capacitor 100 having a conductive layer-dielectric layer-conductive layer structure according to an embodiment of the present invention. As shown in FIG. 1 , the side view of the microstructure of a three-dimensional silicon-based capacitor 100 includes a groove structure etched on a silicon substrate, and conductive layers, dielectric layers, and conductive layers are alternately deposited on the groove structure, and different conductive layers The layers are completely isolated by a dielectric layer. The groove structure includes a silicon pillar array and a groove between the silicon pillar array. The groove is filled with an isolation layer, and a first electrode layer is deposited on the top conductive layer and the isolation layer, so that The outermost conductive layer deposited on the trench structure forms an ohmic contact with the first electrode layer; a redistribution layer is etched on the back of the silicon substrate and a second electrode layer is deposited, so that the innermost conductive layer deposited on the trench structure An ohmic contact is formed with the second electrode layer through the redistribution layer. Among them, the shape of the silicon column array can be in various forms such as cylinder, diamond column, star column, honeycomb column, etc., and can also include a variety of silicon columns of different shapes at the same time. The interval between adjacent silicon columns in the silicon column array The distance is the same. In an embodiment of the present invention, the aspect ratio of the trench structure is between 2:1 and 50:1, that is, the ratio of the height to width of the silicon pillar is between 2:1 and 50:1. It should be noted that, The aspect ratio of the groove structure in this embodiment is only exemplary, and may be properly adjusted according to actual requirements.

The materials of the conductive layer, the first electrode layer and the second electrode layer can be metal materials such as Cu (copper), Al (aluminum), Ta (tantalum) or alloy materials such as copper alloy and aluminum alloy, cadmium sulfide (CdS), selenium Cadmium chloride (CdSe), or composite materials combined with various metal materials, etc., the dielectric layer and isolation layer can be selected from materials with high dielectric constant (high dielectric constant indicates that the material has poor conductivity and good insulation performance), such as SiO2 ( Silicon dioxide), BaO (barium oxide), HfO2 (hafnium dioxide), ZrO2 (zirconium dioxide), Al2O3 (alumina), BaZrO3, BaTiO3 and other barium titanate and lead titanate materials with ilmenite phase structure . Dielectric layers can prevent interconnection between different conductive layers. The etched wires in the redistribution layer enable the innermost conductive layer to form an ohmic contact with the second conductive layer.

FIG. 2 shows a schematic diagram of the microstructure of a three-dimensional silicon-based capacitor 200 having a structure of two conductive layers-dielectric layers-conductive layers according to an embodiment of the present invention. As shown in Figure 2, the first conductive layer, the first dielectric layer, the second conductive layer, the second dielectric layer, and the third conductive layer are sequentially deposited on the trench structure to form two conductive layers-dielectric layer - Conductive layer structure, a redistribution layer is etched on the bottom of the silicon substrate, and wires in the redistribution layer can connect the first conductive layer to the second electrode layer. It should be noted that the microstructures of the three-dimensional silicon-based capacitors shown in Figures 1 and 2 are only exemplary, and the number of conductive layer-dielectric layer-conductive layer structures can be increased according to the actual required capacitance value. Capacitor values are expected to range up to 5nF-5uF.

FIG. 3 shows a schematic top view of a three-dimensional silicon-based capacitor 300 according to an embodiment of the present invention. As shown in FIG. 3 , the three-dimensional silicon-based capacitor 300 can be connected in series or in parallel on the silicon substrate by wire bonding, so as to achieve the desired capacitance value.

According to an embodiment of the present invention, semiconductor devices such as doped resistors, PiN diodes, and Schottky diodes can be formed on the backside of the silicon substrate of the above-mentioned three-dimensional silicon-based capacitor through a doping process, thereby realizing an integrated Passive components. Resistors or semiconductor devices can be produced by doping the backside of a silicon substrate by ion implantation. The resistivity of a resistor or semiconductor device is determined by the carrier concentration and mobility, and the higher the doped impurity concentration, the smaller the resistivity. The semiconductor device may include a silicon substrate, a PN junction and a highly doped resistance region, and the resistance region and the semiconductor device region may be circuit-connected through a redistribution layer to form a functional passive device.

FIG. 4 shows a schematic flowchart of a method 400 for manufacturing a three-dimensional silicon-based capacitor according to an embodiment of the present invention. As shown in FIG. 4 , the method 400 begins with step S410 , etching a trench structure on the surface of the silicon substrate, and the trench structure includes a silicon pillar array and trenches between the silicon pillar arrays.

In order to increase the effective area of the capacitor, the silicon substrate can be etched to form a groove structure. Generally, several times of plasma etching can be used to realize the deep etching of the surface of the silicon material. The aspect ratio of the trench structure can reach (2-50): 1. This 50:1 high aspect ratio trench structure is conducive to the three-dimensional integrated design of the silicon capacitor structure, thereby reducing the volume of the capacitor while ensuring the capacitor higher capacitance value.

Then step S420 is performed, depositing a conductive layer on the surface of the trench structure, depositing a dielectric layer on the surface of the conductive layer, so that the dielectric layer completely covers the surface of the conductive layer, depositing a conductive layer on the surface of the dielectric layer, so that the conductive layer completely covers the dielectric layer. On the surface of the electrical layer, at least one conductive layer-dielectric layer-conductive layer structure is formed. Among them, the conductive layer and the dielectric layer can be deposited by physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma enhanced chemical vapor deposition (HPECVD), plasma enhanced chemical vapor deposition (PECVD) and other methods.

Finally, step S430 is performed, depositing the first electrode layer on the top conductive layer and the isolation layer, etching the redistribution layer and depositing the second electrode layer on the bottom of the silicon substrate, so that the outermost conductive layer deposited on the trench structure and the second electrode layer One electrode layer forms an ohmic contact, and the innermost conductive layer deposited on the trench structure forms an ohmic contact with the second electrode layer, thereby obtaining a three-dimensional silicon-based capacitor with a preset capacitance value.

The scheme of the present invention forms a three-dimensional capacitor microstructure with at least one conductive layer-dielectric layer-conductive layer structure on the silicon substrate through a mature semiconductor etching process, which can greatly increase the effective area of the capacitor electrode, thereby improving the unit area. Capacitance can ensure a high capacitance while reducing the size of the capacitor, and can adapt to high-voltage, high-power usage scenarios; and due to the compatibility of the surface silicon process and the integrated circuit process, it is possible to use a three-dimensional silicon base The integrated passive components of the capacitor are directly mounted in the integrated circuit, which improves the anti-interference ability of the circuit. Moreover, the preparation process of the three-dimensional silicon-based capacitor is simple, and the production cost of the capacitor can be reduced.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, in order to streamline this disclosure and to facilitate an understanding of one or more of the various inventive aspects, various features of the invention are sometimes grouped together in a single embodiment, figure, or its description. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this invention.

Those skilled in the art will understand that the modules or units or components of the devices in the examples disclosed herein may be arranged in the device as described in this embodiment, or alternatively may be located in a different location than the device in this example. in one or more devices. The modules in the preceding examples may be combined into one module or furthermore may be divided into a plurality of sub-modules.

Those skilled in the art can understand that the modules in the device in the embodiment can be adaptively changed and arranged in one or more devices different from the embodiment. Modules or units or components in the embodiments may be combined into one module or unit or component, and furthermore may be divided into a plurality of sub-modules or sub-units or sub-assemblies. All features disclosed in this specification (including accompanying claims, abstract and drawings) and any method or method so disclosed may be used in any combination, except that at least some of such features and/or processes or units are mutually exclusive. All processes or units of equipment are combined. Each feature disclosed in this specification (including accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will understand that although some embodiments described herein include some features included in other embodiments but not others, combinations of features from different embodiments are meant to be within the scope of the invention. and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.

Furthermore, some of the described embodiments are described herein as a method or combination of method elements that may be implemented by a processor of a computer system or by other means for performing the described function. Thus, a processor with the necessary instructions for carrying out the described method or element of a method forms a means for carrying out the method or element of a method. Furthermore, elements described herein of an apparatus embodiment are examples of means for carrying out the function performed by the element for the purpose of carrying out the invention.

As used herein, unless otherwise specified, the use of ordinal numbers "first," "second," "third," etc. to describe generic objects merely means referring to different instances of similar objects and is not intended to imply such The described objects must have a given order temporally, spatially, sequentially or in any other way.

While the invention has been described in terms of a limited number of embodiments, it will be apparent to a person skilled in the art having the benefit of the above description that other embodiments are conceivable within the scope of the invention thus described. In addition, it should be noted that the language used in the specification has been chosen primarily for the purpose of readability and instruction rather than to explain or define the inventive subject matter. Accordingly, many modifications and alterations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the appended claims. The disclosure of the present invention is intended to be illustrative rather than restrictive with respect to the scope of the present invention, which is defined by the appended claims.

Claims (8)

1. A three-dimensional silicon-based capacitor comprises a groove structure etched on a silicon substrate, and is characterized in that conducting layers and dielectric layers are alternately deposited on the groove structure, different conducting layers are completely isolated through the dielectric layers, the groove structure comprises a silicon column array and a groove between the silicon column arrays, an isolation layer is filled in the groove, a first electrode layer is deposited on a top conducting layer and the isolation layer, and an outermost conducting layer deposited on the groove structure and the first electrode layer form ohmic contact; the back of the silicon substrate is etched with a redistribution layer and deposited with a second electrode layer, so that the innermost conductive layer deposited on the trench structure forms ohmic contact with the second electrode layer through the redistribution layer.

2. The three-dimensional silicon-based capacitor according to claim 1, wherein the trench structure has an aspect ratio of (2-50): 1.

3. The three-dimensional silicon-based capacitor according to claim 1, wherein the conductive layer and the electrode layer are made of any one or more of Cu, al, ta, graphite, cdS, cdSe and a composite material.

4. The three-dimensional silicon-based capacitor according to claim 1, wherein the material of the dielectric layer and the isolation layer is SiO ₂ 、BaO、HfO ₂ 、ZrO ₂ 、Al ₂ O ₃ 、BaZrO ₃ 、BaTiO ₃ One or more of them.

5. A method of fabricating a three-dimensional silicon-based capacitor, the method comprising:

etching a groove structure on the surface of the silicon substrate, wherein the groove structure comprises a silicon column array and a groove between the silicon column arrays;

depositing a conducting layer on the surface of the groove structure, depositing a dielectric layer on the surface of the conducting layer to enable the dielectric layer to completely cover the surface of the conducting layer, depositing a conducting layer on the surface of the dielectric layer to enable the conducting layer to completely cover the surface of the dielectric layer, and forming at least one conducting layer-dielectric layer-conducting layer structure;

and depositing a first electrode layer on the top conducting layer and the isolation layer, etching the redistribution layer at the bottom of the silicon substrate and depositing a second electrode layer, so that the outermost conducting layer deposited on the trench structure forms ohmic contact with the first electrode layer, and the innermost conducting layer deposited on the trench structure forms ohmic contact with the second electrode layer, thereby obtaining the three-dimensional silicon-based capacitor.

6. The method of claim 5, wherein the method comprises:

and depositing the conducting layer and the dielectric layer by any one method of physical vapor deposition, atomic layer deposition, high-density plasma enhanced chemical vapor deposition and plasma enhanced chemical vapor deposition.

7. An integrated passive device, characterized in that it comprises a three-dimensional silicon-based capacitor as claimed in any one of claims 1 to 5 and a resistor and/or a semiconductor device arranged on the back of the silicon substrate of said three-dimensional silicon-based capacitor.

8. The integrated passive device of claim 7, wherein the resistor or semiconductor device is created by ion implantation doping of different concentrations at the back side of the silicon substrate.

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