CN103346148B - A kind of Vertical-type capacitor structure and preparation method thereof - Google Patents

Abstract

The invention relates to a vertical capacitor structure and a manufacturing method thereof, belonging to the technical field of microelectronic passive devices. Its structure specifically includes: a deep trench structure located in the wafer substrate, an insulating layer and a conductive layer sequentially deposited on the inner sidewall of the deep trench, and a dielectric layer filled between the conductive layers. The insulating layer, the conductive layer, the dielectric layer and the deep trench are of the same height. Based on the principle of expanding the capacitance area in the vertical direction of the substrate, the electrode plate area in the vertical direction is used to make metal electrode plates by sputtering, electroplating and other processes, and the plates are made of low-resistivity materials such as metal. Combined with through-silicon via technology, a vertical capacitor with a large aspect ratio is realized; combined with substrate back thinning technology, the vertical capacitor structure runs through the substrate and can be used as a high-frequency channel between multi-layer chips; it can greatly save layout area, Improve integrated circuit integration.

Description

A vertical capacitor structure and manufacturing method thereof

technical field

The invention relates to a vertical capacitor structure and a manufacturing method thereof, belonging to the technical field of microelectronic passive devices.

Background technique

Capacitors are passive devices with the function of storing charges, and have electrical functions such as decoupling, switching noise suppression, bypass filtering, AC/DC conversion, and signal isolation. It has important functions both in discrete device circuits and integrated circuits. Capacitance values typically vary on the order of picofarads (pF) to microfarads (μF).

In the development of integrated circuits for more than 40 years, the feature size of transistors has been continuously reduced following Moore's Law, and the functions and performance of integrated circuits have been continuously improved. However, the size of the capacitor cannot be effectively reduced due to the limitation of the dielectric material, and it is currently much larger than the size of the transistor. In integrated circuits, especially in the design of analog integrated circuits, the area of a single picofarad capacitor is as high as ~1000 μm ² , which greatly increases the total area of the chip, thus significantly increasing the manufacturing cost of the chip. Although there are area-saving capacitors, such as high dielectric constant capacitors, capacitors with this structure often have high losses and poor voltage coefficients, which are difficult to meet the needs of high-performance analog circuits. On the other hand, the capacitance value is difficult to reach the microfarad level, and researchers have to use other methods to make up for this defect. It can be seen that in the future development, it is still necessary to design high-density, high-performance, and low-cost capacitors to meet market demand.

Today's CMOS integrated circuit processes use thin-film technology to manufacture capacitors. In order to obtain a higher capacitance density, films with higher dielectric constants, such as BaTiO ₃ and PbZr _x Ti _1-x O ₃ , are generally used as dielectrics. Since the breakdown voltage of the capacitor is inversely proportional to the dielectric constant of the dielectric, the capacitor obtained by this scheme has a lower breakdown voltage; The capacitance obtained by the scheme also has high temperature sensitivity. How to increase the capacitance density while ensuring the electrical performance of the device is a hot research topic.

Vertical capacitors are a viable way to achieve high density capacitance. By using a high-density deep trench structure, the capacitance area can be effectively increased, thereby increasing the capacitance density. Combined with wafer thinning technology, it can be used for high-frequency channels connecting upper and lower chips in three-dimensional integration technology. The existing trench capacitor structure cannot be completely called a vertical capacitor. Although the capacitor area is expanded by the vertical substrate method, the upper and lower electrode plates are still similar to the flat capacitor, and the electrode plate filling material is mostly polysilicon. , the resistance value is large, and the surface of the groove cannot be fully charged. On the other hand, the existing deep-trench capacitor structure is mostly used in memory, and has not been applied to high-frequency channels between multi-layer chips in three-dimensional integrated circuits.

Contents of the invention

The object of the present invention is to propose a vertical capacitor structure and a manufacturing method thereof in order to improve the capacitance density and integration of integrated circuits.

The vertical capacitor of the present invention is based on the idea of expanding the capacitor area in the direction perpendicular to the substrate, which is different from the material of the electrode plate of the trench capacitor and its manufacturing method. It utilizes the area of the electrode plate in the vertical direction and is manufactured by sputtering, electroplating and other processes. Metal electrode plate, the plate is made of low resistivity materials such as metal. Combined with through-silicon via technology, a vertical capacitor with a large aspect ratio is realized; combined with substrate back thinning technology, the vertical capacitor structure runs through the substrate and can be used as a high-frequency channel between multi-layer chips.

A vertical capacitor, the specific structure includes: a deep groove structure located in a wafer substrate, an insulating layer and a conductive layer deposited on the inner wall of the deep groove in sequence, and a dielectric layer filled between the conductive layers. The insulating layer, the conductive layer, the dielectric layer and the deep trench are of the same height.

The vertical capacitor is vertically embedded in the wafer substrate and penetrates the wafer substrate from top to bottom.

The deep groove structure is ring-shaped. The rings include circular rings, circular rings and polygonal rings.

The deep groove structure can also be two parallel rectangular strips, or two parallel polygonal strips.

The wafer substrate material is one of silicon wafer, glass wafer, sapphire wafer, gallium arsenide and organic wafer.

The material of the insulating layer is one of silicon dioxide, aluminum oxide, silicon oxynitride, silicon nitride and high molecular polymer.

The conductive layer material is one of copper, aluminum, iron, nickel, titanium, tungsten, platinum, gold, silver, titanium, palladium, tantalum, polysilicon, titanium silicide, tungsten silicide, molybdenum silicide, platinum silicide and cobalt silicide .

The dielectric layer material is one of silicon nitride, silicon dioxide, tantalum oxide, titanium oxide, zinc oxide, lead zirconate titanate, barium strontium titanate, and high molecular polymer.

The high molecular polymer is one of benzocyclobutene, polyimide, polyethylene, polydimethylsiloxane, polymethyl methacrylate and epoxy resin.

The capacitance value is related to the dielectric material and thickness of the dielectric layer, the height of the deep groove and the surface area of the inner side wall. The higher the height, the larger the surface area of the inner side wall, and the greater the capacitance value. The smaller the thickness of the dielectric, the greater the dielectric constant and the greater the capacitance.

A method for manufacturing a vertical loop-shaped capacitor structure, comprising the steps of:

Step 1, using deep reactive ion etching technology to form a deep trench structure perpendicular to the bottom surface of the substrate on the wafer substrate;

Step 2, depositing an insulating layer on the inner sidewall of the deep trench structure and the upper surface of the wafer substrate;

Step 3, depositing a conductive layer on the insulating layer;

Step 4, filling a dielectric material in the deep trench formed by the conductive layer to form a dielectric layer;

Step 5, removing the dielectric layer and the conductive layer on the upper surface of the wafer substrate;

Step 6, thinning the lower surface of the wafer substrate until the conductive layer is exposed.

Another method for manufacturing a vertical strip capacitor structure includes the following steps:

Step 1, making two strip-shaped deep groove structures side by side on the wafer substrate;

Step 2, depositing an insulating layer on the inner sidewall of the strip-shaped deep trench structure and the upper surface of the wafer substrate;

Step 3, filling the deep groove between the insulating layers with conductive material to form two strip-shaped conductive layers;

Step 4, removing the wafer substrate and insulating layer between the two strip-shaped conductive layers by means of etching to form an upright deep trench structure equal in height to the conductive layer;

Step 5, filling the deep trench structure formed in step 4 with a dielectric material to form a dielectric layer;

In step 6, thinning is performed on the back of the wafer substrate until the conductive layer is exposed.

Beneficial effect

The invention replaces the capacitor structure in the traditional integrated circuit technology, transforms the flat capacitor into a vertical capacitor, easily realizes a large capacitance density, and can remove the capacitor layout when designing the circuit without changing the original CMOS technology. Only the corresponding capacitor interface is left, and the purpose of connecting the capacitor is achieved by bonding the wafer with the vertical capacitor structure. The capacitor can be made above or below the integrated circuit through three-dimensional integration technology, so that the capacitor structure is independent, which can greatly save the layout The area, its manufacturing process is compatible with the vertical interconnection technology in the three-dimensional integrated circuit, and can be made on the same layer as the through-silicon via structure, which can greatly improve the integration degree of the integrated circuit.

Description of drawings

FIG. 1 is a three-dimensional schematic diagram of the structure of a vertical loop capacitor provided in Embodiment 1 of the present invention. In the figure, S1 is a wafer substrate, S2 is a circular deep trench structure, 101 is an insulating layer, 102 is a conductive layer, and 103 is a dielectric layer;

Fig. 2 is a schematic diagram of forming a circular deep groove structure on a wafer substrate according to Embodiment 1 of the present invention; wherein (a) is a schematic cross-sectional view, and (b) is a schematic top view;

3 is a schematic diagram of forming an insulating layer, a conductive layer and a dielectric layer provided by Embodiment 1 of the present invention;

4 is a schematic diagram after removing the dielectric layer and the conductive layer on the surface of the wafer substrate provided by Embodiment 1 of the present invention, wherein (a) is a schematic cross-sectional view, and (b) is a schematic top view;

Fig. 5 is a schematic diagram after thinning the back of the wafer substrate provided by Embodiment 1 of the present invention;

6 is a schematic diagram of two strip-shaped deep groove structures provided by Embodiment 2 of the present invention. In the figure, S21 is a wafer substrate, and S22 is two parallel strip-shaped deep groove structures;

7 is a schematic diagram of a conductive layer deposited with an insulating layer in a deep trench structure provided by Embodiment 2 of the present invention; in the figure, 201 is an insulating layer on the upper surface, and 202 is a conductive layer;

8 is a schematic diagram of forming a deep trench between two conductive layers according to Embodiment 2 of the present invention; in the figure, S23 is a deep trench structure between two conductive layers.

Fig. 9 is a schematic diagram of the filled dielectric layer provided by Embodiment 2 of the present invention; 203 in the figure is a dielectric layer;

FIG. 10 is a schematic diagram of the backside thinning of the wafer substrate provided by Embodiment 2 of the present invention;

Figure 11 is a schematic diagram of the interdigitated parallel structure of vertical strip capacitors provided by Embodiment 3 of the present invention, wherein S31 is a wafer substrate, S32 is an interdigitated electrode, 301 is an insulating layer, 302 is a conductive layer, and 303 is a dielectric layer.

detailed description

The invention discloses a vertical capacitor structure. As shown in FIG. 1, the vertical capacitor includes: a wafer substrate, a deep groove structure, an insulating layer and a conductive layer located on the sidewall of the deep groove, and a conductive layer located on the conductive layer. dielectric layer between. Compared with the flat capacitor commonly used in current integrated circuits, the vertical capacitor disclosed in the present invention has the advantages of occupying a small chip area and having high capacitance density. In the following, the present invention will be further described in detail in combination with specific examples and accompanying drawings, and two specific implementation schemes will be disclosed.

Specific embodiment 1: vertical shape capacitor structure and manufacturing method thereof.

As shown in FIG. 2 , deep reactive ion etching technology is used to etch a circular deep trench S2 on the wafer substrate S1 . The width of the deep trench is 5-10 microns; the length of the deep trench is not strictly limited, and can be 5-200 microns; the depth of the deep trench is less than the thickness of the wafer substrate, and can be 60-500 microns; the shape of the deep trench is One of a shape, a circular ring, or a polygonal ring.

As shown in Figure 3, the insulating layer 101 silicon dioxide is deposited on the inner wall of the deep trench by plasma enhanced chemical vapor deposition; the copper seed layer is deposited by sputtering technology, and the thickness of the copper layer is increased by electroplating to form a conductive layer 102, used as inner and outer electrode plates. The thickness of the copper seed layer is not strictly limited, and may be 50nm-300nm; the thickness of the conductive layer may be 1 μm-5 μm. Finally, spraying, spin coating, plasma enhanced chemical vapor deposition or vacuum adsorption technology is used to fill the deep trench with silicon nitride, silicon dioxide, tantalum oxide, titanium oxide, zinc oxide, lead zirconate titanate, barium strontium titanate One of them forms a dielectric layer 103 .

As shown in FIG. 4 , the dielectric layer 103 and the conductive layer 102 deposited on the surface of the wafer substrate S1 are sequentially removed by chemical mechanical polishing technology, and the insulating layer 101 on the surface of the wafer substrate S1 is retained.

As shown in Figure 5, firstly, the rough grinding technology is used to remove most of the back substrate until the back substrate is close to the bottom of the deep groove; then the chemical mechanical polishing technology is used to planarize the back substrate until the deep groove is exposed, and ground The conductive layer at the bottom of the deep trench is connected to form independent inner and outer electrode plates.

Specific embodiment 2: vertical strip capacitor structure and manufacturing method thereof.

As shown in FIG. 6 , in this embodiment, the same manufacturing method as in Embodiment 1 is used to manufacture two strip-shaped deep groove structures S22 side by side. The production range of the length of the deep trench under the existing technology is 5-200 microns; the width of the deep trench in this embodiment is 3-5 microns; the depth of the deep trench is less than the thickness of the wafer substrate S21, which can be 60-500 microns; The distance between the deep grooves is 2-5 microns; the shape of the deep grooves is a rectangle or an "S" polygon.

As shown in FIG. 7 , in this embodiment, the same fabrication method as in Embodiment 1 is used to deposit an insulating layer 201 and a conductive layer 202 in the deep trench S21 until the deep trench is filled.

As shown in FIG. 8 , the silicon between the conductive layers 202 is etched by deep reactive ion etching technology to form a strip-shaped deep trench structure S23 .

As shown in Figure 9, the deep trench S23 is filled with silicon nitride, silicon dioxide, tantalum oxide, titanium oxide, zinc oxide, lead zirconate titanate, and barium strontium titanate by plasma enhanced chemical vapor deposition or vacuum adsorption technology. One of them forms a dielectric layer 203 .

As shown in FIG. 10 , in this embodiment, the same fabrication method as in Embodiment 1 is used to thin the back of the wafer substrate until the conductive layer 202 is exposed.

Specific embodiment 3: vertical strip capacitor interdigitated parallel structure.

As shown in Figure 11, this embodiment uses the manufacturing method in Embodiment 2 to manufacture three vertical strip capacitors on the same wafer substrate, wherein 301 is an insulating layer, 302 is a conductive layer, and 303 is a dielectric layer , and then use the surface interconnection process to form the interdigitated electrode S32 to form a parallel capacitor structure.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (4)

1. A manufacturing method of an upright return-shaped capacitor structure, comprising the steps of: Step 1, using deep reactive ion etching technology to form a deep trench structure perpendicular to the bottom surface of the substrate on the wafer substrate; Step 2, depositing an insulating layer on the inner sidewall of the deep trench structure and the upper surface of the wafer substrate; Step 3, depositing a conductive layer on the insulating layer; Step 4, filling a dielectric material in the deep trench formed by the conductive layer to form a dielectric layer; Step 5, removing the dielectric layer and the conductive layer on the upper surface of the wafer substrate; Step 6, thinning the lower surface of the wafer substrate until the conductive layer is exposed. 2. The manufacturing method of a vertical loop capacitor structure according to claim 1, characterized in that, the shape of the deep groove can also be a circular ring or a polygonal ring. 3. A manufacturing method of an upright strip capacitor structure, comprising the steps of: Step 1, making two strip-shaped deep groove structures side by side on the wafer substrate; Step 2, depositing an insulating layer on the inner sidewall of the strip-shaped deep trench structure and the upper surface of the wafer substrate; Step 3, filling the deep groove between the insulating layers with conductive material to form two strip-shaped conductive layers; Step 4, removing the wafer substrate and insulating layer between the two strip-shaped conductive layers by means of etching to form an upright deep trench structure equal in height to the conductive layer; Step 5, filling the deep trench structure formed in step 4 with a dielectric material to form a dielectric layer; In step 6, thinning is performed on the back of the wafer substrate until the conductive layer is exposed. 4 . The method for manufacturing a vertical strip capacitor structure according to claim 3 , wherein the strip shape includes a rectangle or a polygon.