CN115547927A - Preparation method of array substrate, array substrate and display panel - Google Patents

Abstract

The application relates to the technical field of display panels and discloses a preparation method of an array substrate, the array substrate and the display panel. Sequentially forming a grid metal layer, a grid insulating layer and a first semiconductor layer on a substrate; the preparation method is characterized by further comprising the following steps: and forming a photoresist layer on the first semiconductor layer, exposing and developing the photoresist layer through a mask plate to form a patterned photoresist layer, wherein the patterned photoresist layer comprises a first photoresist layer module and a second photoresist layer module, a second semiconductor layer and a second metal layer are sequentially formed, the first photoresist layer module is completely removed, the second photoresist layer module with partial thickness is reserved as a buffer module, and the patterned first semiconductor layer is etched to form a first channel and a second channel. Compared with the prior art, the method has the advantages of reducing etching times, simplifying processing technology, improving uniformity of the characteristics of the etched panel and effectively improving the quality of the panel.

Description

Preparation method of array substrate, array substrate and display panel

technical field

The present application relates to the technical field of display panels, in particular to a method for preparing an array substrate, an array substrate and a display panel.

Background technique

A thin film transistor liquid crystal display (TFT-LCD) is composed of an array glass substrate (Array), a color filter glass substrate (CF) and a cell of the two. The transmission array substrate includes the gate signal line (GE) or the first metal layer (M1) (GE or M1) formed on the substrate, the gate insulating layer (GI), the amorphous silicon semiconductor layer (a-Si), The source and drain or the second metal layer (SD or M2), passivation layer (PV) and transparent electrode (ITO), the preparation of the array substrate often adopts the 4mask process, and the amorphous silicon semiconductor layer (a-Si layer) and the source and drain The electrode layer (SD layer) is combined into one layer. In the preparation process of the traditional array substrate, etching is often used to form the required patterned film layer, and except for the gate insulating layer (GI), which does not need to be patterned, other various All layers need to use a mask (Mask) to form a patterned film layer through a yellow light process. Due to the need for multiple etchings, it is easy to cause poor uniformity of panel characteristics, especially now that more and more large-size products are more likely to appear. The problem of abnormal panel quality.

Contents of the invention

In order to solve the technical problem of many etching times and difficult control of the array substrate, the main purpose of the present application is to provide a method for preparing an array substrate, an array substrate and a display panel that can reduce the number of etching times and simplify the process.

In order to realize the above-mentioned purpose of the invention, the application adopts the following technical solutions:

According to one aspect of the present application, a method for preparing an array substrate is provided, including sequentially forming a gate metal layer, a gate insulating layer, and a first semiconductor layer on the substrate; the preparation method further includes the steps of:

forming a photoresist layer on the first semiconductor layer;

Exposing and developing the photoresist layer through a mask, forming a first subbing layer module and a second subbing layer module on the first semiconductor layer, and the connection between the first subbing layer module and the second subbing layer module There is an opening in contact with the first semiconductor layer, and the thickness of the second glue layer module is greater than the thickness of the first glue layer module;

sequentially forming a second semiconductor layer and a second metal layer;

completely removing the first glue layer module, exposing the first semiconductor layer corresponding to the first glue layer module, and retaining a part of the thickness of the second glue layer module as a buffer module to pattern the second semiconductor layer and the second metal layer;

Etching and patterning the first semiconductor layer to form a first channel in contact with the gate insulating layer, and cleaning the buffer module at the same time, the second metal layer corresponding to the adjacent opening, the A second channel in contact with the first semiconductor layer is formed between the second semiconductor layers.

According to an embodiment of the present application, after exposing and developing the photoresist layer through a mask, the steps further include:

Plasma bombardment, so that the first semiconductor layer sputters inorganic particles outward, forming a discontinuous masking layer on the surface of the first glue layer module and the second glue layer module;

Etching the masking layer to perform texturing on the masking layer to form a peeling cavity in contact with the first adhesive layer module and the second adhesive layer module;

sequentially forming a second semiconductor layer and a second metal layer;

immersing the stripping liquid into the stripping chamber to contact the first glue line module and the second glue line module, so as to completely remove the first glue line module and retain part of the thickness of the second glue line The module serves as the buffer module to pattern the second semiconductor layer and the second metal layer.

According to an embodiment of the present application, the masking layer is etched to texture the masking layer, wherein, after etching the masking layer, the surface of the first adhesive layer module and the second A plurality of support columns are formed on the surface of the second glue layer module, and the stripping cavity is formed between adjacent support columns.

所述支撑柱的高度为

所述支撑柱的最大外径的范围为

According to an embodiment of the present application, wherein the thickness of the mask layer is

The height of the support column is

The range of the maximum outer diameter of the support column is

According to an embodiment of the present application, wherein the stripping solution is a mixed solution including amine basic organic substances and polar organic solvents, and the treatment time for stripping with the stripping solution is 1S-1200S.

According to an embodiment of the present application, the photoresist layer is exposed and developed through a mask, wherein the mask is a semi-transmissive mask, and in a projection plane perpendicular to the substrate, the The first adhesive layer module corresponds to the sub-light transmission area of the mask plate one by one, the second adhesive layer module corresponds to the full shielding area of the mask plate one by one, and the openings correspond to the full shielding area of the mask plate The light-transmitting regions correspond one-to-one.

且

According to an embodiment of the present application, wherein the thickness of the first glue layer module is D1, and the thickness of the second glue layer module is D2, wherein,

and

According to an embodiment of the present application, wherein the thickness of the buffer module is D3, and

According to another aspect of the present application, an array substrate is provided, comprising:

The device structure prepared by the preparation method of the array substrate;

A passivation layer and a pixel electrode layer are sequentially formed on the device structure.

According to another aspect of the present application, a display panel is provided, including:

The above-mentioned array substrate;

The color filter substrate is arranged in a box with the array substrate;

The liquid crystal layer is arranged between the array substrate and the color filter substrate.

From the above technical solutions, it can be seen that the advantages and positive effects of the method for preparing an array substrate, the array substrate and the display panel of the present application are as follows:

By forming a thick photoresist layer on the first semiconductor, after exposing and developing the photoresist layer, retaining the first layer module and the second layer module, and forming an opening in contact with the first semiconductor layer, After forming the second semiconductor layer and the thickness of the second metal layer in sequence, the second semiconductor layer at the opening position is in contact with the first semiconductor layer. After the first glue layer module is completely removed, the corresponding first glue layer module is exposed. semiconductor layer, and retain a part of the thickness of the second adhesive layer module as a buffer module to realize the patterning of the second semiconductor layer and the second metal layer, and then pattern the first semiconductor layer after etching, without The position covered by the buffer module forms a first channel in joint contact with the gate insulating layer. After the buffer module is etched and removed, a channel is formed between the second metal layer and the second semiconductor layer corresponding to the adjacent opening. For the second channel that is in contact with the first semiconductor layer, furthermore, through the preparation method of the present application, compared with the prior art, no etching process is required when patterning the second metal layer and the second semiconductor layer, reducing the etching process. The number of times, the simplification of the processing process, the uniformity of the characteristics of the display panel are improved, and the quality of the display panel is effectively improved.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description serve to explain the principles of the application.

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, In other words, other drawings can also be obtained from these drawings without paying creative labor.

FIG. 1 is a schematic flowchart of a method for preparing an array substrate according to an embodiment of the present application;

FIG. 2 is a schematic flowchart of a method for preparing an array substrate according to another embodiment provided by the embodiment of the present application;

3 is a schematic cross-sectional structure diagram of an array substrate on which a first semiconductor layer is formed in a method for preparing an array substrate provided in an embodiment of the present application;

4 is a schematic cross-sectional structure diagram of an array substrate with a photoresist layer formed in a method for preparing an array substrate provided in an embodiment of the present application;

5 is a schematic cross-sectional structure diagram of an array substrate when exposing a photoresist layer in a method for preparing an array substrate provided in an embodiment of the present application;

6 is a schematic cross-sectional structure diagram of an array substrate when developing a photoresist layer in a method for preparing an array substrate provided in an embodiment of the present application;

FIG. 7 is a schematic cross-sectional structure diagram of an array substrate after texturing in a method for preparing an array substrate provided in an embodiment of the present application;

Fig. 8 is a schematic cross-sectional structure diagram of the first adhesive layer module (second adhesive layer module) after texturing in the method for preparing an array substrate provided by the embodiment of the present application;

9 is a schematic cross-sectional structure diagram of an array substrate after forming a second semiconductor layer in a method for manufacturing an array substrate provided by an embodiment of the present application;

10 is a schematic cross-sectional structure diagram of an array substrate after forming a second metal layer in a method for manufacturing an array substrate provided in an embodiment of the present application;

11 is a schematic cross-sectional structure diagram of the array substrate when the first adhesive layer module is completely removed and a buffer module is formed in a method for preparing an array substrate provided by the embodiment of the present application;

FIG. 12 is a schematic cross-sectional structure diagram of the array substrate after etching and patterning the first semiconductor layer in a method for preparing an array substrate provided by an embodiment of the present application;

FIG. 13 is a schematic flowchart of a method for manufacturing an array substrate according to another embodiment provided by the embodiments of the present application.

in:

10. Substrate; 20. Gate metal layer; 30. Gate insulating layer; 40. First semiconductor layer;

50. Photoresist layer; 51. First glue layer module; 52. Second glue layer module; 53. Opening hole; 54. Buffer module;

60. The second semiconductor layer; 70. The second metal layer; 80. The first channel; 90. The second channel; 100. The mask plate; 1. The mask layer;

detailed description

In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of this application, but not all of them. Based on the embodiments in the present application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present application.

In the prior art, at least four times of etching are performed during the preparation of the array substrate before the gate signal line (GE) or the first metal layer (M1) (GE or M1 ), the amorphous silicon semiconductor layer (a -Si), source and drain or second metal layer (SD orM2), passivation layer (PV) and transparent electrode (ITO) for patterning, due to the difficulty in controlling the etching process, multiple etchings will lead to the formation of In order to solve the problem of uneven process characteristics of the display panel, in order to solve the technical problem that the number of etching times of the array substrate is high and the uniformity of etching is difficult to control, the main purpose of this application is to provide a method that can reduce the number of etching times and improve the uniformity of etching. A method for preparing an array substrate and the array substrate.

In order to realize the above-mentioned purpose of the invention, the application adopts the following technical solutions:

According to one aspect of the present application, a method for preparing an array substrate is provided, including:

S10: sequentially forming a gate metal layer 20, a gate insulating layer 30, and a first semiconductor layer 40 on the substrate 10;

In one embodiment of the present application, the first metal layer is formed by physical vapor deposition (PVD) on the glass substrate 10, and then the yellow light process (Photo) is carried out through the first optical diffraction film plate (mask) to form a patterned positive Photoresist layer 50 (PR), wherein the Photo process includes coating photoresist, exposure and development processes;

Then, the metal not covered by PR is removed by wet etching (Wet) process to form patterned gate signal line (GE) and array common electrode (A_Com), and finally the PR layer is peeled off by stripping solution. When the first metal After the layer is completed its thickness is

其成分为氮化硅或者氧化硅或氮化硅与氧化硅组合层，第一半导体层40(a-si)层厚度为

其成分为非晶硅。Then by chemical vapor deposition (CVD) a layer of gate insulating layer 30 (GI) and the first semiconductor layer 40 (a-si), wherein the thickness of the GI layer is

Its composition is silicon nitride or silicon oxide or a combination layer of silicon nitride and silicon oxide, and the thickness of the first semiconductor layer 40 (a-si) is

Its composition is amorphous silicon.

The preparation method also includes the steps of:

S20: forming a photoresist layer 50 on the first semiconductor layer 40;

S30: Exposing and developing the photoresist layer 50 through the mask 100, forming a first glue layer module 51 and a second glue layer module 52 on the first semiconductor layer 40, the first glue layer module There is an opening 53 in contact with the first semiconductor layer 40 between the 51 and the second glue layer module 52, and the thickness of the second glue layer module 52 is greater than the thickness of the first glue layer module 51;

S40: sequentially forming the second semiconductor layer 60 and the second metal layer 70;

S50: completely remove the first glue layer module 51, expose the first semiconductor layer 40 corresponding to the first glue layer module 51, and reserve a part of the thickness of the second glue layer module 52 as a buffer module 54, in a pattern Thinning the second semiconductor layer 60 and the second metal layer 70;

S60: Etching and patterning the first semiconductor layer 40 to form a first channel 80 in contact with the gate insulating layer 30 , and cleaning the buffer module 54 at the same time, in the adjacent openings 53 corresponding to A second channel 90 in contact with the first semiconductor layer 40 is formed between the second metal layer 70 and the second semiconductor layer 60 .

Referring to Figures 1-6, by forming a thick photoresist layer 50 on the first semiconductor, after exposing and developing the photoresist layer 50, the first layer module and the second layer module 52 are retained, and formed The opening 53 that is in contact with the first semiconductor layer 40 is formed in sequence with the thickness of the second semiconductor layer 60 and the second metal layer 70. The second semiconductor layer 60 at the position of the opening 53 is in contact with the first semiconductor layer 40, and can pass through the The opening 53 is reserved for the formation of the second semiconductor layer 60 and the second metal layer 70, so that the second semiconductor layer 60 is in contact with the first semiconductor layer 40, and it is convenient for the second semiconductor layer 60 and the second The metal layer 70 is patterned.

In step S30, according to an embodiment of the present application, the photoresist layer 50 is exposed and developed through the mask plate 100, wherein the mask plate 100 is a semi-transmissive mask, which is perpendicular to the In the projection plane of the substrate 10 , the first adhesive layer module 51 is in one-to-one correspondence with the sub-light-transmitting area of the mask 100 , and the second adhesive layer module 52 is in one-to-one correspondence with the full shielding area of the mask 100 Correspondingly, the openings 53 are in one-to-one correspondence with the fully transparent regions of the mask 100 . Furthermore, the thickness of the second glue layer module 52 can be made greater than the thickness of the first glue layer module 51 .

In an example of the present application, a patterned positive photoresist layer 50 (PR) is produced by using a half-tone mask (Half-Tone Mask: HTM) to produce a patterned positive photoresist layer 50 (PR), in which the second metal All the PRs in the positions to be reserved for the layer 70 (SD) (equivalent to the position of the opening 53) are all removed, and the PRs in the positions to be removed in the subsequent SD layer (equivalent to the first adhesive layer module 51 and the second adhesive layer module 52) are retained, and further The PR at the position of the thin-film transistor (TFT) channel (equivalent to the second glue layer module 52) is made using the HTM impermeable part, and the other reserved PRs (equivalent to the first glue layer module 51) are made using the HTM semi-transparent part. Partially manufactured, so the TFT channel position PR will be thicker than the PR reserved in other positions.

TFT沟道处PR厚度(相当于第二胶层模块52)通常较其他位置PR(相当于第一胶层模块51)厚

In this application, other positions reserve PR (equivalent to the first adhesive layer module 51) thickness is

The thickness of PR at the TFT channel (equivalent to the second glue layer module 52) is usually thicker than other positions PR (equivalent to the first glue layer module 51)

且

进而以预留足够厚度的缓冲模块54，为S60在步骤中，形成第二沟道90做基础。That is, the thickness of the first adhesive layer module 51 is D1, and the thickness of the second adhesive layer module 52 is D2, wherein,

and

Furthermore, the buffer module 54 with a sufficient thickness is reserved as a basis for forming the second channel 90 in step S60.

With reference to Fig. 12, after photoresist layer 50 is developed, remove the photoresist layer 50 at opening 53 positions, and the thickness of the second glue layer module 52 is greater than the thickness of the first glue layer module 51, so that After the first glue layer module 51 is completely removed, the second glue layer module 52 also has a remaining thickness to form a buffer module 54, which can facilitate the formation of corresponding in-phase holes in two adjacent openings 53 after etching. A pair of second channel 90 in contact with the first semiconductor layer 40 is formed between the second metal layer 70 corresponding to the adjacent opening 53 and the second semiconductor layer 60 .

And, after the processing in step S50, the first semiconductor layer 40 corresponding to the first glue layer module 51 will be exposed, and the second glue layer module 52 with a partial thickness will be reserved as the buffer module 54 to achieve patterning of the second semiconductor layer 60 and the second metal layer 70, and then pattern the first semiconductor layer 40 by etching in step S60, and form a first channel in joint contact with the gate insulating layer 30 at a position not covered by the buffer module 54 80. After the buffer module 54 is removed by etching, furthermore, through the preparation method of the present application, compared with the prior art, no etching process is required when patterning the second metal layer 70 and the second semiconductor layer 60, reducing the number of etching times , thereby simplifying the processing technology, improving the uniformity of the panel characteristics after multiple etchings, and effectively improving the product quality.

Compared with the existing 4mask process, the TFT-LCD array substrate reduces 2 Wet processes and simplifies a Dry process. At the same time, it can reduce a mask and a yellow light process the same as the existing 5mask process. Due to the reduction of etching process, it can effectively improve the problem of uneven panel process characteristics caused by multi-channel etching process, and then improve the product quality problems caused by uneven process characteristics, such as panel color caused by uneven film thickness of GI process The problem of unevenness, and the electrical reliability problem caused by the uneven length of the channel length and the tail length of the semiconductor layer.

Referring to FIG. 2 and FIG. 7 and FIG. 8, according to an embodiment of the present application, after exposing and developing the photoresist layer 50 through the mask plate 100, that is, after the processing step S30, further includes the step :

S100: plasma bombardment, so that the first semiconductor layer 40 sputters inorganic particles outward, and forms a discontinuous masking layer 1 on the surface of the first glue layer module 51 and the second glue layer module 52 ;

S200: Etching the mask layer 1 to perform texturing treatment on the mask layer 1 to form a stripping cavity 2 in contact with the first adhesive layer module 51 and the second adhesive layer module 52;

通过物理气相沉积法制作一层第二金属层70(SD层)，其厚度为

S300 (S40): Referring to FIGS. 9 and 10, the second semiconductor layer 60 and the second metal layer 70 are sequentially formed; as an example, a layer of boron-doped amorphous silicon layer (N+a- Si layer), its thickness is

Make one deck second metal layer 70 (SD layer) by physical vapor deposition method, its thickness is

S400 (S50): As shown in FIG. 11 , make the stripping solution immersed in the stripping chamber 2 and contact the first adhesive layer module 51 and the second adhesive layer module 52 to completely remove the first adhesive layer. layer module 51 , and retain part of the thickness of the second adhesive layer module 52 as the buffer module 54 to pattern the second semiconductor layer 60 and the second metal layer 70 .

After the step S30, through the processing step S100, a discontinuous masking layer 1 of inorganic particles is formed on the surfaces of the first glue layer module 51 and the second glue layer module 52, wherein the inorganic particles are plasma to the first semiconductor layer 40 The bombardment is formed by sputtering the inorganic particles of the first semiconductor layer 40 , wherein the discontinuous inorganic particles cover the layer 1 .

Referring to the figure, in one embodiment of the present application, argon inert gas plasma (Plasma) is used to bombard the first semiconductor layer 40 (a-Si layer) not covered by the photoresist layer 50 (PR), and the amorphous Silicon (a-Si) is sputtered and transferred to the PR surface, that is, the surfaces of the first glue layer module 51 and the second glue layer module 52 to form a discontinuous inorganic amorphous silicon layer, and its inorganic a-Si layer mask layer 1 has a thickness of

In one embodiment of the present application, the stripping cavity 2 is formed after the step S200, so that the stripping liquid in the subsequent S400 is immersed in the stripping cavity 2 and connected with the first adhesive layer module 51 and the second adhesive layer module 52. Contact, as shown in FIG. 11 , completely remove the first glue layer module 51, and retain the second glue layer module 52 of partial thickness as the buffer module 54, to pattern the second semiconductor layer 60 and The second metal layer 70, and further, after forming and patterning the second semiconductor layer 60 and the second metal layer 70, perform the step of S60, referring to FIG. 12, etching and patterning the first semiconductor layer 40, forming a first channel 80 in contact with the gate insulating layer 30, and cleaning the buffer module 54 at the same time, the second metal layer 70 corresponding to the adjacent opening 53, the first A second channel 90 in contact with the first semiconductor layer 40 is formed between the two semiconductor layers 60 .

Furthermore, through this step, the patterning treatment of the second metal layer 70 and the second semiconductor layer 60 can be completed without etching, compared with the existing 4mask process, two etching processes are reduced, and the preparation process is simplified. Basically, the problem of non-uniform characteristics of the display panel due to the difficulty of etching control is avoided.

According to an embodiment of the present application, the mask layer 1 is etched to texture the mask layer 1, wherein after the mask layer 1 is etched, the surface of the first glue layer module 51 And the surface of the second adhesive layer module 52 forms a plurality of support columns 3 , and the stripping cavity 2 is formed between adjacent support columns 3 . Referring to Fig. 8, the volume of the stripping chamber 2 is improved by the support column 3, so as to avoid covering the stripping chamber 2 when forming the second semiconductor layer 60 and the second metal layer 70, and improve the stripping liquid and the first adhesive layer module 51 and the second The contact area of the adhesive layer module 52 improves the peeling efficiency of the step S400 and improves the peeling accuracy of the first adhesive layer module 51 and the second adhesive layer module 52 .

所述支撑柱3的高度为

所述支撑柱3的最大外径的范围为

以进一步的提高剥离腔2的体积，以提高剥离液与第一胶层模块51及第二胶层模块52的接触面积，提高S400步骤的剥离效率，提高第一胶层模块51及第二胶层模块52的剥离精确度。According to an embodiment of the present application, wherein the thickness of the mask layer 1 is

The height of the support column 3 is

The range of the maximum outer diameter of the support column 3 is

To further increase the volume of the stripping chamber 2, to increase the contact area between the stripping liquid and the first adhesive layer module 51 and the second adhesive layer module 52, improve the stripping efficiency of the S400 step, and improve the first adhesive layer module 51 and the second adhesive layer module 51. The peeling accuracy of the layer module 52.

According to an embodiment of the present application, wherein the stripping solution is a mixed solution including amine basic organic substances and polar organic solvents, and the treatment time for stripping with the stripping solution is 1S-1200S.

In the step S400, the first adhesive layer module 51 and the second adhesive layer module 52 are stripped using a stripping liquid, and the main components of the stripping liquid are amine alkaline organic substances and polar organic solvents. Among them, amine basic organic substances, such as amides or alcohol amines, account for 30%-90%; among them, polar organic solvents such as dimethyl sulfoxide or diethylene glycol butyl ether, etc., account for 10% %-70%. The stripping process time is 1S-1200S.

Corresponding to the second adhesive layer module 52 in the second channel 90 (TFT channel) is thicker than the photoresist retained in the first adhesive layer module 51 corresponding to the first channel 80, after the stripping process, the first A glue layer module 51 is completely peeled off, and the second glue layer module 52 still remains in the second channel 90, forming a buffer module 54, and the thickness of the buffer module 54 is

After step S400, step S60 is performed to remove the first semiconductor layer 40 (a-Si layer) at the position not covered by metal (corresponding to the position of the first channel 80) through a dry etching process, and remove the first semiconductor layer 40 at the same time. PR (equivalent to the buffer module 54) remains in the second channel 90 (TFT channel) and a small part of the first semiconductor layer 40 (a-Si layer) in the second channel 90 (TFT channel), and then completed through the above process The second mask process patterns the first semiconductor layer 40 (a-Si layer) and the second metal layer 70 (SD layer).

Referring to FIG. 13 , according to an embodiment of the present application, after etching and patterning the first semiconductor layer 40, further steps are included:

forming a passivation base layer, and patterning the passivation base layer through a mask 100 to form a passivation layer;

A pixel electrode base layer is formed, and the pixel electrode base layer is patterned through a mask 100 to form a pixel electrode layer.

In one embodiment of the present application, the passivation layer (Passivation: PV) coating is carried out by chemical vapor deposition, and the third mask is used to perform a yellow light process to form a patterned positive photoresist layer 50 (PR), wherein Photo The process includes coating photoresist, exposure and development processes; and then removes the passivation layer not covered by PR through a dry etching (Dry) process to form a patterned passivation layer, which can be used for the second metal layer 70 and the thin film transistor form a protective effect. Finally, the PR layer is peeled off by a stripping solution. The composition of the passivation layer is silicon nitride or silicon oxide or a combined layer of silicon nitride and silicon oxide, and its thickness is

The pixel electrode layer is coated by physical vapor deposition, and the fourth mask is used to perform a yellow light process to form a patterned positive photoresist layer 50 (PR), wherein the Photo process includes coating photoresist, exposure and development processes; and then The pixel electrode layer not covered by PR is removed by a wet etching (Wet) process to form a patterned pixel electrode layer, and finally the PR layer is peeled off by a stripping solution. The composition of the pixel electrode layer is currently used in the industry as indium tin oxide, and it can also be replaced by other transparent conductive materials, such as PEDOT:PSS or silver nanowires, etc., all within the scope of the present invention. The thickness of the pixel electrode layer is

Referring to Figure 1-Figure 12, this application proposes an array substrate preparation method that is the same as the existing 4mask process, which is to combine the a-Si layer and the SD layer into one mask. After the a-Si coating is completed, use the HTM Make the required pattern, remove the organic photoresist layer 50 (PR) layer where the subsequent SD layer metal needs to be reserved in advance in the yellow light process, and then retain the PR at the position where the SD metal layer needs to be removed and use the semi-transparent part of the HTM Fabrication, but the TFT channel position uses the HTM opaque part to reserve the PR, and the PR thickness of this part is thicker than other positions.

After S100 and S200, the remaining PR layer is subjected to texturing treatment by plasma bombardment;

Then perform step S300 of boron-doped (P) a-Si layer (N+a-Si) coating and second metal layer 70 (SD) coating;

Then in S400, the PR layer is stripped using a stripping solution, because there is a layer of velvet nano-pillar PR layer on the surface of the PR, and the N+a-Si and SD layers deposited on the velvet PR are discontinuous The dense film layer (equivalent to the mask layer 1), so the stripping liquid can penetrate the upper covering film layer to contact PR, and peel off the PR layer together with the N+a-Si and SD layers covering the upper layer of PR.

Since the PR in the TFT channel (equivalent to the second channel 90) formed by the HTM is relatively thick (the second adhesive layer module 52), after stripping by the stripping liquid, the PR remaining in other positions (the first adhesive layer module 51) is removed. However, a certain thickness of PR (equivalent to the buffer module 54) will still remain in the channel of the TFT. Finally, the a-Si layer not covered by the metal will be removed through a dry etching process, and the remaining PR in the channel (equivalent to in the buffer module 54) to remove.

The 4mask process of the manufacturing method of the present invention reduces 2 Wet processes and simplifies a Dry process compared with the existing process, and at the same time reduces a mask and a yellow light process the same as the existing 5mask process. Due to the reduction of etching process, it can effectively improve the problem of uneven panel process characteristics caused by multi-channel etching process, and then improve the product quality problems caused by uneven process characteristics, such as panel color caused by uneven film thickness of GI process The problem of unevenness, and the electrical reliability problem caused by the uneven length of the channel length and the tail length of the semiconductor layer.

According to another aspect of the present application, an array substrate is provided, comprising:

The device structure prepared by the preparation method of the array substrate;

A passivation layer and a pixel electrode layer are sequentially formed on the device structure.

According to another aspect of the present application, a display panel is provided, comprising:

The array substrate;

The color filter substrate is arranged in a box with the array substrate;

The liquid crystal layer is arranged between the array substrate and the color filter substrate.

It should be noted that in this article, relative terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these No such actual relationship or order exists between entities or operations. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

The above descriptions are only specific implementation manners of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the application. Therefore, the present application will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims (10)

1. A method for preparing an array substrate, comprising sequentially forming a gate metal layer (20), a gate insulating layer (30) and a first semiconductor layer (40) on a substrate (10); it is characterized in that the preparation The method also includes the steps of: forming a photoresist layer (50) on the first semiconductor layer (40); Exposing and developing the photoresist layer (50) through a mask (100), forming a first glue layer module (51) and a second glue layer module (52) on the first semiconductor layer (40) , there is an opening (53) in contact with the first semiconductor layer (40) between the first glue layer module (51) and the second glue layer module (52), and the second glue layer module (52) ) is greater than the thickness of the first adhesive layer module (51); sequentially forming a second semiconductor layer (60) and a second metal layer (70); Completely remove the first adhesive layer module (51), expose the first semiconductor layer (40) corresponding to the first adhesive layer module (51), and retain the second adhesive layer module (52) of partial thickness as a buffer module (54) for patterning the second semiconductor layer (60) and the second metal layer (70); Etching and patterning the first semiconductor layer (40), forming a first channel (80) in contact with the gate insulating layer (30), cleaning the buffer module (54) at the same time, adjacent to the A second channel (90) in contact with the first semiconductor layer (40) is formed between the second metal layer (70) corresponding to the opening (53) and the second semiconductor layer (60). 2. The method for preparing an array substrate according to claim 1, characterized in that, after exposing and developing the photoresist layer (50) through a mask (100), further comprising the steps of: Plasma bombardment, so that the first semiconductor layer (40) sputters inorganic particles outwards, forming discontinuities on the surfaces of the first glue layer module (51) and the second glue layer module (52) The cover layer(1); Etching the mask layer (1) to perform texturing treatment on the mask layer (1), forming a stripping cavity in contact with the first glue layer module (51) and the second glue layer module (52) (2); sequentially forming a second semiconductor layer (60) and a second metal layer (70); So that the stripping liquid is immersed in the stripping chamber (2) to contact with the first glue line module (51) and the second glue line module (52), to completely remove the first glue line module (51) , and retain part of the thickness of the second adhesive layer module (52) as the buffer module (54), so as to pattern the second semiconductor layer (60) and the second metal layer (70). 3. The method for preparing an array substrate according to claim 2, characterized in that, etching the mask layer (1) to texture the mask layer (1), wherein the mask layer (1) ) after etching, a plurality of support pillars (3) are formed on the surface of the first glue layer module (51) and the surface of the second glue layer module (52), and between adjacent support pillars (3) The stripping chamber (2) is provided. 4. The method for preparing an array substrate according to claim 3, wherein the thickness of the mask layer (1) is

The height of the support column (3) is

The range of the maximum outer diameter of the support column (3) is

5. The method for preparing an array substrate as claimed in claim 2, wherein the stripping solution is a mixed solution comprising amine basic organic matter and a polar organic solvent, and the processing time for stripping by using the stripping solution is 1S-1200S. 6. The method for preparing the array substrate according to claim 1, wherein the photoresist layer (50) is exposed and developed through a mask (100), wherein the mask (100) is In the semi-transparent mask, in the projection plane perpendicular to the substrate (10), the first adhesive layer module (51) corresponds to the secondary light-transmitting area of the mask (100), and the first The two glue layer modules (52) correspond one-to-one to the full shielding areas of the mask (100), and the openings (53) correspond to the full light transmission areas of the mask (100). 7. The method for preparing an array substrate according to claim 6, wherein the thickness of the first adhesive layer module (51) is D1, and the thickness of the second adhesive layer module (52) is D2, wherein ,

and

8. The method for preparing an array substrate according to claim 1, wherein the thickness of the buffer module (54) is D3, and

9. An array substrate, characterized in that, comprising: A device structure prepared by the method for preparing an array substrate according to any one of claims 1-8; A passivation layer and a pixel electrode layer are sequentially formed on the device structure. 10. A display panel, characterized in that it comprises: The array substrate of claim 9; The color filter substrate is arranged in a box with the array substrate; The liquid crystal layer is arranged between the array substrate and the color filter substrate.

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