CN115533733B - Precise control method for polishing thickness of silicon wafer for integrated circuit - Google Patents
Precise control method for polishing thickness of silicon wafer for integrated circuit Download PDFInfo
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- CN115533733B CN115533733B CN202110723046.6A CN202110723046A CN115533733B CN 115533733 B CN115533733 B CN 115533733B CN 202110723046 A CN202110723046 A CN 202110723046A CN 115533733 B CN115533733 B CN 115533733B
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- 238000005498 polishing Methods 0.000 title claims abstract description 75
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 36
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 36
- 239000010703 silicon Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 23
- 235000012431 wafers Nutrition 0.000 claims abstract description 100
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 59
- 239000013072 incoming material Substances 0.000 claims abstract description 40
- 239000000126 substance Substances 0.000 claims abstract description 18
- 238000005260 corrosion Methods 0.000 claims abstract description 8
- 230000007797 corrosion Effects 0.000 claims abstract description 8
- 238000007517 polishing process Methods 0.000 claims abstract description 8
- 230000004913 activation Effects 0.000 claims description 2
- 238000003486 chemical etching Methods 0.000 claims 1
- 230000007423 decrease Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000008204 material by function Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/005—Control means for lapping machines or devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/005—Control means for lapping machines or devices
- B24B37/013—Devices or means for detecting lapping completion
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/005—Control means for lapping machines or devices
- B24B37/015—Temperature control
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- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
A precise control method of the chemical mechanical polishing thickness of a silicon wafer for an integrated circuit comprises the following steps: according to the incoming material thickness difference extreme value of the monocrystalline silicon wafers required by the internal control standard, determining the incoming material thickness difference extreme value maximum value of the same group of polished monocrystalline silicon wafers; continuously adjusting polishing pressure in the polishing process through a pressure calculation equation; continuously adjusting the polishing temperature in the polishing process through a temperature calculation equation; when the extreme value of the incoming material thickness difference of the same group of polished monocrystalline silicon wafers is smaller than the extreme value of the incoming material thickness difference of the monocrystalline silicon wafers required by the internal control standard, a constant pressure minimum value and a constant temperature minimum value which meet the condition that the mechanical grinding polishing removal speed and the chemical corrosion polishing removal speed are close are selected for polishing until the target value of the thickness of the polished monocrystalline silicon wafers required by customers is reached. The method has wide thickness range of the incoming material, the thickness of the produced polished silicon wafer can be controlled within the scope of the Spec requirement of customers, the thickness uniformity is obviously improved, and the polishing time is greatly shortened.
Description
Technical Field
The invention relates to the technical field of silicon wafer production for integrated circuits, in particular to a method for precisely controlling the polishing thickness of a silicon wafer for integrated circuits.
Background
Semiconductor silicon materials are the main functional materials in the electronic information industry, especially in the integrated circuit industry. With the increasing diameter of silicon wafers and the decreasing feature sizes of integrated circuits, the method has higher technical requirements on the overall performance of monocrystalline silicon wafers, wherein the thickness consistency of monocrystalline silicon wafers is a key technical index. In the monocrystalline silicon wafer processing technology, double-sided chemical mechanical polishing processing is one of the most effective technical means for processing the ultra-smooth surface of a silicon wafer, and is widely focused and paid attention to the ultra-precise processing research field and the production and processing enterprises of semiconductor silicon materials. The total material removal amount of the double-sided chemical mechanical polishing of the monocrystalline silicon wafer is the sum of the chemical action removal amount, the mechanical action removal amount and the material removal amount generated under the mutual promotion of the chemical action removal amount and the mechanical action removal amount, and the polishing pressure and the polishing temperature have obvious influence on the silicon wafer removal rate. In the conventional chemical mechanical polishing process, constant polishing pressure and polishing temperature are mostly adopted, so that the mechanical polishing speed and the chemical corrosion speed are ensured to be basically consistent. The polishing pressure and the polishing temperature in the polishing process are constant values, so that the removal rate of the silicon wafer material tends to be single, but the thickness of each monocrystalline silicon wafer is different in the same polishing disc, when the thickness difference of each monocrystalline silicon wafer exceeds a certain value, the polishing deviation phenomenon can occur, and various quality problems of influencing the consistency of products, such as non-fit local flatness of the polished monocrystalline silicon wafer, poor consistency of the thickness and the like, occur. In order to solve the problem, the method has high requirements on the thickness range of the incoming material polished by the same batch of silicon wafers, and is usually controlled within 2 mu m, a lot of time is required to be consumed in the stage of classifying the thickness of the incoming material before polishing, the overall polishing efficiency is low, and the method is a productivity bottleneck in the whole silicon wafer manufacturing process. The small-batch products cannot be processed, the productivity is seriously affected, and the popularization of the products in the sample delivery authentication process is particularly affected.
In order to solve the technical problems, the invention provides the accurate control method for the polishing thickness of the silicon wafer for the integrated circuit, which is used for controlling the thickness by continuously adjusting the polishing pressure and the polishing temperature in the polishing process according to the removal amount change of the material of the monocrystalline silicon wafer in the chemical mechanical polishing process, improving the removal rate of the silicon wafer with larger thickness, reducing the removal rate of the silicon wafer with smaller thickness, ensuring the consistency of the thickness of the polished silicon wafer, shortening the polishing time and improving the overall polishing efficiency.
Disclosure of Invention
In order to meet the above requirements, the present invention provides a method for precisely controlling the chemical mechanical polishing thickness of a silicon wafer for an integrated circuit, comprising the following steps:
Firstly, determining the incoming material thickness limit difference value Diff spec of the same group of polished monocrystalline silicon wafers according to the technical requirement of an internal control standard on the monocrystalline silicon wafers, wherein the application range Diff spec =1-2 mu m;
Secondly, determining the feed thickness limit difference Diff wafer of the same group of polished monocrystalline silicon wafers according to the empirical equation (1),
Diffwafer＝Dmax-Dmin (1)
Wherein D max is the maximum value of the feed thickness of the same group of polished monocrystalline silicon wafers, and D min is the minimum value of the feed thickness of the same group of polished monocrystalline silicon wafers;
The appropriate range of Diff wafer corresponds to empirical equation (2):
Diffspec≤Diffwafer≤1.5Diffspec (2)
when Diff wafer＝1.5Diffspec, the maximum value of the feed thickness limit of the same group of polished monocrystalline silicon wafers is determined and is recorded as: diff wafer,max;
thirdly, measuring and calculating the average value of the thickness of the incoming materials of the same group of polished monocrystalline silicon wafers, marking as D 0, and determining a target value of the thickness of the polished monocrystalline silicon wafers according to the requirement of an internal control standard, marking as D spec; the pressure P during polishing is determined according to empirical equation (3):
Wherein: k is a pressure coefficient, and the value in the method is as follows: k=1.71; p min is the pressure minimum.
It can be seen that, according to the empirical equation (3), the pressure is large just when polishing is started, and the polishing pressure P decreases as the thickness of the single crystal silicon wafer decreases as polishing proceeds. According to the mechanical polishing principle, the speed of grinding and removing the silicon wafers with larger thickness is larger than that of monocrystalline silicon wafers with lower thickness by larger pressure, so that the thickness extreme value of the same group of polished monocrystalline silicon wafers can be effectively reduced, and the thickness uniformity and consistency are improved.
Fourth, the temperature during polishing is determined according to empirical equation (4):
Wherein: l is a temperature coefficient, and the value in the method is as follows: l=0.29; t min is the minimum temperature.
It can be seen that, according to equation (4), the temperature is higher just before polishing starts. As polishing proceeds, the polishing temperature T decreases as the thickness of the single crystal silicon wafer decreases. According to the chemical corrosion principle, the silicon wafer with higher temperature and larger thickness has high polishing pressure and strong strain, so that the removal speed is far higher than that of the monocrystalline silicon wafer with lower thickness, the thickness tolerance value of the same group of polished monocrystalline silicon wafers is further effectively reduced, and the thickness uniformity and consistency are improved.
In the technology of the invention, under the conditions of a pressure minimum value P min and a temperature minimum value T min, the mechanical grinding polishing removal speed and the chemical corrosion polishing removal speed are required to be close, namely, the chemical corrosion polishing removal speed accords with the equation (5):
Wherein K is 11.3, ea is the activation energy of corrosion reaction; r is molar gas constant;
When Diff wafer<Diffspec, polishing was performed using constant pressure minimum P min and temperature minimum T min conditions.
The thickness of the polished silicon wafer produced by the method can be controlled within the scope of the Spec requirement of clients, the thickness uniformity is obviously improved, and the polishing time is greatly shortened.
Drawings
FIG. 1 is a graph showing the polishing pressure as a function of the amount of polishing removal.
FIG. 2 is a graph showing a polishing temperature as a function of a polishing removal amount.
Detailed Description
Example 1
Polishing a 300mm silicon wafer, wherein the incoming material thickness difference value of the same group of polished monocrystalline silicon wafers is 2.0 mu m according to the technical requirements of internal control standards on the monocrystalline silicon wafers; selecting the same group of polished monocrystalline silicon wafers, wherein the maximum value of the thickness of the incoming materials is 789.5 mu m, the minimum value of the thickness of the incoming materials is 786.5 mu m, the average value of the incoming materials is 787.48 mu m, and calculating the thickness difference value of the incoming materials to be 3.0 mu m according to the equation (1); satisfying equation (2), determining the polishing pressure to be 12.86kpa according to equation (3), and continuously adjusting according to equation (3); according to equation (4), the initial polishing temperature value is determined to be 24.64 ℃, and is continuously adjusted according to equation (4). The 45 pieces of 300mm silicon wafers are polished by the process, the thickness extreme value of the polished monocrystalline silicon wafers is 1.0 mu m, the polishing duration is 230 minutes, and the Spec requirement of customers is met.
Comparative example 1
Polishing a 300mm silicon wafer, wherein the incoming material thickness difference value of the same group of polished monocrystalline silicon wafers is 2.0 mu m according to the technical requirements of internal control standards on the monocrystalline silicon wafers; selecting the same group of polished monocrystalline silicon wafers, wherein the maximum value of the thickness of the incoming materials is 788.5 mu m, the minimum value of the thickness of the incoming materials is 786.5 mu m, the average value of the incoming materials is 787.48 mu m, and calculating the thickness difference value of the incoming materials to be 2.0 mu m according to the equation (1); 45 300mm silicon wafers are polished under constant pressure and temperature, the thickness difference value of the polished monocrystalline silicon wafers is 1.0 mu m, the polishing time is 278 minutes similar to the result of the example 1, the polishing time is longer than the time of the example 1, and the Spec requirement of customers is met.
Example 2
Polishing a 300mm silicon wafer, wherein the incoming material thickness difference value of the same group of polished monocrystalline silicon wafers is 1.0 mu m according to the technical requirements of internal control standards on the monocrystalline silicon wafers; selecting the same group of polished monocrystalline silicon wafers, wherein the maximum value of the thickness of the incoming materials is 780.3 mu m, the minimum value of the thickness of the incoming materials is 778.8 mu m, the average value of the incoming materials is 779.52 mu m, and calculating the thickness difference value of the incoming materials according to the equation (1) to be 1.5 mu m; satisfying equation (2), determining the polishing pressure to be 6.62kpa according to equation (3), and continuously adjusting according to equation (3); according to equation (4), the initial polishing temperature value is determined to be 23.60 ℃, and is continuously adjusted according to equation (4). The 45 pieces of 300mm silicon wafers are polished by the process, the thickness extreme value of the polished monocrystalline silicon wafers is 0.7 mu m, and the Spec requirement of customers is met.
Example 3
Polishing a 300mm silicon wafer, wherein the incoming material thickness difference value of the same group of polished monocrystalline silicon wafers is 1.2 mu m according to the technical requirements of internal control standards on the monocrystalline silicon wafers; selecting the same group of polished monocrystalline silicon wafers, wherein the maximum value of the thickness of the incoming materials is 783.6 mu m, the minimum value is 781.8 mu m, the average value is 782.02 mu m, and the thickness difference value is 1.8 mu m according to the equation (1); satisfying equation (2), determining the polishing pressure to be 7.50kpa according to equation (3), and continuously adjusting according to equation (3); according to equation (4), the initial polishing temperature value is determined to be 23.75 ℃, and is continuously adjusted according to equation (4). The 45 pieces of 300mm silicon wafers are polished by the process, the thickness extreme value of the polished monocrystalline silicon wafers is 0.9 mu m, and the Spec requirement of customers is met.
Example 4
Polishing a 300mm silicon wafer, wherein the incoming material thickness difference value of the same group of polished monocrystalline silicon wafers is 1.2 mu m according to the technical requirements of internal control standards on the monocrystalline silicon wafers; selecting the same group of polished monocrystalline silicon wafers, wherein the maximum value of the thickness of the incoming materials is 782.7 mu m, the minimum value of the thickness of the incoming materials is 781.9 mu m, the average value of the incoming materials is 782.28 mu m, and the thickness difference value of the incoming materials is 0.8 mu m according to the equation (1); equation (2) is not satisfied, a pressure minimum and a temperature minimum are calculated according to equation (5), and polishing is performed with a constant pressure minimum and temperature minimum. The 45 pieces of 300mm silicon wafers are polished by the process, the thickness extreme value of the polished monocrystalline silicon wafers is 1.0 mu m, and the Spec requirement of customers is met.
Claims (4)
1. An accurate control method of silicon wafer chemical mechanical polishing thickness for an integrated circuit comprises the steps of determining the maximum value of the incoming material thickness difference extreme value of a same group of polished monocrystalline silicon wafers according to the incoming material thickness difference extreme value of the monocrystalline silicon wafers required by an internal control standard; continuously adjusting polishing pressure in the polishing process through a pressure calculation equation; continuously adjusting the polishing temperature in the polishing process through a temperature calculation equation; when the extreme value of the incoming material thickness difference of the same group of polished monocrystalline silicon wafers is smaller than the extreme value of the incoming material thickness of the monocrystalline silicon wafers required by the internal control standard, a constant pressure minimum value and a constant temperature minimum value which meet the condition that the mechanical grinding polishing removal speed and the chemical corrosion polishing removal speed are close are selected for polishing until the thickness target value of the polished monocrystalline silicon wafers required by customers is reached; the method is characterized by comprising the following steps of:
firstly, determining the incoming material thickness limit difference spec of the same group of polished monocrystalline silicon wafers required by an internal control standard;
In the second step, the difference of the incoming material thickness differences wafer of the same group of polished monocrystalline silicon wafers accords with the equation (1),
Diffwafer＝Dmax-Dmin (1)
Wherein D max is the maximum value of the feed thickness of the same group of polished monocrystalline silicon wafers, and D min is the minimum value of the feed thickness of the same group of polished monocrystalline silicon wafers;
The range of Diff wafer corresponds to equation (2):
Diffspec≤Diffwafer≤1.5Diffspec (2)
Third, the pressure P during polishing conforms to equation (3):
Wherein: k is a pressure coefficient, and the value is as follows: k=1.71; p min is the pressure minimum; d 0 is the average value of the thickness of the incoming materials of the same group of polished monocrystalline silicon pieces; d spec is an internal control standard requirement to determine a thickness target value of the polished silicon wafer;
Fourth, the temperature during polishing conforms to equation (4):
wherein: l is a temperature coefficient, and the value is as follows: l=0.29; t min is the minimum temperature; d 0 is the average value of the thickness of the incoming materials of the same group of polished monocrystalline silicon pieces; d spec is the internal control standard requirement to determine the thickness target value of the polished silicon wafer.
2. The method for precisely controlling the chemical mechanical polishing thickness of a silicon wafer for an integrated circuit according to claim 1, wherein the mechanical lapping removal rate and the chemical etching removal rate are close to each other under the conditions of a pressure minimum value P min and a temperature minimum value T min, namely, satisfy the following equation (5):
wherein K is 11.3, ea is the activation energy of corrosion reaction; r is molar gas constant.
3. The method of precisely controlling the chemical mechanical polishing thickness of a silicon wafer for an integrated circuit according to claim 1, wherein the polishing is performed using constant pressure minimum P min and temperature minimum T min conditions when Diff wafer<Diffspec is used.
4. The method for precisely controlling the chemical mechanical polishing thickness of a silicon wafer for an integrated circuit according to claim 1, wherein the range of the incoming material thickness limit difference spec of the same group of polished monocrystalline silicon wafers required by the internal control standard is as follows: diff spec = 1-2 μm.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105252406A (en) * | 2015-09-10 | 2016-01-20 | 上海超硅半导体有限公司 | Polishing method for silicon wafer |
| CN107336126A (en) * | 2017-08-31 | 2017-11-10 | 清华大学 | Polish pressure control method, device and the polissoir of polissoir |
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| JP2001501545A (en) * | 1996-10-04 | 2001-02-06 | オブシディアン，インコーポレイテッド | Method and system for controlling chemical mechanical polishing thickness removal |
| TW430594B (en) * | 1999-12-29 | 2001-04-21 | United Microelectronics Corp | Method for controlling polishing time in CMP process |
| JP2005011977A (en) * | 2003-06-18 | 2005-01-13 | Ebara Corp | Device and method for substrate polishing |
| JP2005342841A (en) * | 2004-06-03 | 2005-12-15 | Renesas Technology Corp | Polishing device |
| WO2006077994A1 (en) * | 2005-01-21 | 2006-07-27 | Ebara Corporation | Substrate polishing method and apparatus |
| JP2008258510A (en) * | 2007-04-07 | 2008-10-23 | Tokyo Seimitsu Co Ltd | Polish requirement management device for cmp device and method of managing polish requirement |
| JP6196858B2 (en) * | 2012-09-24 | 2017-09-13 | 株式会社荏原製作所 | Polishing method and polishing apparatus |
| JP6287778B2 (en) * | 2014-11-21 | 2018-03-07 | 信越半導体株式会社 | Epitaxial wafer manufacturing method |
| CN110193775B (en) * | 2019-03-12 | 2021-09-17 | 上海新昇半导体科技有限公司 | Chemical mechanical polishing method and chemical polishing system |
| CN111863613A (en) * | 2019-04-08 | 2020-10-30 | 清华大学 | A chemical mechanical polishing method, device, system and control equipment |
| CN111203792B (en) * | 2020-01-13 | 2022-04-15 | 天津中环领先材料技术有限公司 | Method for controlling thickness of heavily doped product after polishing |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105252406A (en) * | 2015-09-10 | 2016-01-20 | 上海超硅半导体有限公司 | Polishing method for silicon wafer |
| CN107336126A (en) * | 2017-08-31 | 2017-11-10 | 清华大学 | Polish pressure control method, device and the polissoir of polissoir |
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