CN115458515B - A power MOSFET module and production method - Google Patents
A power MOSFET module and production method Download PDFInfo
- Publication number
- CN115458515B CN115458515B CN202211300532.8A CN202211300532A CN115458515B CN 115458515 B CN115458515 B CN 115458515B CN 202211300532 A CN202211300532 A CN 202211300532A CN 115458515 B CN115458515 B CN 115458515B
- Authority
- CN
- China
- Prior art keywords
- power mosfet
- wafer
- chip
- mosfet module
- copper substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
- H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
- H01L2021/60097—Applying energy, e.g. for the soldering or alloying process
- H01L2021/60135—Applying energy, e.g. for the soldering or alloying process using convection, e.g. reflow oven
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a power MOSFET module and a production method thereof, and relates to the technical field of semiconductors. The semiconductor packaging structure comprises a DBC plate, wherein a plurality of copper substrates are arranged on the DBC plate, wafers are arranged on the copper substrates, and the DBC plate, the copper substrates and the wafers are embedded in a plastic package body. According to the invention, the wafer is fixed in the groove of the copper substrate and then welded and fixed with the DBC plate, so that the power MOSFET module can be produced by adopting equipment with lower cost in production, and the copper substrate can be used as additional heat capacity, so that the thermal shock resistance of the power MOSFET module is effectively enhanced, and the applicability of the power MOSFET module is wider. According to the invention, the wafer is fixed on the copper substrate, and then BIN is separated in a test mode, so that an expensive wafer tester is replaced by a cheaper common chip sorter, the production cost can be effectively saved, and meanwhile, after the wafer is fixed on the copper substrate, SMT equipment for producing MOS single tubes can be adopted.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a power MOSFET module and a production method thereof.
Background
The power MOSFET module is almost used in all electronic manufacturing industries including notebooks, PCs, servers, displays and various peripheral devices in the computer field, mobile phones, telephones and other various terminal and local side equipment in the network communication field, traditional black and white household appliances and various digital products in the consumer electronics field, industrial PCs, various instruments and meters, various control equipment and the like in the industrial control field.
When the existing power MOSFET module is manufactured, because of the fragile characteristic of the wafer, the wafer cannot be braided and packaged, namely, a chip mounter with braiding feeding cannot be adopted for chip mounting, a special chip mounter is required to be adopted for chip mounting operation, the chip mounter is used for directly bonding the wafer on a DBC plate with the brushed solder paste, then welding and fixing are carried out through vacuum reflow soldering, and then plastic packaging, rib cutting, testing and packaging are carried out, so that the power MOSFET module is manufactured.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a power MOSFET module with good thermal shock resistance.
In order to achieve the aim of the invention, the invention adopts the following technical scheme:
A power MOSFET module is provided, which comprises a DBC plate, wherein a plurality of copper substrates are arranged on the DBC plate, wafers are arranged on the copper substrates, and the DBC plate, the copper substrates and the wafers are embedded in a plastic package body.
Further, a groove is formed in the copper substrate, the wafer is welded to the bottom of the groove through solder paste, and the wafer does not protrude from the surface of the copper substrate.
The wafer is welded in the groove, so that the wafer is embedded in the copper substrate, the surface of the wafer, which does not protrude out of the copper substrate, can enable the wafer and the copper substrate to be subjected to braid packaging, and the wafer cannot be scratched during braid packaging.
Further, the wafer is located at the very center of the groove, and a uniform gap is arranged between the wafer and the groove.
In order to overcome the defects in the prior art, the invention provides a production method of a power MOSFET module with lower production cost.
In order to achieve the aim of the invention, the invention adopts the following technical scheme:
a method of producing a power MOSFET module comprising the steps of:
S1, mounting a copper substrate in a carrier and then placing the copper substrate in a chip mounter;
S2, fixing a wafer on a copper substrate through a DB thermomotor to obtain a chip material;
S3, braiding and packaging the chip material to obtain a material belt;
s4, using a chip mounter to paste chip materials on the material belt on a DBC plate with tin paste brushed;
s5, welding the chip material on the DBC board by using vacuum reflow soldering;
S6, electrically connecting the chip materials by using a wire bonding machine to obtain a power MOSFET module chip;
And S7, sequentially performing plastic packaging, rib cutting, testing and packaging on the power MOSFET module chip to obtain the power MOSFET module.
Further, between step S2 and step S3, there is a step of:
And S2.5, testing and BIN-separating the chip materials by using a chip sorting machine, and separating the chip materials with the same BIN onto the same material belt.
The beneficial effects of the invention are as follows:
1. According to the invention, the wafer is fixed in the groove of the copper substrate and then welded and fixed with the DBC plate, so that the power MOSFET module can be produced by adopting equipment with lower cost in production, and the copper substrate can be used as additional heat capacity, so that the thermal shock resistance of the power MOSFET module is effectively enhanced, and the applicability of the power MOSFET module is wider.
2. The wafer is fixed on the copper substrate, and then BIN is separated in a testing mode, so that an expensive wafer testing machine is replaced by a cheaper common chip sorting machine, the production cost can be effectively saved, meanwhile, after the wafer is fixed on the copper substrate, SMT equipment for producing MOS single tubes can be adopted, compared with a special die bonder, the chip mounter and the SMT equipment have the advantages of lower cost and wider purchase channel, moreover, the power MOSFET module can adopt the same production line with the MOS single tubes, a factory can flexibly receive order production, the operation cost of the factory is reduced, and meanwhile, when the factory wants to convert, the production conversion cost of the factory is reduced, so that the factory is converted from a production MOS tube part mode to a production power MOSFET module finished product mode more quickly, and the technical blockage of equipment abroad is avoided.
Drawings
FIG. 1 is a schematic perspective view of a chip material;
FIG. 2 is a schematic diagram of a front center cross-section of a chip material;
fig. 3 is a flow chart of a method for producing the power MOSFET module.
Wherein, 1, copper substrate, 2, wafer, 3, groove, 4, soldering tin layer.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and all the inventions which make use of the inventive concept are protected by the spirit and scope of the present invention as defined and defined in the appended claims to those skilled in the art.
As shown in fig. 1-2, a power MOSFET module includes a DBC board, a plurality of copper substrates 1 are disposed on the DBC board, a wafer 2 is disposed on each of the plurality of copper substrates 1, and the DBC board, the copper substrates 1 and the wafer 2 are all embedded in a plastic package. The copper substrate 1 is provided with a groove 3, the wafer 2 is welded at the bottom of the groove 3 through solder paste, and the wafer 2 does not protrude from the surface of the copper substrate 1. The wafer 2 is positioned at the center of the groove 3, and a uniform gap is arranged between the wafer 2 and the groove 3.
As shown in fig. 3, a method for producing a power MOSFET module includes the steps of:
s1, loading a copper substrate 1 into a carrier and then placing the carrier into a chip mounter;
S2, fixing a wafer 2 on a copper substrate 1 through a DB thermomotor to obtain a chip material;
The DB thermo-engine adopts the device with model ASM SD832, i.e. Die Bond thermo-engine, which is a commonly used device in semiconductor packaging factories, and has lower device cost and maintenance cost compared with Die bonders.
And S2.5, testing and BIN-separating the chip materials by using a chip sorting machine, and separating the chip materials with the same BIN onto the same material belt.
S3, braiding and packaging the chip material to obtain a material belt;
s4, using a chip mounter to paste chip materials on the material belt on a DBC plate with tin paste brushed;
s5, welding the chip material on the DBC board by using vacuum reflow soldering;
S6, electrically connecting the chip materials by using a wire bonding machine to obtain a power MOSFET module chip;
And S7, sequentially performing plastic packaging, rib cutting, testing and packaging on the power MOSFET module chip to obtain the power MOSFET module.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202211300532.8A CN115458515B (en) | 2022-10-24 | 2022-10-24 | A power MOSFET module and production method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202211300532.8A CN115458515B (en) | 2022-10-24 | 2022-10-24 | A power MOSFET module and production method |
Publications (2)
Publication Number | Publication Date |
---|---|
CN115458515A CN115458515A (en) | 2022-12-09 |
CN115458515B true CN115458515B (en) | 2025-02-11 |
Family
ID=84311150
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202211300532.8A Active CN115458515B (en) | 2022-10-24 | 2022-10-24 | A power MOSFET module and production method |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN115458515B (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN210325791U (en) * | 2019-10-25 | 2020-04-14 | 成都赛力康电气有限公司 | Power MOS module structure convenient for heat dissipation |
CN114843196A (en) * | 2022-03-02 | 2022-08-02 | 南通格普微电子有限公司 | Electrode conductive pillar bonded wafer fabrication method |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5895974A (en) * | 1998-04-06 | 1999-04-20 | Delco Electronics Corp. | Durable substrate subassembly for transistor switch module |
FR2814279B1 (en) * | 2000-09-15 | 2003-02-28 | Alstom | SUBSTRATE FOR ELECTRONIC CIRCUIT AND ELECTRONIC MODULE USING SUCH SUBSTRATE |
CN100474539C (en) * | 2002-03-12 | 2009-04-01 | 费查尔德半导体有限公司 | Wafer-level coated copper stud bumps |
CN103000536B (en) * | 2012-12-07 | 2016-01-20 | 天水华天微电子股份有限公司 | A kind of preparation technology of Intelligent Power Module |
CN206497883U (en) * | 2017-02-27 | 2017-09-15 | 西安后羿半导体科技有限公司 | High-power MOS FET's is fanned out to shape encapsulating structure |
CN110690120B (en) * | 2019-09-27 | 2021-08-03 | 天津大学 | Sintered package MOS chip bidirectional switch electronic module and manufacturing method thereof |
US12113038B2 (en) * | 2020-01-03 | 2024-10-08 | Qualcomm Incorporated | Thermal compression flip chip bump for high performance and fine pitch |
CN112038245B (en) * | 2020-07-22 | 2022-11-18 | 无锡利普思半导体有限公司 | Connection process of internal binding line of power module |
CN216849871U (en) * | 2021-11-25 | 2022-06-28 | 苏州万达电子科技有限公司 | Wafer loading substrate of semiconductor power MOS tube |
CN114373689A (en) * | 2021-12-30 | 2022-04-19 | 黄山市阊华电子有限责任公司 | A kind of preparation method of high power module |
-
2022
- 2022-10-24 CN CN202211300532.8A patent/CN115458515B/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN210325791U (en) * | 2019-10-25 | 2020-04-14 | 成都赛力康电气有限公司 | Power MOS module structure convenient for heat dissipation |
CN114843196A (en) * | 2022-03-02 | 2022-08-02 | 南通格普微电子有限公司 | Electrode conductive pillar bonded wafer fabrication method |
Also Published As
Publication number | Publication date |
---|---|
CN115458515A (en) | 2022-12-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7279784B2 (en) | Semiconductor package | |
CN100499052C (en) | Planar grid array packaged device and method of forming same | |
CN100380614C (en) | Partially patterned lead frames and methods of making and using the same in semiconductor packaging | |
TWI407533B (en) | Integrated circuit package system with die on base package | |
CN103474406A (en) | Copper-free flat packaging piece of AAQFN frame product and manufacturing process thereof | |
KR20130046117A (en) | Semiconductor package and method for manufacturing the same and semiconductor package module having the same | |
CN102163591A (en) | Spherical grating array IC (integrated circuit) chip packaging part and production method thereof | |
CN102315135B (en) | Chip package and manufacturing process thereof | |
US20080150128A1 (en) | Heat dissipating chip structure and fabrication method thereof and package having the same | |
CN115458515B (en) | A power MOSFET module and production method | |
CN102222658A (en) | Multi-circle arranged IC (integrated circuit) chip packaging member and producing method thereof | |
CN206059374U (en) | High-power patch components and their processing tools | |
US20090200362A1 (en) | Method of manufacturing a semiconductor package | |
CN114783886B (en) | A method for preparing an intelligent power module and a packaging module prepared therefrom | |
CN110164831A (en) | Conducive to the high-current semiconductor power device and its manufacturing method of welding | |
CN214588813U (en) | Packaging structure of reverse-bending internal insulation product | |
KR20080074468A (en) | Surface Mounting Method of Semiconductor Chip Using Ultrasonic Wave | |
CN100378992C (en) | Semiconductor package and manufacturing method thereof | |
CN112775509B (en) | Method for reducing voidage during welding of TO packaged components | |
CN213212147U (en) | Semiconductor device structure | |
CN1332443C (en) | Leadframe for semiconductor device, method for manufacturing semiconductor device using the same, semiconductor device using the same, and electronic equipment | |
CN214477424U (en) | Novel DFN packaged semiconductor | |
JP3191684B2 (en) | Method for manufacturing semiconductor element having electroplating lead | |
CN220439614U (en) | Laminated packaging module | |
CN218647932U (en) | Power semiconductor module of ultrasonic welding lead frame |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |