CN115456182B - Device for generating qubit control signal and quantum computer control system - Google Patents
Device for generating qubit control signal and quantum computer control system Download PDFInfo
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Abstract
The invention discloses a device for generating a quantum bit control signal and a quantum computer control system. The device comprises: the sine and cosine signal generator is used for respectively outputting sine signals and cosine signals with the same frequency of a preset path number in parallel under the action of the working clock; the envelope generator is used for determining the envelope of the target control signal from a pre-stored corresponding table according to the target single-bit revolving door, respectively outputting an envelope in-phase component and an envelope quadrature component of a preset number of paths in parallel under the action of the working clock, and the corresponding table stores the control signals corresponding to different single-bit revolving doors; the signal mixer is used for multiplying the sine signals with the preset paths by the envelope in-phase component and the cosine signals with the preset paths by the envelope quadrature component under the action of the working clock, and adding the two multiplication results to obtain the target control signal, so that the phase difference of the target control signal and the local oscillation signal is consistent. The invention can automatically compensate the phase of the control signal when realizing the same single-bit revolving door.
Description
Technical Field
The present invention relates to the field of quantum computing, and in particular, to a device for generating a qubit manipulation signal and a quantum computer control system.
Background
The single bit rotation gate operation of Qubit is realized by applying a control signal to the Qubit, the phase of the control signal determines the angle of the rotation axis of the Qubit state vector in the bloch sphere on the XY plane, and the amplitude of the control signal determines the rotation angle of the state vector around the rotation axis. Since the signal acting on the qubit is a radio frequency signal (RF) and the initially generated steering signal is an intermediate frequency signal (IF), it is necessary to mix the intermediate frequency steering signal with a local oscillator signal (LO) to obtain the radio frequency steering signal.
However, the present inventors have found in long-term studies that, when a plurality of identical single-bit rotary gates are continuously implemented, the intermediate frequency control signal and the local oscillation signal of the front and rear single-bit rotary gates are not identical in phase difference, resulting in the difference between the front and rear single-bit rotary gates. In order to obtain the same single-bit rotary gate, it is known to change the phase of the intermediate frequency control signal of the following single-bit rotary gate. However, the implementation of the same single-bit rotation gate generates different control signals, which makes it difficult to control the qubits in units of single-bit rotation gates.
Disclosure of Invention
The invention aims to provide a device for generating a quantum bit control signal and a quantum computer control system, which are used for solving the problem that different control signals are required to be generated when the same single-bit revolving door is realized in the prior art, and can automatically compensate the phase of the control signal when the same single-bit revolving door is realized, so that the quantum bit is controlled by taking the single-bit revolving door as a unit.
In order to solve the above technical problems, the present invention provides a device for generating a qubit manipulation signal, where the manipulation signal and a local oscillation signal are mixed to change from an intermediate frequency to a radio frequency and then act on a qubit to implement a single bit revolving gate, and the device comprises:
the sine and cosine signal generator is used for respectively outputting sine signals and cosine signals with the same frequency of a preset path number in parallel under the action of the working clock;
The envelope generator is used for determining the envelope of the target control signal from a pre-stored corresponding table according to the target single-bit revolving door, and respectively outputting an in-phase envelope component and an orthogonal envelope component of a preset number of paths in parallel under the action of the working clock, wherein the corresponding table stores control signals corresponding to different single-bit revolving doors;
And the signal mixer is used for multiplying the sine signals with the preset paths by the envelope in-phase component and the cosine signals with the preset paths by the envelope quadrature component under the action of the working clock, and adding the two multiplication results to obtain the target control signal, so that the phase difference of the target control signal and the local oscillation signal is consistent.
Preferably, the parallel-serial conversion module is further comprised:
The signal mixer is also used for dividing the target control signal into at least one path of parallel output;
The parallel-serial conversion module is used for converting at least one path of target control signals which are output in parallel into serial signals under the action of a serial clock, wherein the frequency of the serial clock is not lower than that of the working clock.
Preferably, the sine and cosine signal generator includes an address acquisition module and a memory, where the memory stores a first number of sine values and cosine values of a preset frequency:
the address acquisition module is used for sequentially acquiring table lookup addresses which are increased by a preset step length under the action of a working clock and sending the table lookup addresses into the memory;
the memory is configured to output a second number of current sine values and current cosine values for forming a sine signal and a cosine signal respectively in parallel each time a table lookup address is sent;
The second number is the preset number of paths, the phases of the sine value and the cosine value output each time are increased by a preset phase increment, the sine value and the cosine value output by two adjacent times are continuous in phase, and the preset phase increment is determined according to the preset frequency, the first number, the second number and the frequency of the working clock.
Preferably, the memory provides two identical lookup tables, the two lookup tables respectively store sine values and cosine values, the number of lookup address bits of the lookup table is a first number of bits a, the number of data bits of the lookup table is a second number of bits B, and the sine values and the cosine values of the second number with continuous phases correspond to the same lookup address, wherein the product of 2 A and the second number is equal to 2 B.
Preferably, the lookup table has a second number of sub-tables, each sub-table stores a number of sine values or cosine values of 2 B, the same data bit of each sub-table corresponds to the same lookup address, the sine values or cosine values stored in the same data bit are continuous in phase, and the phases of the sine values or cosine values stored in two adjacent data bits in the same sub-table differ by a second number of preset phase increment.
Preferably, the preset phase increment is:
Wherein N represents the first number, the value range is [1,2 B ], c represents the second number, f out represents the preset frequency, and f S represents the frequency of the working clock.
Preferably, the sinusoidal signal is:
The cosine signal is:
wherein n represents the value of the table lookup address, the range of the value is [0,2 A -1], a represents the amplitude, Representing the initial phase, and b representing the offset.
Preferably, the sine and cosine signal generator comprises an address acquisition module and a memory storing at least one quarter of the trigonometric function values of a period, wherein the number of the trigonometric function values of one period is a first number, and the number of the memory is a second number;
the address acquisition module is used for sequentially acquiring multiple paths of table lookup addresses under the action of a working clock, respectively sending the multiple paths of table lookup addresses into a second number of memories, wherein the table lookup addresses of two adjacent paths at the same time differ by a preset phase increment, and the table lookup addresses of two adjacent paths differ by a second number multiple of the preset phase increment;
The memory is configured to output a current sine value and a current cosine value when a table lookup address is sent in, and a sine signal and a cosine signal of preset frequency are formed respectively;
The second number is the preset number of paths, and the preset phase increment is determined according to the preset frequency, the first number, the second number and the frequency of the working clock.
Preferably, the trigonometric function value stored in the memory is a sine value of at least one quarter period, a cosine value of at least one quarter period, or a sine value and a cosine value of at least one quarter period.
Preferably, the memory is configured to check whether the current table lookup address stores a corresponding sine value or a corresponding cosine value when one table lookup address is sent, output the stored current sine value and current cosine value when the corresponding sine value or the corresponding cosine value is stored, respectively form a sine signal and a cosine signal of a preset frequency, calculate the corresponding sine value or the corresponding cosine value according to the periodicity of the sine value or the corresponding cosine value when the corresponding sine value or the corresponding cosine value is not stored, and output the calculated current sine value and the calculated current cosine value to respectively form the sine signal and the cosine signal of the preset frequency.
Preferably, the memory provides a lookup table storing a quarter-period sine value, and the number of lookup address bits of the lookup table is a first number of bits a, wherein 2 A is equal to the first number.
Preferably, the preset phase increment is:
Wherein N represents the first number, c represents the second number, f out represents the preset frequency, f S represents the frequency of the working clock, and Round () represents a rounding function.
Preferably, the sinusoidal signal is:
The cosine signal is:
Wherein n is the value of the lookup address, n is in the range of [0,2 A -1], a is the amplitude, Representing the initial phase, and b representing the offset.
Preferably, the current sine value of the memory output is:
The current cosine value output by the memory is:
Wherein m represents the value of the lookup address of the lookup table, and the value range is [0,2 A -1].
Preferably, the amplitude, the initial phase and the offset of the sine signal and the cosine signal are the same.
In order to solve the technical problems, the invention also provides a quantum computer control system, which comprises any one of the devices for generating the quantum bit control signals.
Preferably, the device further comprises a mixer, wherein the mixer is used for mixing the target control signal with a local oscillator signal, so that the target control signal is changed from an intermediate frequency to a radio frequency.
Preferably, the device further comprises a digital-to-analog converter, wherein the digital-to-analog converter is used for performing digital-to-analog conversion on the target manipulation signal before the target manipulation signal is mixed.
Compared with the prior art, the device for generating the quantum bit control signal provided by the invention is characterized in that sine signals and cosine signals with the same frequency of the preset path number are respectively output in parallel under the action of the working clock, the envelope of the target control signal is determined according to the target single-bit rotating gate, the envelope in-phase component and the envelope quadrature component of the preset path number are respectively output in parallel, the sine signals and the envelope in-phase component of the preset path number are multiplied, the cosine signals and the envelope quadrature component of the preset path number are multiplied, and the two multiplication results are added to obtain the target control signal, so that the phase difference of the target control signal and the local oscillation signal is consistent, the phase of the control signal can be automatically compensated when the same single-bit rotating gate is realized, quantum bits are controlled by taking the single-bit rotating gate as a unit, and the control signal stored in the corresponding table is not changed, so that the compiling and pre-storing of the control signal are facilitated, and the operation complexity of the quantum bits is simplified.
The quantum computer control system provided by the invention and the device for generating the quantum bit control signal belong to the same invention conception, so that the quantum computer control system has the same beneficial effects and is not repeated herein.
Drawings
Fig. 1 is a schematic structural diagram of an apparatus for generating a qubit manipulation signal according to a first embodiment of the present invention.
Fig. 2 is a schematic structural diagram of an apparatus for generating a qubit manipulation signal according to a second embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a sine-cosine signal generator of an apparatus for generating a qubit manipulation signal according to a third embodiment of the present invention.
Fig. 4 is a schematic diagram of a data structure of a lookup table provided by a memory of a sine and cosine signal generator according to a third embodiment.
Fig. 5 is a schematic diagram of a data structure of storing sine values in each sub-table of the lookup table in the third embodiment.
Fig. 6 is a schematic structural diagram of a sine-cosine signal generator of an apparatus for generating a qubit manipulation signal according to a fourth embodiment of the present invention.
Fig. 7 is a schematic diagram of a data structure of a lookup table provided by a memory of a sine and cosine signal generator according to a fourth embodiment.
Fig. 8 is a schematic structural diagram of a quantum computer control system according to a fifth embodiment of the present invention.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. Advantages and features of the invention will become more apparent from the following description and claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", etc., are based on the directions or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
Referring to fig. 1, a first embodiment of the present invention provides an apparatus for generating a qubit manipulation signal. The control signal and the local oscillation signal are mixed to be changed into radio frequency from intermediate frequency and then act on the quantum bit to realize the single-bit revolving gate. The apparatus of this embodiment comprises a sine and cosine signal generator 1, an envelope generator 2 and a signal mixer 3.
The sine and cosine signal generator 1 is used for respectively outputting sine signals and cosine signals with the same frequency of a preset number of paths in parallel under the action of a working clock. The clocks of each path of sine signals in the sine signals with the preset paths are working clocks, and the clocks of each path of cosine signals in the cosine signals with the preset paths are working clocks.
The envelope generator 2 is configured to determine an envelope of the target control signal from a pre-stored correspondence table according to the target single-bit rotation gate, and output an envelope in-phase component and an envelope quadrature component of a preset number of paths in parallel under the action of the working clock, where the correspondence table stores control signals corresponding to different single-bit rotation gates. The clocks of each path of envelope in-phase component in the envelope in-phase components of the preset path number are working clocks, and the clocks of each path of envelope quadrature component in the envelope quadrature components of the preset path number are working clocks. The table can store parameters of the control signal of the single-bit rotary door, which parameters form the control signal, from which parameters the envelope of the control signal can be determined. In this embodiment, the single bit rotator gate is preferably a single bit X gate or a single bit Y gate.
The signal mixer 3 is configured to multiply a sinusoidal signal with a preset number of paths by an envelope in-phase component and a cosine signal with a preset number of paths by an envelope quadrature component under the action of a working clock, and add the two multiplication results to obtain a target control signal, so that a phase difference between the target control signal and a local oscillator signal is consistent. The sine signals of the preset path number are multiplied by the envelope in-phase components of the preset path number, the cosine signals of the preset path number are multiplied by the envelope quadrature components of the preset path number, the conversion from the envelope to the wave packet is realized, the phase compensation of the control signals is realized by adding the two multiplication results, the phase difference of the target control signals and the phase difference of the local oscillation signals are consistent, and the same single-bit revolving door can be continuously realized.
Wherein, the control signal that single bit revolving door corresponds is:
IF＝ε’I(t)cos(ωIFt)+ε'Q(t)sin(ωIFt)
Where ε 'I (t) represents the envelope in-phase component of the steering signal, ε' Q (t) represents the envelope quadrature component of the steering signal, ω IF represents the phase of the steering signal, sin (ω IF t) represents the sine signal, cos (ω IF t) represents the cosine signal.
The envelope in-phase component of the steering signal is:
ε’I(t)＝εI(t)cos(φ0+δt)+εQ(t)sin(φ0+δt)
the envelope quadrature component of the steering signal is:
ε’Q(t)＝εQ(t)cos(φ0+δt)-εI(t)sin(φ0+δt)
Wherein epsilon I(t)、εQ(t)、φ0 and delta both represent parameters of the control signal, and the size of phi 0 determines the angle and direction of the rotation axis in the bloch sphere about which the qubit state vector needs to rotate. Epsilon I (t) and epsilon Q (t) are expressed as follows:
In one specific application, the parameters of the control signal of the single-bit revolving door are as follows: omega IF =600×2pi MHz, delta is 0-20×2pi MHz, phi 0 is 0, pi, The values of A I are respectively 0.3 and 1, the value of T is 20ns, eta= -240 x2 pi MHz, and the value of alpha is 1. Phi 0 =0, the axis of rotation is the X-axis in the Buloch sphere and the direction is the positive direction of the X-axis, phi 0 =pi, the axis of rotation is the X-axis in the Buloch sphere and the direction is the negative direction of the X-axis,/>In the case of the ball, the axis of rotation is the Y-axis of the ball and the direction is the positive Y-axis direction,/>When the rotating shaft is the Y-axis in the Buloch sphere, and the direction is the negative direction of the Y-axis. The rotation angle of the qubit state vector is 90 degrees when a I =0.3, and 180 degrees when a I =1.
When the single-bit revolving door is needed to be realized, only the parameters corresponding to the target single-bit revolving door are needed to be determined according to actual needs, and the envelope of the target control signal can be determined according to the determined parameters. The envelope in-phase component and the envelope quadrature component are multiplied by the sine signal and the cosine signal respectively, and then the two multiplication results are added to obtain a wave packet signal, namely a target control signal, the phase of the target control signal is consistent with the phase difference of the local oscillation signal, and a plurality of identical target single-bit revolving doors can be continuously realized. The control signals stored in the corresponding table cannot be changed, so that the compiling and pre-storing of the control signals are facilitated, and the operation complexity of the quantum bits is simplified.
Referring to fig. 2, a second embodiment of the present invention provides an apparatus for generating a qubit manipulation signal. The control signal and the local oscillation signal are mixed to be changed into radio frequency from intermediate frequency and then act on the quantum bit to realize the single-bit revolving gate. The device of the present embodiment has all the technical features of the device of the first embodiment, and is different in that the device of the present embodiment further includes a parallel-serial conversion module 4, and the signal mixer 3 is further configured to divide the target control signal into at least one path of parallel outputs; the parallel-serial conversion module 4 is configured to convert at least one path of target control signal output in parallel into a serial signal under the action of a serial clock, where the frequency of the serial clock is not lower than the frequency of the working clock.
The sine signal and the cosine signal generated by the sine signal generator are usually digital signals, so that digital-to-analog conversion needs to be performed on the target control signal, and parallel-to-serial processing needs to be performed on the target control signal before digital-to-analog conversion is performed.
The sine signal generator generates sine signals and cosine signals in the form of digital signals, which are mostly realized in the FPGA, and the invention adopts two modes to generate sine and cosine signals with higher frequency in the FPGA in consideration of the limited highest working frequency of the FPGA.
For the first mode, please refer to fig. 3, the sine and cosine signal generator 1 is used in an FPGA, and can generate a sine and cosine signal with a higher frequency in the FPGA. The sine and cosine signal generator 1 comprises an address acquisition module 10A and a memory 20A, wherein the memory 20A stores a first number of sine values and cosine values of a preset frequency.
The address acquisition module 10A is configured to sequentially acquire the table lookup addresses incremented by a preset step size under the action of the working clock, and send the table lookup addresses to the memory 20A. The table lookup address is usually represented in binary, and the value of the table lookup address acquired for the first time is preferably 0. The difference between the table lookup address obtained each time and the table lookup address obtained last time is a preset step length, and the preset step length can be set according to actual needs, for example, 1. The table lookup address may be obtained by internal pre-storing, internal generating or external inputting.
The memory 20A is configured to output in parallel a second number of current sine values and current cosine values for forming a sine signal and a cosine signal, respectively, each time a table lookup address is entered; the second number is a preset number of paths, the phases of the sine value and the cosine value output each time are increased by a preset phase increment, the sine value and the cosine value output by two adjacent times are continuous in phase, and the preset phase increment is determined according to a preset frequency, the first number, the second number and the frequency of the working clock.
In which, taking the sine value of each output as an example, their frequencies are all preset frequencies, but their phases are continuous. When the first table lookup address is sent, the memory 20A may sequentially read the second number of sine values from the sine value with the smallest phase in the order of from the smaller phase to the larger phase, the difference between the phases of the sine values read in two adjacent times is the preset phase increment, and then the memory 20A outputs the read second number of sine values in parallel. This is then done for each look-up table, and the difference between the phase of the first sine value of the last read and the last sine value of the last read is also the predetermined phase increment.
Similarly, the frequency of the cosine value output each time is a preset frequency, and the phase is continuous. The second number of sine values forms a digitized sine signal and the second number of cosine values forms a digitized cosine signal, which are continuously generated as long as the lookup address is continuously fed into the memory 20A.
The preset frequency, the first quantity, the second quantity and the frequency of the working clock are set according to actual needs. The preset frequency is the frequency of the sine signal and the cosine signal. The first number is a total number of sine or cosine values stored by the memory and the second number is a fraction of the total number of sine or cosine values, and therefore the second number is less than or equal to the first number. The frequency of the operating clock should not exceed the maximum operating frequency of the FPGA. The frequency of the operating clock and the value of the second number are related to the sampling rate, the product of the two being equivalent to the sampling rate, e.g. when the sampling rate is 1.6GHz, the frequency of the operating clock is set to 200MHz, and then the second number is 8. The sampling rate is determined by the control requirements of the qubit. According to the nyquist sampling law, the ratio of the preset frequency to the sampling frequency is at most 1:2, that is to say, the preset frequency can reach 800MHz theoretically, thereby realizing the sine and cosine signals with higher frequency in the FPGA.
Referring to fig. 4, the memory 20A provides two identical lookup tables LUT1, the two lookup tables LUT1 store sine values and cosine values respectively, the number of lookup address bits of the lookup table LUT1 is a first number of bits a, the number of data bits of the lookup table LUT1 is a second number of bits B, and the second number of sine values and cosine values with continuous phases correspond to the same lookup address, wherein the product of 2 A and the second number is equal to 2 B. The lookup address is incremented from 0.
Wherein one lookup table LUT1 stores a first number of sine values and the other lookup table LUT1 stores a first number of cosine values, the first number being equal to 2 A.2A sine values or cosine values, which is required to be addressed by 2 B lookup addresses, and the second number B being smaller than the first number a, one lookup address is required to address the second number of sine values or cosine values simultaneously. The phases of the sine value and the cosine value of the second number corresponding to each table lookup address are continuous, so that the phase difference between the adjacent sine value and the adjacent cosine value in the sine value and the cosine value of the second number corresponding to the same table lookup address is a preset phase increment, and the phase difference between the sine value and the cosine value with the largest phase in the sine value and the cosine value of the second number corresponding to the former table lookup address and the phase difference between the sine value and the cosine value with the smallest phase in the sine value and the cosine value of the second number corresponding to the latter table lookup address is also a preset phase increment.
The storage locations of the first number of sine values or cosine values in the look-up table LUT1 can be flexibly adjusted. In an application scenario of the embodiment of the present invention, the lookup table LUT1 has a second number of sub-tables, where the number of sine values or cosine values stored in each sub-table is 2 B, the same data bit of each sub-table corresponds to the same table lookup address, and the sine values or cosine values stored in the same data bit are continuous in phase, and the phases of the sine values or cosine values stored in two adjacent data bits in the same sub-table differ by a second number of preset phase increment.
Wherein the number of sub-tables is also equal to the second number, so that each sub-table only needs to store a number of sine values or cosine values of 2 B, and thus the total number of the sine values or cosine values stored in all sub-tables is equal to the first number. Each sine value or cosine value in the sub-table occupies a data bit, the number of table lookup address bits corresponding to the data bits in the sub-table is the second bit number B, the 1 st table lookup address corresponds to the 1 st data bit of each sub-table, namely corresponds to the sine value or cosine value stored in the 1 st data bit, the 2 nd table lookup address corresponds to the 2 nd data bit of each sub-table, the 3 rd table lookup address corresponds to the 3 rd data bit of each sub-table, and the like, and the 2 nd B table lookup address corresponds to the 2 nd B data bits of each sub-table.
And the sine or cosine values stored by the same data bits of each sub-table are consecutive in phase, i.e. the difference in phase is a preset phase increment. The phase difference of the sine value or the cosine value stored by two adjacent data bits in the same sub-table is a preset phase increment of a second quantity, namely the product of the second quantity and the preset phase increment.
In this embodiment, the preset phase increment is:
Wherein, N represents the first quantity, the value range is [1,2 B ], c represents the second quantity, f out represents the preset frequency, and f S represents the frequency of the working clock.
Further, the sinusoidal signal is:
The cosine signal is:
wherein n represents the value of the lookup address, the range of the value is [0,2 A -1], a represents the amplitude, Representing the initial phase, and b representing the offset. In order to facilitate signal processing, in this embodiment, the amplitudes, initial phases, and offset of the sine signal and the cosine signal are the same.
Each sub-table will be described in detail below with reference to fig. 5. Referring to fig. 5, each sine value of the sine signal expressed by the above formula is stored in 8 sub-tables of a lookup table LUT 1. The number of sine values, namely the first number N is equal to 2 17, the number of sub-tables, namely the second number 8,c, is in the value range of [0,7], 8 sub-tables are respectively corresponding, the number of bits of the table lookup address is 14, the value range of the table lookup address is [0,2 14 -1], for the convenience of calculation, a is 1,And b takes 0. The sine values stored in each sub-table are as follows:
The sine value stored in each data bit of the 1 st sub-table is in turn sin[0*2π*PINC/N]、sin[8*2π*PINC/N]、sin[16*2π*PINC/N]、…、sin[8*(214-2)*2π*PINC/N]、sin[8*(214-1)*2π*PINC/N];
The sine value stored in each data bit of the 2 nd sub-table is in turn sin[1*2π*PINC/N]、sin[9*2π*PINC/N]、sin[17*2π*PINC/N]、…、sin[(8*(214-2)+1)*2π*PINC/N]、sin[(8*(214-1)+1)*2π*PINC/N];
The sine value stored in each data bit of the 3 rd sub-table is in turn sin[2*2π*PINC/N]、sin[10*2π*PINC/N]、sin[18*2π*PINC/N]、…、sin[(8*(214-2)+2)*2π*PINC/N]、sin[(8*(214-1)+2)*2π*PINC/N];
Similarly, the sine value stored in each data bit of the 8 th sub-table is in turn sin[7*2π*PINC/N]、sin[15*2π*PINC/N]、sin[23*2π*PINC/N]、…、sin[(8*(214-2)+7)*2π*PINC/N]、sin[(8*(214-1)+7)*2π*PINC/N].
It can be seen that the sine values stored in adjacent two data bits in each sub-table are out of phase by 8 x PINC.
The process of generating the sinusoidal signal is as follows:
when the 1 st table lookup address is sent, i.e. n=0, 8 sub-tables output sin [0 x pinc x 2 pi/N ], sin [1 x pinc x 2 pi/N ], sin [ 2x pinc x 2 pi/N ], …, sin [7 x pinc x 2 pi/N ] respectively;
when the 2 nd table lookup address is sent, i.e. n=1, 8 sub-tables output sin [8×pinc×2pi/N ], sin [9×pinc×2pi/N ], sin [10×pinc×2pi/N ], …, sin [15×pinc×2pi/N ] respectively;
When the 3 rd table lookup address is sent, i.e. n=2, 8 sub-tables output sin [16×pinc×2pi/N ], sin [17×pinc×2pi/N ], sin [18×pinc×2pi/N ], …, sin [23×pinc×2pi/N ] respectively;
By analogy, when the 2 14 th lookup address is input, namely n= 14 -1, 8 sub-tables output respectively sin[8*(214-1)*2π*PINC/N]、sin[(8*(214-1)+1)*2π*PINC/N]、sin[(8*(214-1)+2)*2π*PINC/N]、…、sin[(8*(214-1)+7)*2π*PINC/N].
It can be seen that the phase of the 8 sine values output by the 8 sub-tables each time is incremented by PINC, the last sine value output in the previous time being out of phase with the first sine value output in the next time by PINC.
For the second mode, please refer to fig. 6, the sine and cosine signal generator 1 is used in an FPGA, and can generate a sine and cosine signal with a higher frequency in the FPGA. The sine and cosine signal generator 1 includes an address acquisition module 10B and a memory 20B storing trigonometric values of at least one quarter cycle, the number of trigonometric values of one cycle being a first number, the number of the memory 20B being a second number.
The address acquisition module 10B is configured to sequentially acquire multiple table lookup addresses under the action of the working clock, and send the multiple table lookup addresses to the second number of memories 20B, where the table lookup addresses of two adjacent table lookup addresses at the same time differ by a preset phase increment, and the table lookup addresses of two adjacent table lookup addresses of the same time differ by a second number multiple of the preset phase increment. If the preset phase increment is represented by PINC, the second number is represented by c, the table lookup addresses of two adjacent paths at the same time are different from each other by PINC, the minimum preferred value in the table lookup addresses obtained for the first time is 0, the table lookup addresses of other paths are sequentially 1 PINC, 2 PINC, 3 PINC, 4 PINC and … …, and the table lookup addresses of two adjacent paths at the same time are different from each other by c PINC, for example, the table lookup addresses of the first path are sequentially 0, c PINC, 2c PINC, 3c PINC and … ….
The memory 20B is configured to output a current sine value and a current cosine value each time a table lookup address is sent, and form a sine signal and a cosine signal of a preset frequency, respectively. The second number is a preset number of paths, and the preset phase increment is determined according to a preset frequency, the first number, the second number and the frequency of the working clock.
Wherein, the table lookup address corresponding to each trigonometric function value stored in the memory 20B is incremented by PINC from 0. For a certain memory 20B, for example, the memory 20B corresponding to the first path of table lookup address receives table lookup addresses of 0, c×pinc, 2c×pinc, 3c×pinc, … … in order, and then the phases of the sine signal and the cosine signal output finally are increased by c×pinc, and the phases of the sine signal and the cosine signal output by two adjacent memories 20 are different by PINC.
The preset frequency, the first quantity, the second quantity and the frequency of the working clock are set according to actual needs. The first number is the total number of trigonometric values for one cycle and the memory 20B needs to store at least the first quarter of the trigonometric values of the first number. The frequency of the operating clock should not exceed the maximum operating frequency of the FPGA. The frequency of the operating clock and the value of the second number are related to the sampling rate, and the product of the two is equivalent to the sampling rate, for example, when the sampling rate is 1.6GHz, and the frequency of the operating clock is set to 200MHz, then the second number is 8, that is, 8 memories 20B are needed. The sampling rate is determined by the control requirements of the qubit. According to the nyquist sampling law, the ratio of the preset frequency to the sampling frequency is at most 1:2, that is to say, the preset frequency can reach 800MHz theoretically, thereby realizing the sine and cosine signals with higher frequency in the FPGA.
Since the trigonometric function has periodicity, the trigonometric function value of the last three-quarter cycle can be calculated from the periodicity as long as the trigonometric function value of the first three-quarter cycle is known. In the present embodiment, the trigonometric function value stored in the memory 20B is a sine value of at least one quarter cycle, a cosine value of at least one quarter cycle, or a sine value and a cosine value of at least one quarter cycle.
Further, the memory 20B is configured to check whether the current table lookup address stores a corresponding sine value or a corresponding cosine value every time one table lookup address is sent, output the stored current sine value and the stored current cosine value to form a sine signal and a cosine signal of a preset frequency respectively when the corresponding sine value or the corresponding cosine value is stored, calculate the corresponding sine value or the corresponding cosine value according to the periodicity of the sine value or the corresponding cosine value when the corresponding sine value or the corresponding cosine value is not stored, and output the calculated current sine value and the calculated current cosine value to form a sine signal and a cosine signal of the preset frequency respectively.
If the memory 20B stores a sine value of one period and a cosine value of one period, and the numbers of the sine value and the cosine value are the first numbers, each lookup table address stores a corresponding sine value or cosine value, and the stored current sine value and current cosine value can be directly output. If the memory 20B stores only sine values for less than one period and/or cosine values for less than one period, then there are cases where some table lookup addresses do not have corresponding sine values or cosine values, and the sine values and cosine values corresponding to these table lookup addresses may be calculated according to the periodicity of the sine values or cosine values in combination with the stored sine values and/or cosine values.
Referring to fig. 7, the memory 20B provides a lookup table LUT2, wherein the lookup table LUT2 stores a quarter-period sine value, and the number of lookup address bits of the lookup table LUT2 is a first number of bits a, wherein 2 A is equal to the first number. Only the data bits corresponding to the first 2 A/4 table lookup addresses respectively store sine values, and the data bits corresponding to the rest table lookup addresses are empty.
In this embodiment, the preset phase increment is:
Where N represents a first number, c represents a second number, f out represents a preset frequency, f S represents a frequency of an operation clock, and Round () represents a rounding function.
Further, the sinusoidal signal is:
The cosine signal is:
wherein n is the value of the lookup address, n is in the range of 0,2 A -1, a is the amplitude, Representing the initial phase, and b representing the offset.
The current sine value output by memory 20B is:
the current cosine value output by memory 20B is:
Wherein m represents the value of the lookup address of the lookup table, and the value range is [0,2 A -1].
In order to facilitate signal processing, in this embodiment, the amplitudes, initial phases, and offset of the sine signal and the cosine signal are the same. For ease of understanding, a takes 1,And b takes 0.
As can be seen from FIG. 7, the sine values stored in the first 2 A/4 data bits of the lookup table LUT2 are, in order, sin (0*2 pi/N), sin (1*2 pi/N), sin (2 x 2 pi/N), sin (3*2 pi/N), … …,The remaining data bits store data that is NULL, indicating that it is empty. It can be seen that each of the stored sine values in the look-up table LUT2 is associated with a look-up address of the look-up table, which is m, the sine value is sin (m x 2 pi/N).
Then the sine values corresponding to the rest search addresses can be calculated to be in turn as follows according to the periodicity of the sine functionsin[(N-1)*2π/N]。
Similarly, the cosine value may be calculated based on the periodicity of the sine value.
Assuming that the second number is 8, the process of generating the sinusoidal signal is as follows:
The table lookup addresses fed into the 1 st memory 20B are sequentially 0 PINC, 8 PINC, 16 PINC and … …, and the table lookup addresses equal to 0 PINC, 8 PINC, 16 PINC and … … in the table lookup LUT2 are sequentially 0 PINC, 8 PINC, 16 PINC and … …, and the sine signals output by the 1 st memory 20B are sin (0*2 pi) PINC/N, sin (8*2 pi) PINC/N, sin (16 pi) PINC/N and … …;
The table lookup addresses fed into the 2 nd memory 20B are sequentially 1G NC, 9G NC, 17G NC and … …, and the table lookup addresses equal to 1G NC, 9G NC, 17G NC and … … in the table lookup LUT2 are sequentially 1G NC, 9G NC, 17G NC and … …, and sine signals output by the 2 nd memory 20B are sin (1*2 pi) PINC/N, sin (9*2 pi) PINC/N, sin (17 pi) PINC/N and … …;
The table lookup addresses fed into the 3 rd memory 20B are sequentially 2x PINC, 10 x PINC, 18 x PINC and … …, and the table lookup addresses equal to 2x PINC, 10 x PINC, 18 x PINC and … … in the table lookup LUT2 are sequentially 2x PINC, 10 x PINC, 18 x PINC and … …, so that sine signals output by the 3 rd memory 20B are sin (2 x 2 pi x PINC/N), sin (10 x 2 pi x PINC/N), sin (18 x 2 pi x PINC/N) and … …;
Similarly, the table lookup addresses fed into the 8 th memory 20B are 7×pinc, 15×pinc, 23×pinc, … … in order, and the table lookup addresses equal to 7×pinc, 15×pinc, 23×pinc, … … in the table lookup LUT2 are 7×pinc, 15×pinc, 23×pinc, … … in order, and the sine signal output from the 8 th memory 20B is sin (7*2 ×pinc/N), sin (15×2pi×pinc/N), sin (23×2pi×pinc/N), … ….
It can be seen that the phase of the sinusoidal signal output by each of the 8 memories 20B is incremented by PINC and the phase of the sinusoidal signal output by the same memory 20B is incremented by 8 PINC.
It should be noted that, if the table lookup address sent to the memory 20B exceeds the maximum value of the table lookup address of the table lookup table, the table lookup address addressed by the memory 20B in the table lookup table LUT2 is the sum of the table lookup address sent to the memory 20B and the first number N.
Likewise, the 8 memories 20B output cosine signals according to the above procedure. The cosine signals output by the 1 st memory 20B are cos (0*2 pi×pinc/N), cos (8*2 pi×pinc/N), cos (16pi×pinc/N), … …; the cosine signal output by the 2 nd memory 2B0 is cos (1*2 pi×pinc/N), cos (9*2 pi×pinc/N), cos (172pi×pinc/N), … …; the cosine signals output by the 3 rd memory 20B are cos (2×2pi×pinc/N), cos (10×2pi×pinc/N), cos (18×2pi×pinc/N), … …; … …; the cosine signals output by the 8 th memory 20B are cos (7*2 pi PINC/N), cos (15 pi PINC/N), cos (23 pi PINC/N), … ….
In the two modes, the product of the frequency of the working clock and the second number is equivalent to the sampling frequency, and according to the Nyquist sampling law, the theoretical preset frequency can reach half of the sampling frequency, so that sine and cosine signals with higher frequency can be generated in the FPGA, and the resource consumption and cost can be reduced.
Referring to fig. 8, a fifth embodiment of the present invention provides a quantum computer control system, which includes an apparatus 100, where the apparatus 100 is an apparatus for generating a qubit manipulation signal according to any of the foregoing embodiments.
In other embodiments, the quantum computer control system further comprises a mixer 200, where the mixer 200 is configured to mix the target manipulation signal with the local oscillator signal, so that the target manipulation signal is changed from an intermediate frequency to a radio frequency. After mixing, the target control signal of the radio frequency is directly applied to the quantum bit to realize the target single-bit revolving gate.
Further, the quantum computer control system further includes a digital-to-analog converter 300, where the digital-to-analog converter 300 is configured to perform digital-to-analog conversion on the target manipulation signal before mixing the target manipulation signal.
In the description of the present specification, a description of the terms "one embodiment," "some embodiments," "examples," or "particular examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (17)
1. An apparatus for generating a qubit manipulation signal, the manipulation signal being mixed with a local oscillator signal to change from an intermediate frequency to a radio frequency and acting on a qubit to implement a single bit turnstile, comprising:
the sine and cosine signal generator is used for respectively outputting sine signals and cosine signals with the same frequency of a preset path number in parallel under the action of the working clock;
The envelope generator is used for determining the envelope of the target control signal from a pre-stored corresponding table according to the target single-bit revolving door, and respectively outputting an in-phase envelope component and an orthogonal envelope component of a preset number of paths in parallel under the action of the working clock, wherein the corresponding table stores control signals corresponding to different single-bit revolving doors;
The signal mixer is used for multiplying sine signals with preset paths by envelope in-phase components and cosine signals with preset paths by envelope quadrature components under the action of the working clock, and adding the two multiplication results to obtain the target control signal so that the phase difference of the target control signal and the local oscillation signal is consistent;
when the sine and cosine signal generator outputs sine signals and cosine signals in a first mode, the sine and cosine signal generator comprises an address acquisition module and a memory, wherein the memory stores sine values and cosine values of a first number of preset frequencies:
the address acquisition module is used for sequentially acquiring table lookup addresses which are increased by a preset step length under the action of a working clock and sending the table lookup addresses into the memory;
the memory is configured to output a second number of current sine values and current cosine values for forming a sine signal and a cosine signal respectively in parallel each time a table lookup address is sent;
The second number is the preset number of paths, the phases of the sine value and the cosine value output each time are increased by a preset phase increment, the sine value and the cosine value output by two adjacent times are continuous in phase, and the preset phase increment is determined according to the product of the ratio of the preset frequency to the frequency of the working clock and the ratio of the first number to the second number.
2. The apparatus of claim 1, further comprising a parallel-to-serial conversion module:
The signal mixer is also used for dividing the target control signal into at least one path of parallel output;
The parallel-serial conversion module is used for converting at least one path of target control signals which are output in parallel into serial signals under the action of a serial clock, wherein the frequency of the serial clock is not lower than that of the working clock.
3. The apparatus of claim 1 or 2, wherein the memory provides two identical look-up tables, the two look-up tables storing sine and cosine values, respectively, the look-up table having a first number of bits a, the look-up table having a second number of bits B, the second number of sine and cosine values being consecutive in phase corresponding to the same look-up table address, wherein the product of 2 A and the second number is equal to 2 B.
4. A device according to claim 3, wherein the look-up table has a second number of sub-tables, each sub-table storing a number of sine or cosine values of 2 B, the same data bits of each sub-table corresponding to the same table address, and the sine or cosine values stored in the same data bit being consecutive in phase, the phases of the sine or cosine values stored in adjacent two data bits in the same sub-table being different by a second number of preset phase increments.
5. The apparatus of claim 4, wherein the predetermined phase increment is:
wherein N represents the first number and the value range is [1,2 B ], c represents the second number, Representing the preset frequency,/>Representing the frequency of the operating clock.
6. The apparatus of claim 5, wherein the sinusoidal signal is:
The cosine signal is:
Wherein n represents the value of the table lookup address, the range of the value is [0,2 A -1], a represents the amplitude, Representing the initial phase, and b representing the offset.
7. The apparatus according to claim 1 or 2, wherein when the sine and cosine signal generator outputs sine and cosine signals in a second manner that is an alternative to the first manner, the sine and cosine signal generator includes an address acquisition module and a memory storing trigonometric function values of at least one quarter cycle, the number of trigonometric function values of one cycle being a first number, the number of the memory being a second number;
the address acquisition module is used for sequentially acquiring multiple paths of table lookup addresses under the action of a working clock, respectively sending the multiple paths of table lookup addresses into a second number of memories, wherein the table lookup addresses of two adjacent paths at the same time differ by a preset phase increment, and the table lookup addresses of two adjacent paths differ by a second number multiple of the preset phase increment;
The memory is configured to output a current sine value and a current cosine value when a table lookup address is sent in, and a sine signal and a cosine signal of preset frequency are formed respectively;
The second number is the preset number of paths, and the preset phase increment is determined according to the product of the ratio of the preset frequency to the frequency of the working clock and the ratio of the first number to the second number.
8. The apparatus of claim 7, wherein the memory stores trigonometric values as sine values of at least one quarter cycle, cosine values of at least one quarter cycle, or sine and cosine values of at least one quarter cycle.
9. The apparatus of claim 8, wherein the memory is configured to check whether a corresponding sine value or a corresponding cosine value is stored in a current lookup address every time a lookup address is input, to output the stored current sine value and current cosine value to form a sine signal and a cosine signal of a preset frequency, respectively, when the corresponding sine value or cosine value is not stored, to calculate the corresponding sine value or cosine value according to periodicity of the sine value or cosine value, and to output the calculated current sine value and current cosine value to form a sine signal and a cosine signal of the preset frequency, respectively.
10. The apparatus of claim 9, wherein the memory provides a look-up table storing a quarter-cycle sine value, the look-up table having a first number of bits a, wherein 2 A is equal to the first number.
11. The apparatus of claim 10, wherein the predetermined phase increment is:
Wherein N represents the first number, c represents the second number, Representing the preset frequency,/>Representing the frequency of the operating clock,/>Representing a rounding function.
12. The apparatus of claim 11, wherein the sinusoidal signal is:
The cosine signal is:
Wherein, The value of the table lookup address is represented, the value range of n is [0,2 A -1], a represents the amplitude,/>Representing the initial phase, and b representing the offset.
13. The apparatus of claim 12, wherein the current sine value of the memory output is:
The current cosine value output by the memory is:
Wherein m represents the value of the lookup address of the lookup table, and the value range is [0,2 A -1].
14. The apparatus of claim 6 or 13, wherein the sine and cosine signals are the same in amplitude, phase and offset.
15. A quantum computer control system comprising the apparatus for generating a qubit manipulation signal of any one of claims 1 to 14.
16. The quantum computer control system of claim 15, further comprising a mixer for mixing the target manipulation signal with a local oscillator signal to change the target manipulation signal from an intermediate frequency to a radio frequency.
17. The quantum computer control system of claim 16 further comprising a digital-to-analog converter for digital-to-analog converting the target manipulation signal prior to mixing the target manipulation signal.
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