CN115441717B

CN115441717B - Self-adaptive accelerating circuit suitable for voltage mode loop

Info

Publication number: CN115441717B
Application number: CN202211171225.4A
Authority: CN
Inventors: 徐海峰; 易新敏; 梁华
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2022-09-23
Filing date: 2022-09-23
Publication date: 2024-05-03
Anticipated expiration: 2042-09-23
Also published as: CN115441717A

Abstract

The present disclosure provides an adaptive acceleration circuit for a voltage die loop, comprising: the circuit comprises a first conversion circuit, a second conversion circuit, a third conversion circuit, a difference circuit, a multiplication circuit and an output circuit, wherein the first conversion circuit converts a reference voltage into a first reference current and a second reference current; the second conversion circuit converts the output sampling partial pressure into an output sampling current; the third conversion circuit converts the input sampling partial pressure of the voltage mode loop into input sampling current; the difference circuit determines a difference current according to the input sampling current and the output sampling current and provides the difference current to the multiplication circuit; the multiplication circuit determines an output current according to the difference current, the first reference current and the output sampling current, and provides the output current to the output circuit; the output circuit outputs a clamping voltage according to the output current and the second reference current, controls the output voltage of an output end of the error amplifier in the voltage die loop and clamps the output voltage to the clamping voltage.

Description

Self-adaptive accelerating circuit suitable for voltage mode loop

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and in particular, to an adaptive acceleration circuit suitable for a voltage mode loop.

Background

Along with the expansion of the market of integrated circuits, direct current-to-direct current (DC-DC) converters are rapidly developed, a DC-DC voltage mode topology control loop system is simple in structure, an inductor L and a capacitor C in a voltage mode loop form a second-order LC filter network, but because a power level double pole and a complex three-type compensation network are needed, the three-type compensation network introduces larger capacitance and impedance under the condition of ensuring the stability of the loop, and generates a low-frequency main pole and other compensation zero poles, so that the system bandwidth is smaller, and the system response speed is slower when the system hops facing different application conditions.

Aiming at the problem of slower system response speed when the jump is faced with different application conditions in the related art, no effective technical solution is proposed at present.

Disclosure of Invention

The main objective of the present disclosure is to provide an adaptive acceleration circuit suitable for a voltage loop, so as to solve the problem of slow system response speed when the system hops to different application conditions in the related art.

In order to achieve the above object, the present disclosure provides an adaptive acceleration circuit adapted for a voltage die loop, the adaptive acceleration circuit comprising: a first conversion circuit, a second conversion circuit, a third conversion circuit, a difference circuit, a multiplication circuit, and an output circuit, wherein:

The first conversion circuit is configured to convert the reference voltage into a first reference current and a second reference current, and to supply the first reference current to the multiplication circuit and the second reference current to the output circuit;

the second conversion circuit is configured to convert the output sampling partial pressure of the voltage mode loop into output sampling current and provide the output sampling current to the difference circuit and the multiplication circuit respectively, wherein the output sampling partial pressure of the voltage mode loop is obtained by sampling the output voltage of the voltage mode loop;

The third conversion circuit is configured to convert the input sampling partial pressure of the voltage mode loop into an input sampling current and provide the input sampling current to the difference circuit, wherein the input sampling partial pressure of the voltage mode loop is obtained by sampling the input voltage of the voltage mode loop;

The difference circuit is configured to determine a difference current from the input sampling current and the output sampling current and to provide the difference current to the multiplication circuit;

The multiplying circuit is configured to determine an output current according to the difference current, the first reference current and the output sampling current, and provide the output current to the output circuit; and

The output circuit is configured to output a clamping voltage based on the output current and the second reference current, to control an output voltage at an output of the error amplifier in the voltage die loop, to clamp the output voltage to the clamping voltage.

Optionally, the first conversion circuit includes a first buffer circuit and a first current mirror circuit, wherein:

The first buffer circuit is configured to convert the reference voltage into a reference current and provide the reference current to the first current mirror circuit;

The first current mirror circuit is configured to replicate the reference current, obtain a first reference current and a second reference current, and provide the first reference current to the multiplication circuit and the second reference current to the output circuit, wherein the reference current, the first reference current, and the second reference current are equal.

Further, the first buffer circuit includes a first operational amplifier, a first transistor, and a first resistor, and the first current mirror circuit includes a second transistor, a third transistor, and a fourth transistor, wherein:

The non-inverting input end of the first operational amplifier is coupled with the reference voltage end, the inverting input end of the first operational amplifier is respectively coupled with the second pole of the first transistor and the first end of the first resistor, the output end of the first operational amplifier is coupled with the control pole of the first transistor, and the first operational amplifier is configured to clamp the reference voltage on the first resistor to obtain the reference current;

The first electrode of the first transistor is coupled with the control electrode of the second transistor, the second electrode of the second transistor, the control electrode of the third transistor and the control electrode of the fourth transistor respectively;

the control electrode of the second transistor is respectively coupled with the second electrode of the second transistor, the control electrode of the third transistor and the control electrode of the fourth transistor, and the first electrode of the second transistor is respectively coupled with the power supply voltage end, the first electrode of the third transistor and the first electrode of the fourth transistor;

The control electrode of the third transistor is coupled with the control electrode of the fourth transistor, the first electrode of the third transistor is respectively coupled with the power supply voltage end and the first electrode of the fourth transistor, the second electrode of the third transistor is coupled with the second end of the multiplication circuit, the third transistor is configured to replicate the reference current flowing through the second transistor to obtain a first reference current, and the first reference current is provided from the second electrode to the second end of the multiplication circuit;

The first pole of the fourth transistor is coupled to the power supply voltage terminal, the second pole of the fourth transistor is coupled to the first terminal of the output circuit, and the fourth transistor is configured to replicate the reference current flowing through the second transistor to obtain a second reference current, and to provide the second reference current from the second pole to the first terminal of the output circuit.

Optionally, the second conversion circuit includes a second buffer circuit and a second current mirror circuit, wherein:

The second buffer circuit is configured to convert the output sampling voltage division into an output sampling current and provide the output sampling current to the second current mirror circuit;

the second current mirror circuit is configured to replicate the output sampling current and provide the output sampling current to the difference circuit and the multiplication circuit, respectively.

Further, the second buffer circuit includes a second operational amplifier, a fifth transistor, and a second resistor, and the second current mirror circuit includes a sixth transistor, a seventh transistor, and an eighth transistor, wherein:

The non-inverting input end of the second operational amplifier is coupled with the output sampling voltage division end, the inverting input end of the second operational amplifier is respectively coupled with the second pole of the fifth transistor and the first end of the second resistor, the output end of the second operational amplifier is coupled with the control pole of the fifth transistor, and the second operational amplifier is configured to clamp the output sampling voltage division on the second resistor to obtain output sampling current;

the first electrode of the fifth transistor is coupled to the control electrode of the sixth transistor, the second electrode of the sixth transistor, the control electrode of the seventh transistor and the control electrode of the eighth transistor, respectively;

the second end of the second resistor is grounded;

The control electrode of the sixth transistor is coupled to the second electrode of the sixth transistor, the control electrode of the seventh transistor and the control electrode of the eighth transistor respectively, and the first electrode of the sixth transistor is coupled to the power supply voltage terminal, the first electrode of the seventh transistor and the first electrode of the eighth transistor respectively;

The control electrode of the seventh transistor is coupled to the control electrode of the eighth transistor, the first electrode of the seventh transistor is coupled to the power voltage terminal and the first electrode of the eighth transistor respectively, the second electrode of the seventh transistor is coupled to the first terminal of the difference circuit, the seventh transistor is configured to replicate the output sampling current flowing through the sixth transistor and provide the output sampling current from the second electrode to the first terminal of the difference circuit;

the first pole of the eighth transistor is coupled to the power supply voltage terminal, the second pole of the eighth transistor is coupled to the second terminal of the multiplication circuit, and the eighth transistor is configured to replicate the output sampling current flowing through the sixth transistor and provide the output sampling current from the second pole to the second terminal of the multiplication circuit.

Optionally, the third conversion circuit includes a third buffer circuit and a third current mirror circuit, wherein:

The third buffer circuit is configured to convert the input sample voltage division into an input sample current and provide the input sample current to the third current mirror circuit;

the third current mirror circuit is configured to replicate the input sample current and provide the input sample current to the difference circuit.

Further, the third buffer circuit includes a third operational amplifier, a ninth transistor, and a third resistor, and the third current mirror circuit includes a tenth transistor and an eleventh transistor, wherein:

the non-inverting input end of the third operational amplifier is coupled to the input sampling voltage division end, the inverting input end of the third operational amplifier is respectively coupled to the second pole of the ninth transistor and the first end of the third resistor, the output end of the third operational amplifier is coupled to the control pole of the ninth transistor, and the third operational amplifier is configured to clamp the input sampling voltage division on the third resistor to obtain an input sampling current;

A first electrode of the ninth transistor is coupled to the control electrode of the tenth transistor, the second electrode of the tenth transistor and the control electrode of the eleventh transistor, respectively;

the second end of the third resistor is grounded;

the control electrode of the tenth transistor is coupled with the second electrode of the tenth transistor and the control electrode of the eleventh transistor respectively, and the first electrode of the tenth transistor is coupled with the power supply voltage terminal and the first electrode of the eleventh transistor respectively;

The first pole of the eleventh transistor is coupled to the supply voltage terminal, the second pole of the eleventh transistor is coupled to the second terminal of the difference circuit, and the eleventh transistor is configured to replicate the input sampling current flowing through the tenth transistor and to provide the input sampling current from the second pole to the second terminal of the difference circuit.

Optionally, the difference circuit includes a fourth current mirror circuit and a fifth current mirror circuit, the fourth current mirror circuit including a twelfth transistor and a thirteenth transistor, the fifth current mirror circuit including a fourteenth transistor and a fifteenth transistor, wherein:

The control electrode of the twelfth transistor is coupled to the first end of the second conversion circuit, the first electrode of the twelfth transistor and the control electrode of the thirteenth transistor respectively, the first electrode of the twelfth transistor is coupled to the first end of the second conversion circuit and the control electrode of the thirteenth transistor respectively, the second electrode of the twelfth transistor is coupled to the second electrode of the thirteenth transistor, the second electrode of the fourteenth transistor, the second electrode of the fifteenth transistor and the ground terminal respectively, wherein the output sampling current provided by the first end of the second conversion circuit flows through the twelfth transistor;

The control electrode of the thirteenth transistor is coupled to the first end of the second conversion circuit, the first electrode of the thirteenth transistor is coupled to the first end of the third conversion circuit and the first electrode of the fourteenth transistor respectively, the second electrode of the thirteenth transistor is coupled to the second electrode of the fourteenth transistor, the second electrode of the fifteenth transistor and the ground terminal respectively, and the thirteenth transistor is configured to replicate the output sampling current flowing through the twelfth transistor;

The control electrode of the fourteenth transistor is coupled to the first end of the third conversion circuit, the first electrode of the fourteenth transistor and the control electrode of the fifteenth transistor, respectively, the first electrode of the fourteenth transistor is coupled to the first end of the third conversion circuit and the control electrode of the fifteenth transistor, respectively, the second electrode of the fourteenth transistor is coupled to the second electrode of the fifteenth transistor and the ground, respectively, and the fourteenth transistor is configured to: the current flowing through the fourteenth transistor is a difference current obtained by subtracting the output sampling current flowing through the thirteenth transistor from the input sampling current supplied through the first terminal of the third conversion circuit;

The first pole of the fifteenth transistor is coupled to the first end of the multiplication circuit, the second pole of the fifteenth transistor is grounded, and the fifteenth transistor is configured to replicate the differential current flowing through the fourteenth transistor and provide the differential current from the first pole to the first end of the multiplication circuit.

Optionally, the multiplication circuit includes a sixth current mirror circuit including a sixteenth transistor and a seventeenth transistor, a current multiplier, and a seventh current mirror circuit including an eighteenth transistor and a nineteenth transistor, wherein:

the control electrode of the sixteenth transistor is coupled with the third end of the difference circuit, the second electrode of the sixteenth transistor and the control electrode of the seventeenth transistor respectively, the first electrode of the sixteenth transistor is coupled with the power supply voltage end and the first electrode of the seventeenth transistor respectively, and the second electrode of the sixteenth transistor is coupled with the third end of the difference circuit and the control electrode of the seventeenth transistor respectively;

The control electrode of the seventeenth transistor is coupled with the third end of the difference circuit, the first electrode of the seventeenth transistor is coupled with the power supply voltage end, the second electrode of the seventeenth transistor is coupled with the first input end of the current multiplier, and the seventeenth transistor is configured to replicate the difference current flowing through the sixteenth transistor and provide the difference current from the second electrode to the first input end of the current multiplier;

The current multiplier is configured to determine an output current according to the difference current of the first input terminal, the first reference current of the second input terminal and the output sampling current of the second output terminal, and provide the output current from the first output terminal to the eighteenth transistor;

the control electrode of the eighteenth transistor is coupled with the first output end of the current multiplier, the second electrode of the eighteenth transistor and the control electrode of the nineteenth transistor respectively, the first electrode of the eighteenth transistor is coupled with the power supply voltage end and the first electrode of the nineteenth transistor respectively, and the second electrode of the eighteenth transistor is coupled with the first output end of the current multiplier and the control electrode of the nineteenth transistor respectively;

A first pole of the nineteenth transistor is coupled to the supply voltage terminal, a second pole of the nineteenth transistor is coupled to the second terminal of the output circuit, and the nineteenth transistor is configured to replicate the output current flowing through the eighteenth transistor and to provide the output current from the second pole to the second terminal of the output circuit.

Optionally, the output circuit includes a fourth resistor and a fifth resistor, wherein:

The first end of the fourth resistor is coupled with the third end of the multiplication circuit, the second end of the fourth resistor is respectively coupled with the first end of the fifth resistor and the second reference current end of the first conversion circuit, and the current flowing through the fourth resistor is output current, wherein the clamping voltage is output from the first end of the fourth resistor to the output end of the error amplifier in the voltage mode loop, and the clamping voltage is used for clamping the output voltage to the clamping voltage when the output voltage of the error amplifier is smaller than the clamping voltage;

The first end of the fifth resistor is coupled to the second reference current end of the first conversion circuit, the second end of the fifth resistor is grounded, and the current flowing through the fifth resistor is the sum of the output current and the second reference current of the second reference current end.

In the adaptive acceleration circuit suitable for the voltage die loop, the first conversion circuit, the second conversion circuit and the third conversion circuit convert voltages into currents, the difference circuit and the multiplication circuit sequentially output difference currents and output currents, the output circuit outputs clamping voltages according to the output currents and the second reference currents, the output voltage of the output end of the error amplifier in the voltage die loop is controlled to be clamped to the clamping voltages, the output voltage of the error amplifier can be limited to a steady-state value of the clamping voltages, the response time of the voltage die loop is shortened when the voltage die loop jumps or jumps are input, the steady state is recovered more rapidly, and the problem that the response speed of the system is slower when the voltage die loop jumps under different application conditions in the related art is solved.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the prior art, the drawings that are required in the detailed description or the prior art will be briefly described, it will be apparent that the drawings in the following description are only some embodiments of the present disclosure and that other drawings may be obtained from these drawings without inventive effort to those of ordinary skill in the art.

FIG. 1 is an exemplary circuit diagram of a voltage-mode loop;

FIG. 2 is an exemplary block diagram of an adaptive acceleration circuit suitable for use in a voltage die loop provided by an embodiment of the present disclosure;

Fig. 3 is an exemplary circuit diagram of an adaptive acceleration circuit suitable for use in a voltage die loop provided by an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts.

In all embodiments of the present disclosure, since the source and drain of the transistor are symmetrical, the emitter and collector of the transistor are symmetrical, and the on-current directions between the source and drain of the N-type transistor and the P-type transistor are opposite, the on-current directions between the emitter and collector of the N-type transistor and the P-type transistor are opposite, in embodiments of the present disclosure, the controlled middle end of the transistor is referred to as the control electrode, and the remaining two ends of the transistor are referred to as the first electrode and the second electrode, respectively. The transistors employed in the embodiments of the present disclosure are primarily switching transistors. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).

Fig. 1 shows an exemplary circuit diagram of a voltage-mode loop. The input voltage of the voltage mould loop is V _IN, the output voltage is V _OUT, the pulse width modulation signal PWM provides bias voltage for the upper power tube HS and the lower power tube LS through the Drive circuit Drive, the inductance L and the load capacitance C form a second-order LC filter network, rf1 and Rf2 are feedback resistors, the non-inverting input end of the comparator Comp1 is connected with the feedback voltage Vfb, the inverting input end of the comparator Comp1 is connected with the first reference voltage Vref1, the output end of the comparator Comp1 is the feedback output voltage Vfbo, a three-type compensation network is arranged in a dotted line frame in FIG. 1, comp2 is a second comparator, and Vramp is a ramp signal.

Because the existence of the power level bipolar pole and the LC bipolar pole requires a more complex three-type compensation network, the three-type compensation network introduces larger capacitance and impedance under the condition of ensuring the loop to be stable, and the three-type compensation network comprises resistors R1, R2 and R3 and capacitors C1, C2 and C3 in the three-type compensation network, and the resistors and the capacitors can generate low-frequency main poles and other compensation zero poles, so that the bandwidth of the system is smaller, and the response speed of the system is slower when the system is subjected to jump of different application conditions such as load resistance RL jump or input voltage V _IN jump.

The non-inverting input end of the error amplifier EA in the three-type compensation network is a second reference voltage Vref2; when the jump of the application condition is specifically that the load resistor RL jumps from light load to heavy load, the output voltage Veao of the error amplifier EA will increase, the duty ratio of the pulse width modulation signal PWM increases, and the system response speed becomes slow, so that the output voltage Veao of the error amplifier EA rises slowly, and the rising speed of the load current is also slow, resulting in the deterioration of the transient response of the voltage mode loop output voltage V _OUT.

In order to solve the problem that the response speed of the system is slow when the system is in the face of jump of different application conditions, fig. 2 shows an exemplary block diagram of an adaptive acceleration circuit suitable for a voltage die loop according to an embodiment of the present disclosure, fig. 3 shows an exemplary circuit diagram of an adaptive acceleration circuit suitable for a voltage die loop according to an embodiment of the present disclosure, and fig. 2 includes: a first converting circuit 21, a second converting circuit 22, a third converting circuit 23, a difference circuit 24, a multiplying circuit 25, and an output circuit 26, wherein:

The first converting circuit 21 is configured to convert the reference voltage Vref into a first reference current Iref1 and a second reference current Iref2, and to supply the first reference current Iref1 to the multiplying circuit 25 and the second reference current Iref2 to the output circuit 26;

The second conversion circuit 22 is configured to convert the output sampling voltage V _OUT/k of the voltage-mode loop, which is obtained by sampling the output voltage V _OUT of the voltage-mode loop, into an output sampling current I _OUT/k and to supply the output sampling current I _OUT/k to the difference circuit 24 and the multiplication circuit 25, respectively; the output voltage V _OUT of the voltage mode loop is sampled in real time according to the partial pressure proportion coefficient k, and output sampling partial pressure V _OUT/k can be obtained;

The third conversion circuit is configured to convert the input sampling voltage V _IN/k of the voltage-mode loop, which is obtained by sampling the input voltage V _IN of the voltage-mode loop, into an input sampling current I _IN/k and to provide the input sampling current I _IN/k to the difference circuit 24; the input voltage V _IN of the voltage mode loop is sampled in real time according to the partial pressure proportion coefficient k, and input sampling partial pressure V _IN/k can be obtained;

the difference circuit 24 is configured to determine a difference current from the input sampling current I _IN/k and the output sampling current I _OUT/k, and to supply the difference current to the multiplication circuit 25;

The multiplication circuit 25 is configured to determine an output current from the difference current, the first reference current Iref1, and the output sampling current I _OUT/k, and to supply the output current to the output circuit 26; and

The output circuit 26 is configured to output a clamp voltage Vclamp according to the output current and the second reference current Iref2, and to control an output voltage Veao at an output terminal of the error amplifier EA in the voltage die loop, and clamp the output voltage Veao to the clamp voltage Vclamp.

According to the embodiment of the disclosure, through sampling the input voltage V _IN and the output voltage V _OUT of the voltage mode loop in real time, the output voltage Veao output by the error amplifier EA is limited to the clamping voltage Vclamp, the output voltage Veao can be clamped at a system steady-state value of the clamping voltage Vclamp, and other nodes in the whole voltage mode loop are accurately and slowly automatically adjusted by depending on the structure of the voltage mode loop until the voltage mode loop system is stable; by clamping the output voltage Veao at the clamping voltage Vclamp, the response time of the voltage mode loop is shortened when the voltage mode loop jumps against the load resistor RL or the loop input voltage V _IN jumps, the steady state is recovered more rapidly, and the problem of slower system response speed when the voltage mode loop jumps against different application conditions in the related art is solved.

Optionally, the first converting circuit 21 includes a first buffer circuit and a first current mirror circuit, wherein:

The first buffer circuit is configured to convert the reference voltage Vref into a reference current and provide the reference current to the first current mirror circuit; the reference voltage Vref can be converted into a corresponding reference current through the first buffer circuit;

The first current mirror circuit is configured to replicate the reference current, generate a mirrored current of the reference current, obtain a first reference current Iref1 and a second reference current Iref2, and provide the first reference current Iref1 to the multiplication circuit 25 and the second reference current Iref2 to the output circuit 26, wherein the reference current, the first reference current Iref1 and the second reference current Iref2 are equal.

In the embodiment of the disclosure, all current mirror circuits including the first current mirror circuit have a current ratio of 1:1.

Further, the first buffer circuit includes a first operational amplifier OPA1, a first transistor M1, and a first resistor R ₁, and the first current mirror circuit includes a second transistor M2, a third transistor M3, and a fourth transistor M4, wherein:

The non-inverting input terminal of the first operational amplifier OPA1 is coupled to the reference voltage terminal, the inverting input terminal of the first operational amplifier OPA1 is coupled to the second pole of the first transistor M1 and the first terminal of the first resistor R ₁, the output terminal of the first operational amplifier OPA1 is coupled to the control pole of the first transistor M1, and the first operational amplifier OPA1 is configured to clamp the reference voltage Vref on the first resistor R ₁ to obtain the reference current;

the first pole of the first transistor M1 is coupled to the control pole of the second transistor M2, the second pole of the second transistor M2, the control pole of the third transistor M3 and the control pole of the fourth transistor M4, respectively; the first transistor M1 is an N-type transistor;

The second end of the first resistor R ₁ is grounded;

The voltage can be converted into corresponding current information by a BUFFER structure, i.e. a BUFFER circuit, formed by the operational amplifier OPA and the N-type transistor.

The control electrode of the second transistor M2 is coupled to the second electrode of the second transistor M2, the control electrode of the third transistor M3 and the control electrode of the fourth transistor M4, respectively, the first electrode of the second transistor M2 is coupled to the power supply voltage terminal, the first electrode of the third transistor M3 and the first electrode of the fourth transistor M4, respectively, and the current flowing through the second transistor M2 is the reference current;

The control electrode of the third transistor M3 is coupled to the control electrode of the fourth transistor M4, the first electrode of the third transistor M3 is coupled to the power voltage terminal and the first electrode of the fourth transistor M4, respectively, the second electrode of the third transistor M3 is coupled to the second terminal of the multiplication circuit 25, the third transistor M3 is configured to replicate the reference current flowing through the second transistor M2, generate a mirror current of the reference current flowing through the second transistor M2, obtain a first reference current Iref1, and provide the first reference current Iref1 from the second terminal to the second terminal of the multiplication circuit 25;

the first pole of the fourth transistor M4 is coupled to the power voltage terminal, the second pole of the fourth transistor M4 is coupled to the first terminal of the output circuit 26, the fourth transistor M4 is configured to replicate the reference current flowing through the second transistor M2, generate a mirror current of the reference current flowing through the second transistor M2, obtain the second reference current Iref2, and provide the second reference current Iref2 from the second pole to the first terminal of the output circuit 26.

Optionally, the second conversion circuit 22 includes a second buffer circuit and a second current mirror circuit, wherein:

The second buffer circuit is configured to convert the output sampling voltage V _OUT/k into an output sampling current I _OUT/k and provide the output sampling current I _OUT/k to the second current mirror circuit;

The second current mirror circuit is configured to replicate the output sample current I _OUT/k, generate a mirrored current of the output sample current I _OUT/k, and provide the output sample current I _OUT/k to the difference circuit 24 and the multiplication circuit 25, respectively.

Further, the second buffer circuit includes a second operational amplifier OPA2, a fifth transistor M5, and a second resistor R ₂, and the second current mirror circuit includes a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8, wherein:

The non-inverting input end of the second operational amplifier OPA2 is coupled to the output sampling voltage division V _OUT/k end, the inverting input end of the second operational amplifier OPA2 is coupled to the second pole of the fifth transistor M5 and the first end of the second resistor R ₂ respectively, the output end of the second operational amplifier OPA2 is coupled to the control pole of the fifth transistor M5, and the second operational amplifier OPA2 is configured to clamp the output sampling voltage division V _OUT/k on the second resistor R ₂ to obtain an output sampling current I _OUT/k;

The first pole of the fifth transistor M5 is coupled to the control pole of the sixth transistor M6, the second pole of the sixth transistor M6, the control pole of the seventh transistor M7 and the control pole of the eighth transistor M8, respectively; the fifth transistor M5 is an N-type transistor;

The second end of the second resistor R ₂ is grounded;

The control electrode of the sixth transistor M6 is coupled to the second electrode of the sixth transistor M6, the control electrode of the seventh transistor M7 and the control electrode of the eighth transistor M8, respectively, the first electrode of the sixth transistor M6 is coupled to the power voltage terminal, the first electrode of the seventh transistor M7 and the first electrode of the eighth transistor M8, respectively, and the current flowing through the sixth transistor M6 is the output sampling current I _OUT/k;

The control electrode of the seventh transistor M7 is coupled to the control electrode of the eighth transistor M8, the first electrode of the seventh transistor M7 is coupled to the power voltage terminal and the first electrode of the eighth transistor M8, respectively, the second electrode of the seventh transistor M7 is coupled to the first terminal of the difference circuit 24, the seventh transistor M7 is configured to replicate the output sampling current I _OUT/k flowing through the sixth transistor M6, generate a mirrored current of the output sampling current I _OUT/k flowing through the sixth transistor M6, and provide the output sampling current I _OUT/k from the second electrode to the first terminal of the difference circuit 24;

The first pole of the eighth transistor M8 is coupled to the supply voltage terminal, the second pole of the eighth transistor M8 is coupled to the second terminal of the multiplication circuit 25, the eighth transistor M8 is configured to replicate the output sampling current I _OUT/k flowing through the sixth transistor M6, generate a mirrored current of the output sampling current I _OUT/k flowing through the sixth transistor M6, and provide the output sampling current I _OUT/k from the second pole to the second terminal of the multiplication circuit 25.

The third buffer circuit is configured to convert the input sample voltage V _IN/k to an input sample current I _IN/k and provide the input sample current I _IN/k to the third current mirror circuit;

The third current mirror circuit is configured to replicate the input sample current I _IN/k, generate a mirrored current of the input sample current I _IN/k, and provide the input sample current I _IN/k to the difference circuit 24.

Further, the third buffer circuit includes a third operational amplifier OPA3, a ninth transistor M9, and a third resistor R ₃, and the third current mirror circuit includes a tenth transistor M10 and an eleventh transistor M11, wherein:

The non-inverting input end of the third operational amplifier OPA3 is coupled to the input sampling voltage division V _IN/k end, the inverting input end of the third operational amplifier OPA3 is coupled to the second pole of the ninth transistor M9 and the first end of the third resistor R ₃, respectively, the output end of the third operational amplifier OPA3 is coupled to the control pole of the ninth transistor M9, and the third operational amplifier OPA3 is configured to clamp the input sampling voltage division V _IN/k on the third resistor R3 to obtain an input sampling current I _IN/k;

The first pole of the ninth transistor M9 is coupled to the control pole of the tenth transistor M10, the second pole of the tenth transistor M10 and the control pole of the eleventh transistor M11, respectively; the ninth transistor M9 is an N-type transistor;

The second end of the third resistor R ₃ is grounded; the resistance of the third resistor R ₃ is equal to the resistance of the second resistor R ₂, i.e., R ₃＝R₂;

The control electrode of the tenth transistor M10 is coupled to the second electrode of the tenth transistor M10 and the control electrode of the eleventh transistor M11, respectively, the first electrode of the tenth transistor M10 is coupled to the power voltage terminal and the first electrode of the eleventh transistor M11, respectively, and the current flowing through the tenth transistor M10 is the input sampling current I _IN/k;

the first pole of the eleventh transistor M11 is coupled to the supply voltage terminal, the second pole of the eleventh transistor M11 is coupled to the second terminal of the difference circuit 24, the eleventh transistor M11 is configured to replicate the input sampling current I _IN/k flowing through the tenth transistor M10, generate a mirrored current of the input sampling current I _IN/k flowing through the tenth transistor M10, and provide the input sampling current I _IN/k from the second pole to the second terminal of the difference circuit 24.

Optionally, the difference circuit 24 comprises a fourth current mirror circuit configured to generate a mirrored current of the output sampling current I _OUT/k, the fourth current mirror circuit comprising a twelfth transistor M12 and a thirteenth transistor M13, and a fifth current mirror circuit configured to generate a mirrored current of the input sampling current I _IN/k, the fifth current mirror circuit comprising a fourteenth transistor M14 and a fifteenth transistor M15, wherein:

The control electrode of the twelfth transistor M12 is coupled to the first terminal of the second conversion circuit 22, the first electrode of the twelfth transistor M12 and the control electrode of the thirteenth transistor M13, respectively, the first electrode of the twelfth transistor M12 is coupled to the first terminal of the second conversion circuit 22 and the control electrode of the thirteenth transistor M13, respectively, the second electrode of the twelfth transistor M12 is coupled to the second electrode of the thirteenth transistor M13, the second electrode of the fourteenth transistor M14, the second electrode of the fifteenth transistor M15 and the ground, respectively, wherein the output sampling current I _OUT/k provided through the first terminal of the second conversion circuit 22 flows through the twelfth transistor M12;

The control electrode of the thirteenth transistor M13 is coupled to the first end of the second converting circuit 22, the first electrode of the thirteenth transistor M13 is coupled to the first end of the third converting circuit and the first electrode of the fourteenth transistor M14, respectively, the second electrode of the thirteenth transistor M13 is coupled to the second electrode of the fourteenth transistor M14, the second electrode of the fifteenth transistor M15 and the ground, respectively, and the thirteenth transistor M13 is configured to replicate the output sampling current I _OUT/k flowing through the twelfth transistor M12, generating a mirrored current of the output sampling current I _OUT/k flowing through the twelfth transistor M12;

the control electrode of the fourteenth transistor M14 is coupled to the first terminal of the third conversion circuit, the first electrode of the fourteenth transistor M14 and the control electrode of the fifteenth transistor M15, respectively, the first electrode of the fourteenth transistor M14 is coupled to the first terminal of the third conversion circuit and the control electrode of the fifteenth transistor M15, respectively, the second electrode of the fourteenth transistor M14 is coupled to the second electrode of the fifteenth transistor M15 and the ground, respectively, and the fourteenth transistor M14 is configured to: the current flowing through the fourteenth transistor M14 is a difference current obtained by subtracting the output sampling current I _OUT/k flowing through the thirteenth transistor M13 from the input sampling current I _IN/k supplied through the first terminal of the third conversion circuit;

The first pole of the fifteenth transistor M15 is coupled to the first terminal of the multiplication circuit 25, the second pole of the fifteenth transistor M15 is grounded, the fifteenth transistor M15 is configured to replicate the differential current flowing through the fourteenth transistor M14, generate a mirrored current of the differential current flowing through the fourteenth transistor M14, and provide the differential current from the first pole to the first terminal of the multiplication circuit 25.

Optionally, the multiplication circuit 25 includes a sixth current mirror circuit, a current multiplier Multa, and a seventh current mirror circuit, the sixth current mirror circuit configured to generate a mirror current of the difference current, the sixth current mirror circuit including a sixteenth transistor M16 and a seventeenth transistor M17, the seventh current mirror circuit configured to generate a mirror current of the output current, the seventh current mirror circuit including an eighteenth transistor M18 and a nineteenth transistor M19, wherein:

The control electrode of the sixteenth transistor M16 is coupled to the third terminal of the difference circuit 24, the second electrode of the sixteenth transistor M16 and the control electrode of the seventeenth transistor M17, respectively, the first electrode of the sixteenth transistor M16 is coupled to the power voltage terminal and the first electrode of the seventeenth transistor M17, respectively, the second electrode of the sixteenth transistor M16 is coupled to the third terminal of the difference circuit 24 and the control electrode of the seventeenth transistor M17, respectively, and the current flowing through the sixteenth transistor M16 is a difference current;

The control electrode of the seventeenth transistor M17 is coupled to the third terminal of the difference circuit 24, the first electrode of the seventeenth transistor M17 is coupled to the power supply voltage terminal, the second electrode of the seventeenth transistor M17 is coupled to the first input terminal of the current multiplier Multa, the seventeenth transistor M17 is configured to replicate the difference current flowing through the sixteenth transistor M16, generate a difference current mirror current flowing through the sixteenth transistor M16, and provide the difference current from the second electrode to the first input terminal of the current multiplier Multa;

The current multiplier Multa is configured to determine an output current from the difference current of the first input terminal in1, the first reference current Iref1 of the second input terminal in2, and the output sampling current I _OUT/k of the second output terminal out2, and to supply the output current from the first output terminal out1 to the eighteenth transistor M18; the current multiplier Multa may implement a current value calculation relationship: in1=in2=out1×out2;

The control electrode of the eighteenth transistor M18 is coupled to the first output terminal of the current multiplier Multa, the second electrode of the eighteenth transistor M18 and the control electrode of the nineteenth transistor M19, respectively, the first electrode of the eighteenth transistor M18 is coupled to the power voltage terminal and the first electrode of the nineteenth transistor M19, respectively, the second electrode of the eighteenth transistor M18 is coupled to the first output terminal of the current multiplier Multa and the control electrode of the nineteenth transistor M19, respectively, and the current flowing through the eighteenth transistor M18 is an output current;

a first pole of the nineteenth transistor M19 is coupled to the supply voltage terminal, a second pole of the nineteenth transistor M19 is coupled to the second terminal of the output circuit 26, and the nineteenth transistor M19 is configured to replicate the output current flowing through the eighteenth transistor M18, generate a mirrored current of the output current flowing through the eighteenth transistor M18, and provide the output current from the second pole to the second terminal of the output circuit 26.

Optionally, the output circuit 26 includes a fourth resistor R ₄ and a fifth resistor R ₅, the fourth resistor R ₄ having a resistance m times that of the first resistor R1, the fifth resistor R ₅ having a resistance n times that of the first resistor R1, the parameters m and n being greater than 0, wherein:

The first end of the fourth resistor R ₄ is coupled to the third end of the multiplication circuit 25, the second end of the fourth resistor R ₄ is coupled to the first end of the fifth resistor R ₅ and the second reference current end of the first conversion circuit 21, respectively, the current flowing through the fourth resistor R ₄ is an output current, wherein a clamp voltage Vclamp is output from the first end of the fourth resistor R ₄ to the output end of the error amplifier EA in the voltage-mode loop, and the clamp voltage Vclamp is used for clamping the output voltage to the clamp voltage Vclamp when the output voltage of the error amplifier EA is smaller than the clamp voltage Vclamp;

When the voltage loop turns to load resistor RL jump or the input voltage V _IN of the voltage loop jumps, the clamp voltage Vclamp can be adaptively adjusted; when the output voltage Veao of the error amplifier EA is smaller than the clamp voltage Vclamp, the response time of the voltage mode loop can be greatly shortened by limiting the output voltage Veao of the error amplifier EA to a value near the clamp voltage Vclamp, which is a steady state value.

The first end of the fifth resistor R ₅ is coupled to the second reference current end of the first converting circuit 21, the second end of the fifth resistor R ₅ is grounded, and the current flowing through the fifth resistor R ₅ is the sum of the output current and the second reference current Iref2 at the second reference current end.

The operation principle of the adaptive acceleration circuit suitable for a voltage die loop provided in the embodiments of the present disclosure is described below with reference to an exemplary circuit diagram of the adaptive acceleration circuit shown in fig. 3.

The pin currents of the current multiplier Multa in fig. 3 are related as follows:

Thus, the clamp voltage V _clamp value can be calculated as:

Taking Boost topology in a DC-DC converter as an example, assuming that the loop duty cycle is D, then:

V_clamp＝(m+n)V_refD+nV_ref

According to the actual loop control requirement, for example, the slope and the initial value of the ramp signal Vramp, the trimming design of the clamp voltage Vclamp can be realized through parameters m and n. When the output voltage Veao of the error amplifier EA is lower than the clamping voltage V _clamp in the process of adjusting the loop, the output voltage Veao of the error amplifier EA can be clamped at the clamping voltage V _clamp through a BUFFER structure formed by the operational amplifier OPA and the N-type transistor, so that the loop can recover to a steady state more quickly. For example, when Veao is less than Vclamp, veao may be 0.3V or even directly grounded, in which case the loop recovery speed is slow, so clamping Veao to Vclamp when Veao is less than Vclamp can increase the loop recovery speed.

Because the clamp voltage Vclamp contains the information of the loop duty ratio D, when the loop faces the conditions of jump of the load resistor RL or jump of the loop input voltage V _IN, the clamp voltage Vclamp can be adaptively adjusted, and the output voltage Veao of the error amplifier EA is limited near the final steady-state value, so that the response time of the voltage-mode loop can be greatly shortened. Meanwhile, the value of the clamp voltage Vclamp is reserved for the error amplifier EA to output enough floating space to satisfy that a sufficient slew rate is provided for loop adjustment, when the duty ratio D is 0, vclamp is a constant term nVref, and the value of the constant term nVref is set to a smaller value, for example, may be set to 0.1V, so as to leave space for loop adjustment for the duty ratio D.

From the above description, it can be seen that the present disclosure achieves the following technical effects:

According to the embodiment of the disclosure, through sampling the input voltage V _IN and the output voltage V _OUT of the voltage mode loop in real time, the output voltage Veao output by the error amplifier EA is limited to the clamping voltage Vclamp, the output voltage Veao can be clamped at a system steady-state value of the clamping voltage Vclamp, and other nodes in the whole voltage mode loop are accurately and slowly automatically adjusted by depending on the structure of the voltage mode loop until the voltage mode loop system is stable;

By clamping the output voltage Veao at the clamping voltage Vclamp, the response time of the voltage mode loop is shortened when the voltage mode loop jumps against the load resistor RL or the loop input voltage V _IN jumps, the steady state is recovered more rapidly, and the problem of slower system response speed when the voltage mode loop jumps against different application conditions in the related art is solved;

Because the clamp voltage Vclamp contains the information of the loop duty ratio D, the clamp voltage Vclamp can be adaptively adjusted when the voltage loop jumps against the load resistor RL or the input voltage V _IN of the voltage loop jumps and the like; when the output voltage Veao of the error amplifier EA is smaller than the clamp voltage Vclamp, the response time of the voltage mode loop can be greatly shortened by limiting the output voltage Veao of the error amplifier EA to a value near the clamp voltage Vclamp, which is a steady state value.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.

Further aspects and scope will become apparent from the description provided herein. It is to be understood that various aspects of the application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

Although embodiments of the present disclosure have been described with reference to the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the disclosure, and such modifications and variations fall within the scope as defined by the appended claims.

Claims

1. An adaptive acceleration circuit adapted for use in a voltage-mode loop, the adaptive acceleration circuit comprising: a first conversion circuit, a second conversion circuit, a third conversion circuit, a difference circuit, a multiplication circuit, and an output circuit, wherein:

the first converting circuit is configured to convert a reference voltage into a first reference current and a second reference current, and to supply the first reference current to the multiplying circuit and the second reference current to the output circuit;

the second conversion circuit is configured to convert an output sampling partial pressure of the voltage mode loop into an output sampling current and provide the output sampling current to the difference circuit and the multiplication circuit respectively, wherein the output sampling partial pressure of the voltage mode loop is obtained by sampling an output voltage of the voltage mode loop;

The third conversion circuit is configured to convert an input sampling voltage division of the voltage mode loop into an input sampling current and provide the input sampling current to the difference circuit, wherein the input sampling voltage division of the voltage mode loop is obtained by sampling an input voltage of the voltage mode loop;

The multiplication circuit is configured to determine an output current from the difference current, the first reference current, and the output sampling current, and to provide the output current to the output circuit; and

The output circuit is configured to output a clamping voltage according to the output current and the second reference current, control an output voltage of an output end of the error amplifier in the voltage mode loop, and clamp the output voltage to the clamping voltage.

2. The adaptive acceleration circuit of claim 1, wherein the first conversion circuit comprises a first buffer circuit and a first current mirror circuit, wherein:

The first buffer circuit is configured to convert a reference voltage to a reference current and provide the reference current to the first current mirror circuit;

3. The adaptive acceleration circuit of claim 2, wherein the first buffer circuit comprises a first operational amplifier, a first transistor, and a first resistor, the first current mirror circuit comprises a second transistor, a third transistor, and a fourth transistor, wherein:

The non-inverting input end of the first operational amplifier is coupled with a reference voltage end, the inverting input end of the first operational amplifier is respectively coupled with the second pole of the first transistor and the first end of the first resistor, the output end of the first operational amplifier is coupled with the control pole of the first transistor, and the first operational amplifier is configured to clamp the reference voltage on the first resistor to obtain the reference current;

a first electrode of the first transistor is coupled to the control electrode of the second transistor, the second electrode of the second transistor, the control electrode of the third transistor, and the control electrode of the fourth transistor, respectively;

The control electrode of the third transistor is coupled to the control electrode of the fourth transistor, the first electrode of the third transistor is coupled to the power supply voltage terminal and the first electrode of the fourth transistor respectively, the second electrode of the third transistor is coupled to the second terminal of the multiplication circuit, the third transistor is configured to replicate the reference current flowing through the second transistor to obtain a first reference current, and the first reference current is provided from the second terminal to the second terminal of the multiplication circuit;

The first pole of the fourth transistor is coupled to the power supply voltage terminal, the second pole of the fourth transistor is coupled to the first terminal of the output circuit, the fourth transistor is configured to replicate the reference current flowing through the second transistor, obtain a second reference current, and provide the second reference current from the second pole to the first terminal of the output circuit.

4. The adaptive acceleration circuit of claim 1, wherein the second transformation circuit comprises a second buffer circuit and a second current mirror circuit, wherein:

the second buffer circuit is configured to divide the output sample voltage into the output sample current and provide the output sample current to the second current mirror circuit;

5. The adaptive acceleration circuit of claim 4, wherein the second buffer circuit comprises a second operational amplifier, a fifth transistor, and a second resistor, the second current mirror circuit comprises a sixth transistor, a seventh transistor, and an eighth transistor, wherein:

The non-inverting input end of the second operational amplifier is coupled to an output sampling voltage division end, the inverting input end of the second operational amplifier is respectively coupled to the second pole of the fifth transistor and the first end of the second resistor, the output end of the second operational amplifier is coupled to the control pole of the fifth transistor, and the second operational amplifier is configured to clamp the output sampling voltage division end on the second resistor to obtain the output sampling current;

A first electrode of the fifth transistor is coupled to the control electrode of the sixth transistor, the second electrode of the sixth transistor, the control electrode of the seventh transistor, and the control electrode of the eighth transistor, respectively;

the second end of the second resistor is grounded;

A control electrode of the seventh transistor is coupled to the control electrode of the eighth transistor, a first electrode of the seventh transistor is coupled to the power supply voltage terminal and the first electrode of the eighth transistor, respectively, a second electrode of the seventh transistor is coupled to the first terminal of the difference circuit, and the seventh transistor is configured to replicate the output sampling current flowing through the sixth transistor and to provide the output sampling current from the second electrode to the first terminal of the difference circuit;

a first pole of the eighth transistor is coupled to the supply voltage terminal, a second pole of the eighth transistor is coupled to the second terminal of the multiplication circuit, and the eighth transistor is configured to replicate the output sampling current flowing through the sixth transistor and provide the output sampling current from the second pole to the second terminal of the multiplication circuit.

6. The adaptive acceleration circuit of claim 1, wherein the third transformation circuit comprises a third buffer circuit and a third current mirror circuit, wherein:

the third buffer circuit is configured to convert an input sample voltage division into an input sample current and provide the input sample current to the third current mirror circuit;

the third current mirror circuit is configured to replicate the input sampling current and provide the input sampling current to the difference circuit.

7. The adaptive acceleration circuit of claim 6, wherein the third buffer circuit comprises a third operational amplifier, a ninth transistor, and a third resistor, the third current mirror circuit comprises a tenth transistor and an eleventh transistor, wherein:

The non-inverting input end of the third operational amplifier is coupled to an input sampling voltage division end, the inverting input end of the third operational amplifier is respectively coupled to the second pole of the ninth transistor and the first end of the third resistor, the output end of the third operational amplifier is coupled to the control pole of the ninth transistor, and the third operational amplifier is configured to clamp the input sampling voltage division end on the third resistor to obtain the input sampling current;

a first electrode of the ninth transistor is coupled to the control electrode of the tenth transistor, a second electrode of the tenth transistor, and a control electrode of the eleventh transistor, respectively;

The second end of the third resistor is grounded;

A first pole of the eleventh transistor is coupled to the supply voltage terminal, a second pole of the eleventh transistor is coupled to the second terminal of the difference circuit, and the eleventh transistor is configured to replicate the input sampling current flowing through the tenth transistor and provide the input sampling current from the second pole to the second terminal of the difference circuit.

8. The adaptive acceleration circuit of claim 1, wherein the difference circuit comprises a fourth current mirror circuit and a fifth current mirror circuit, the fourth current mirror circuit comprising a twelfth transistor and a thirteenth transistor, the fifth current mirror circuit comprising a fourteenth transistor and a fifteenth transistor, wherein:

The control electrode of the twelfth transistor is coupled to the first end of the second conversion circuit, the first electrode of the twelfth transistor and the control electrode of the thirteenth transistor, respectively, the first electrode of the twelfth transistor is coupled to the first end of the second conversion circuit and the control electrode of the thirteenth transistor, respectively, and the second electrode of the twelfth transistor is coupled to the second electrode of the thirteenth transistor, the second electrode of the fourteenth transistor, the second electrode of the fifteenth transistor and the ground, respectively, wherein the output sampling current provided through the first end of the second conversion circuit flows through the twelfth transistor;

A control electrode of the thirteenth transistor is coupled to the first end of the second conversion circuit, the first electrode of the thirteenth transistor is coupled to the first end of the third conversion circuit and the first electrode of the fourteenth transistor, the second electrode of the thirteenth transistor is coupled to the second electrode of the fourteenth transistor, the second electrode of the fifteenth transistor and the ground, respectively, and the thirteenth transistor is configured to replicate the output sampling current flowing through the twelfth transistor;

a control electrode of the fourteenth transistor is coupled to the first terminal of the third conversion circuit, the first electrode of the fourteenth transistor and the control electrode of the fifteenth transistor, respectively, the first electrode of the fourteenth transistor is coupled to the first terminal of the third conversion circuit and the control electrode of the fifteenth transistor, respectively, the second electrode of the fourteenth transistor is coupled to the second electrode of the fifteenth transistor and the ground, respectively, the fourteenth transistor is configured to: the current flowing through the fourteenth transistor is a difference current obtained by subtracting the output sampling current flowing through the thirteenth transistor from the input sampling current supplied through the first terminal of the third conversion circuit;

A first pole of the fifteenth transistor is coupled to the first end of the multiplication circuit, a second pole of the fifteenth transistor is grounded, and the fifteenth transistor is configured to replicate the differential current flowing through the fourteenth transistor and provide the differential current from the first pole to the first end of the multiplication circuit.

9. The adaptive acceleration circuit of claim 1, wherein the multiplication circuit comprises a sixth current mirror circuit comprising a sixteenth transistor and a seventeenth transistor, a current multiplier, and a seventh current mirror circuit comprising an eighteenth transistor and a nineteenth transistor, wherein:

the control electrode of the sixteenth transistor is coupled to the third end of the difference circuit, the second electrode of the sixteenth transistor and the control electrode of the seventeenth transistor respectively, the first electrode of the sixteenth transistor is coupled to the power supply voltage end and the first electrode of the seventeenth transistor respectively, and the second electrode of the sixteenth transistor is coupled to the third end of the difference circuit and the control electrode of the seventeenth transistor respectively;

A control electrode of the seventeenth transistor is coupled to the third terminal of the difference circuit, a first electrode of the seventeenth transistor is coupled to the power supply voltage terminal, a second electrode of the seventeenth transistor is coupled to the first input terminal of the current multiplier, and the seventeenth transistor is configured to replicate the difference current flowing through the sixteenth transistor and supply the difference current from the second electrode to the first input terminal of the current multiplier;

The control electrode of the eighteenth transistor is coupled to the first output end of the current multiplier, the second electrode of the eighteenth transistor and the control electrode of the nineteenth transistor respectively, the first electrode of the eighteenth transistor is coupled to the power supply voltage end and the first electrode of the nineteenth transistor respectively, and the second electrode of the eighteenth transistor is coupled to the first output end of the current multiplier and the control electrode of the nineteenth transistor respectively;

10. The adaptive acceleration circuit of claim 1, wherein the output circuit comprises a fourth resistor and a fifth resistor, wherein:

The first end of the fourth resistor is coupled to the third end of the multiplication circuit, the second end of the fourth resistor is coupled to the first end of the fifth resistor and the second reference current end of the first conversion circuit respectively, and the current flowing through the fourth resistor is output current, wherein a clamping voltage is output from the first end of the fourth resistor to the output end of the error amplifier in the voltage mode loop, and the clamping voltage is used for clamping the output voltage to the clamping voltage when the output voltage of the error amplifier is smaller than the clamping voltage;