CN114552991A - DC-DC power supply architecture capable of realizing rapid switching of output power and control method thereof - Google Patents
DC-DC power supply architecture capable of realizing rapid switching of output power and control method thereof Download PDFInfo
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- CN114552991A CN114552991A CN202210273571.7A CN202210273571A CN114552991A CN 114552991 A CN114552991 A CN 114552991A CN 202210273571 A CN202210273571 A CN 202210273571A CN 114552991 A CN114552991 A CN 114552991A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Power Engineering (AREA)
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Abstract
The invention relates to a DC-DC power supply framework capable of realizing rapid switching of output power and a control method thereof. When the output voltage changes from high to low, the current flowing through the feedback resistor increases instantly, so that the node voltage of the feedback voltage is raised instantly, and when the feedback voltage is larger than a second threshold voltage and larger than a first threshold voltage, the output of the third comparator increases, the first NMOS transistor is controlled to pull down, and the feedback voltage of the Vfb2 node is pulled to the reference voltage Vref. According to the invention, the jump adjustment of the output power can be accelerated by setting the priority of the control signal Vctrl to be higher than that of the low-power-consumption mode enabling signal, so that the technical problem of long establishment time in the output voltage switching process of the traditional DC-DC power supply framework is solved, the stabilization time after the output voltage jumps is shortened, and the rapid switching of the output power is realized.
Description
Technical Field
The present invention relates to a DC-DC power architecture and a control method thereof, and more particularly, to a DC-DC power architecture capable of realizing fast switching of output power and a control method thereof.
Background
Referring to fig. 1, taking a Buck conversion circuit (Buck circuit) as an example, a first variable output power DC-DC power architecture adopts a working principle that, on the basis of a conventional DC-DC power architecture, a digital-to-analog conversion unit (DAC), i.e., a first digital-to-analog conversion unit DAC1 in fig. 1, is added, so that when a system detects that an output voltage Vout needs to be adjusted to change power supply of a power system to a load in a certain mode, a central control unit can issue an instruction through a digital interface to modify a DAC codeword stored in a register, thereby modifying a first reference voltage Vref1 at an output end of a first digital-to-analog conversion unit DAC1, and then a loop achieves a purpose of changing a power output voltage under a negative feedback adjustment effect.
FIG. 1 omits peripheral assist circuitry; the Logic control unit Logic is a control circuit such as PWM/PFM/COT, and the like, and EA is an error amplifier used for improving loop gain; the first comparator comp1 is a main loop comparator to complete the negative feedback loop regulation function; when the load is light, the Buck circuit efficiency is reduced, the output voltage Vout ripple is increased, and the feedback voltage Vfb fluctuation is also increased.
To improve efficiency, a second comparator comp2 may be added on the basis of the first variable output power DC-DC power supply architecture, and then its input reference voltage is set to a second reference voltage Vref2, where the second reference voltage Vref2 > the first reference voltage Vref 1. When the feedback voltage Vfb > the second reference voltage Vref2, the Logic control unit Logic is controlled by the comparison result to close circuits of other power consuming parts except the second comparator comp2 in the loop. When the output voltage decreases, causing the feedback voltage Vfb to drop below the second reference voltage Vref2, the system loop is again established. Through the dynamic adjustment, the purpose of improving the system efficiency under the condition of light load is achieved, and the mode is called as a Low power consumption mode (Low-Iq mode). At this time, the Driver output of the driving unit maintains the output of the MOS power transistor in a floating state.
It should be noted that if the low power consumption mode is added, in order to improve efficiency in a light load state with different output voltages, the second reference voltage Vref2 needs to be able to follow the first reference voltage Vref1 in the same direction, which requires the additional addition of the second digital-to-analog conversion unit DAC2, resulting in a waste of circuit board or integrated chip area. This disadvantage is exacerbated when the number of DAC bits is large.
In addition, the DC-DC power architecture has a disadvantage to be overcome: because the Buck loop is complex, when the DC-DC power supply architecture performs dynamic output switching, the output voltage Vout changes in a relatively wide range, which requires the digital-to-analog conversion unit to control the corresponding reference voltage to change in a relatively wide range, which increases the design complexity of the comparator to a certain extent, for example, the requirement for the input common mode voltage range is more strict; the drift of the static working point can also influence the loop stability of the power supply system under different output conditions; a series of negative effects are brought on design simulation.
The module configuration of the second variable output power DC-DC power supply architecture differs from the first architecture in that the second architecture places the digital-to-analog conversion unit DAC, which regulates the output voltage Vout, at the output feedback resistance, see fig. 2.
Compared with the first architecture, the architecture has two main advantages:
1) the framework can achieve two purposes of dynamic change of output voltage and low power consumption mode tracking judgment only by one digital-to-analog conversion unit DAC.
2) The input reference voltage of the used comparator is a fixed value, and the comparator design and the loop stability verification are easy.
However, this architecture has one disadvantage: when the resistance value of the feedback resistor Rf is changed from large to small by the DAC codeword, due to the slow change rate of the output voltage Vout1, at the instant of DAC state switching of the digital-to-analog conversion unit, a transient current flowing through the gain resistor Rg is generated at two ends of the feedback resistor Rf, so that a large overshoot exists in the node voltage of the feedback voltage Vfb1, which is a high-resistance node, which causes the node voltage recovery process of the feedback voltage Vfb1 to be too long, and thus, the stabilization time of the output voltage Vout1 when switched from high to low is long. Worse, such overshoot of the feedback voltage Vfb1 tends to be larger than the second reference voltage Vref2, which triggers the aforementioned low power consumption mode, i.e., actively turning off the loop regulation, causing the loop to lose the NMOS power transistor pull-down regulation capability, so that the settling time during switching of the output voltage Vout1 is deteriorated to an unacceptable level.
When the output voltage Vout1 switches to a high voltage, the system will not enter a low power consumption mode fundamentally, and although the feedback voltage Vfb1 is still a high-resistance node, the system settling time is rather short under the action of loop negative feedback. Therefore, only the digital-to-analog conversion unit needs to be considered to control the output voltage down-jump process, and in the process, how to eliminate or reduce the influence caused by the deficiency does not hinder the normal entering of the low power consumption mode under light load, and the setup time of the system power down-jump can meet the performance requirement, so that the problem that the architecture needs to solve is solved.
Disclosure of Invention
The invention aims to provide a DC-DC power supply framework capable of realizing rapid switching of output power and a control method thereof, which solve the technical problem of long establishment time in the switching process of the output voltage Vout1 of the traditional DC-DC power supply framework, can shorten the stabilization time after the output voltage Vout1 jumps, and realize rapid switching of the output power.
The technical solution of the invention is as follows:
a DC-DC power supply framework capable of realizing rapid switching of output power is characterized by comprising a driving module Driver, a switch module, an LC module, a sampling module and a feedback control module which are sequentially connected and form a loop; the switch module comprises a PMOS power tube and an NMOS power tube which are connected in sequence; the sampling module comprises a digital-to-analog conversion unit DAC, and a feedback resistor Rf and a gain resistor Rg which are connected in series; the feedback resistor Rf is a digital adjustable resistor, and the resistance value of the feedback resistor Rf is controlled and connected with the output end of the DAC (digital-to-analog conversion) unit; the feedback control module comprises a first comparison unit, a second comparison unit, a first Logic control unit Logic and a pull-down unit; the output end of the first Logic control unit Logic is connected with the input end of the Driver of the driving module and is used for controlling the Driver of the driving module to work; the first comparing unit comprises an error amplifier EA and a first comparator comp 1; the positive input end of the error amplifier EA is connected with a first reference voltage Vref1, and the negative input end of the error amplifier EA is connected with the connection point of a feedback resistor Rf and a gain resistor Rg; the positive input end of the first comparator comp1 is connected with the connection point of the feedback resistor Rf and the gain resistor Rg, the negative input end thereof is connected with the output end of the error amplifier EA, and the output end thereof is connected with one input end of the first logic control unit; the second comparing unit comprises a second comparator comp2, an inverter and a nor gate; the positive input end of the second comparator comp2 is connected with the connection point of the feedback resistor Rf and the gain resistor Rg, the negative input end thereof is connected with the first threshold voltage Vth _1, and the output end thereof is connected with one input end of the nor gate after passing through the inverter; the other input end of the NOR gate is connected with a control signal Vctrl, and the output end of the NOR gate is connected with the other input end of the first logic control unit; the pull-down unit comprises a third comparator comp3, a Delay unit Delay and a pull-down NMOS tube NMOS 1; the positive input end of the third comparator comp3 is connected with the connection point of the feedback resistor Rf and the gain resistor Rg, the negative input end thereof is connected with the second threshold voltage Vth _2, and the output end thereof outputs a control signal Vctrl after being delayed by the delay unit; the control signal Vctrl is connected with the grid electrode of a pull-down NMOS tube NMOS 1; the drain electrode of the pull-down NMOS tube NMOS1 is connected with the connection point of the feedback resistor Rf and the gain resistor Rg, and the source electrode of the pull-down NMOS tube NMOS1 is connected with a reference voltage Vref; the first reference voltage Vref1 is a fixed value; the first threshold voltage Vth _1 is a fixed value; the second threshold voltage Vth _2 is a fixed value, and the second threshold voltage Vth _2 > the first threshold voltage Vth _1 > the reference voltage Vref > the first reference voltage Vref 1.
The reference voltage Vref is Vref1+ B, where B is 5-20mV, preferably 10 mV.
The invention also provides a control method of the variable output power DC-DC power supply architecture, which comprises the following steps:
the driving module controls the on-off of the switch module;
the switch module controls the power supply to provide the output voltage Vout2 to the load RL in one half cycle, and the capacitor Cs in the LC module provides the output voltage Vout2 to the load RL in the other half cycle; when the output voltage Vout2 needs to be adjusted to change the power supply of the power supply to the load RL, the central control unit adjusts the resistance value of the feedback resistor Rf in the sampling module through the digital-to-analog conversion unit DAC, and correspondingly adjusts the magnitude of the feedback voltage Vfb 2; a first comparator comp1 in the feedback control module compares the feedback voltage Vfb2 with a first reference voltage Vref1, a second comparator comp2 compares the feedback voltage Vfb2 with a first threshold voltage Vth _1, and a third comparator comp3 compares the feedback voltage Vfb2 with a second threshold voltage Vth _ 2;
when the feedback voltage Vfb2 is greater than the first reference voltage Vref1, the first comparator comp1 outputs a corresponding negative feedback control signal, and the driving module drives the loop to adjust the output voltage Vout2 under the action of the negative feedback control signal;
when the feedback voltage Vfb2 is greater than the first threshold voltage Vth _1, the second comparator comp2 outputs a corresponding negative feedback control signal, and the driving module closes other power consuming circuits in the power architecture loop except the second comparing unit and the third comparing unit under the action of the negative feedback control signal;
when the feedback voltage Vfb2 is greater than the second threshold voltage Vth _2, the control signal Vctrl output by the third comparator comp3 after being delayed by the delay unit controls the pull-down NMOS1 to pull down, the feedback voltage Vfb2 is pulled down to the reference voltage Vref, the power supply architecture loop is rapidly recovered, and the output power jump adjustment is accelerated by loop negative feedback; the reference voltage Vref is greater than the first reference voltage Vref1 and less than the first threshold voltage Vth _ 1.
The invention has the beneficial effects that:
according to the invention, the jump adjustment of the output power can be accelerated only by adding a conventional comparator, a delay unit Td and a pull-down NMOS transistor NMOS1 for pull-down on the basis of a conventional DC-DC power supply structure and setting the priority of a control signal Vctrl to be higher than that of a low-power-consumption mode enabling signal when the control signal Vctrl is heightened, the implementation method is simple, and the chip structure is simpler. The invention is suitable for various DC-DC power supply architectures.
The invention solves the technical problem of long establishment time in the switching process of the output voltage Vout1 of the traditional DC-DC power supply framework, can shorten the stabilization time of the output voltage Vout1 after jumping and realizes the quick switching of the output power.
Drawings
FIG. 1 is a schematic diagram of a first prior art variable output DC-DC power supply architecture;
FIG. 2 is a schematic diagram of a second prior art variable output DC-DC power supply architecture;
FIG. 3 is a schematic diagram of a DC-DC power supply architecture capable of rapidly switching output power according to the present invention;
FIG. 4 is a schematic diagram of the relationship between the active phases and the reference voltages of the comparators in accordance with the present invention;
FIG. 5 is a diagram illustrating a comparison between the waveform effects of the key nodes of the conventional power supply architecture and the DC-DC power supply architecture capable of rapidly switching the output power according to the present invention.
Detailed Description
The invention relates to a DC-DC power supply framework capable of realizing rapid switching of output power, which is shown in figure 3 and is characterized by comprising a driving module Driver, a switch module, an LC module, a sampling module and a feedback control module which are sequentially connected and form a loop; the switch module comprises a PMOS power tube and an NMOS power tube which are connected in sequence; the sampling module comprises a digital-to-analog conversion unit DAC, and a feedback resistor Rf and a gain resistor Rg which are connected in series; the feedback resistor Rf is a digital adjustable resistor, and the resistance value of the feedback resistor Rf is controlled and connected with the output end of the DAC (digital-to-analog conversion) unit; the feedback control module comprises a first comparison unit, a second comparison unit, a first Logic control unit Logic and a pull-down unit; the output end of the first Logic control unit Logic is connected with the input end of the Driver of the driving module and is used for controlling the Driver of the driving module to work; the first comparison unit comprises an error amplifier EA and a first comparator comp 1; the positive input end of the error amplifier EA is connected with a first reference voltage Vref1, and the negative input end of the error amplifier EA is connected with the connection point of a feedback resistor Rf and a gain resistor Rg; the positive input end of the first comparator comp1 is connected with the connection point of the feedback resistor Rf and the gain resistor Rg, the negative input end thereof is connected with the output end of the error amplifier EA, and the output end thereof is connected with one input end of the first logic control unit; the second comparing unit comprises a second comparator comp2, an inverter and a nor gate; the positive input end of the second comparator comp2 is connected with the connection point of the feedback resistor Rf and the gain resistor Rg, the negative input end thereof is connected with the first threshold voltage Vth _1, and the output end thereof is connected with one input end of the nor gate after passing through the inverter; the other input end of the NOR gate is connected with the control signal Vctrl, and the output end of the NOR gate is connected with the other input end of the first logic control unit; the pull-down unit comprises a third comparator comp3, a Delay unit Delay and a pull-down NMOS tube NMOS 1; the positive input end of the third comparator comp3 is connected with the connection point of the feedback resistor Rf and the gain resistor Rg, the negative input end thereof is connected with the second threshold voltage Vth _2, and the output end thereof outputs a control signal Vctrl after being delayed by the delay unit; the control signal Vctrl is connected with the grid electrode of a pull-down NMOS tube NMOS 1; the drain of the pull-down NMOS transistor NMOS1 is connected with the connection point of the feedback resistor Rf and the gain resistor Rg, and the source of the pull-down NMOS transistor NMOS1 is connected with the reference voltage Vref; the first reference voltage Vref1 is a fixed value; the first threshold voltage Vth _1 is a fixed value; the second threshold voltage Vth _2 is a fixed value, and the second threshold voltage Vth _2 > the first threshold voltage Vth _1 > the reference voltage Vref > the first reference voltage Vref 1.
Preferably, the reference voltage Vref is Vref1+ B, where B is 5 to 20mV, preferably 10 mV.
When the output voltage Vout2 changes from high to low, the current flowing through the feedback resistor Rf increases instantaneously, so that the node voltage of the feedback voltage Vfb2 is raised instantaneously, and when the feedback voltage Vfb2 > the second threshold voltage Vth _2 > the first threshold voltage Vth _1, the output of the third comparator comp3 becomes high, the first NMOS transistor NMOS1 in fig. 3 is controlled to pull down, so as to pull the feedback voltage of the Vfb2 node (the connection point of the feedback resistor Rf and the gain resistor Rg) to the reference voltage Vref (the first reference voltage Vref1 < the reference voltage Vref < the first threshold voltage Vth _1, Vref is equal to Vref1+ B, and B takes 5-20mV, preferably 10 mV). Because in the normal light load state, the system can temporarily turn off the PMOS power transistor and the NMOS power transistor in the switching circuit at the same time when the feedback voltage Vfb2 > the first threshold voltage Vth _1, so as to improve the system efficiency. During this period, the loop is disconnected, and the feedback voltage Vfb2 is pulled back to the reference voltage Vref by the output of the third comparator comp3 (the reference voltage Vref < the first threshold voltage Vth _1, and the reference voltage Vref should have the ability to absorb the feedback voltage Vfb2 and instantaneously accumulate excessive charges), so that the function of the second comparator comp2 can be directly skipped, the pseudo low power consumption mode is forcibly eliminated, the loop is rapidly recovered, and the output power jump adjustment is accelerated by loop negative feedback. In fig. 3, only a conventional comparator, a delay unit Td, and a pull-down NMOS1 for pull-down are needed to be added, and the priority of setting the control signal Vctrl to be high is higher than that of the low power consumption mode enable signal, so that the implementation method is simple.
The invention also provides a control method of the variable output power DC-DC power supply architecture, which comprises the following steps:
the driving module controls the on-off of the switch module;
the switch module controls the power supply to provide the output voltage Vout2 to the load RL in one half cycle, and the capacitor Cs in the LC module provides the output voltage Vout2 to the load RL in the other half cycle; when the output voltage Vout2 needs to be adjusted to change the power supply of the power supply to the load RL, the central control unit adjusts the resistance value of the feedback resistor Rf in the sampling module through the digital-to-analog conversion unit DAC, and correspondingly adjusts the magnitude of the feedback voltage Vfb 2; a first comparator comp1 in the feedback control module compares the feedback voltage Vfb2 with a first reference voltage Vref1, a second comparator comp2 compares the feedback voltage Vfb2 with a first threshold voltage Vth _1, and a third comparator comp3 compares the feedback voltage Vfb2 with a second threshold voltage Vth _ 2;
when the feedback voltage Vfb2 is greater than the first reference voltage Vref1, the first comparator comp1 outputs a corresponding negative feedback control signal, and the driving module drives the loop to adjust the output voltage Vout2 under the action of the negative feedback control signal;
when the feedback voltage Vfb2 is greater than the first threshold voltage Vth _1, the second comparator comp2 outputs a corresponding negative feedback control signal, and the driving module closes other power consuming circuits in the power architecture loop except the second comparing unit and the third comparing unit under the action of the negative feedback control signal;
when the feedback voltage Vfb2 is greater than the second threshold voltage Vth _2, the control signal Vctrl output by the third comparator comp3 after being delayed by the delay unit controls the pull-down NMOS1 to pull down, the feedback voltage Vfb2 is pulled down to the reference voltage Vref, the power supply architecture loop is rapidly recovered, and the output power jump adjustment is accelerated by loop negative feedback; the reference voltage Vref is greater than the first reference voltage Vref1 and less than the first threshold voltage Vth _ 1.
Fig. 4 is an explanatory diagram of the action phases of the three comparators. FIG. 5 shows the simulation test result of the actual circuit, and it can be seen that the settling time of the output voltage Vout2 after the transition is reduced from 380us to about 37us after the control logic is added; obviously, the invention only needs to add a conventional comparator, a delay unit Td and a pull-down NMOS transistor NMOS1 for pull-down on the basis of the conventional DC-DC power supply structure, and sets the priority of the control signal Vctrl when becoming high to be higher than the low power consumption mode enabling signal, thereby accelerating the jump adjustment of the output power, effectively solving the technical problem of long establishment time in the switching process of the output voltage Vout1 of the conventional DC-DC power supply structure, shortening the stabilization time of the output voltage Vout1 after jumping, realizing the fast switching of the output power, having simple realization method and simpler chip structure.
Claims (5)
1. A DC-DC power architecture capable of realizing fast switching of output power is characterized in that:
the system comprises a driving module Driver, a switch module, an LC module, a sampling module and a feedback control module which are sequentially connected and form a loop;
the switch module comprises a PMOS power tube and an NMOS power tube which are connected in sequence;
the sampling module comprises a digital-to-analog conversion unit DAC, and a feedback resistor Rf and a gain resistor Rg which are connected in series; the feedback resistor Rf is a digital adjustable resistor, and the resistance value of the feedback resistor Rf is controlled and connected with the output end of the DAC (digital-to-analog conversion) unit;
the feedback control module comprises a first comparison unit, a second comparison unit, a first Logic control unit Logic and a pull-down unit;
the output end of the first Logic control unit Logic is connected with the input end of the Driver of the driving module and is used for controlling the Driver of the driving module to work;
the first comparing unit comprises an error amplifier EA and a first comparator comp 1; the positive input end of the error amplifier EA is connected with a first reference voltage Vref1, and the negative input end of the error amplifier EA is connected with the connection point of a feedback resistor Rf and a gain resistor Rg; the positive input end of the first comparator comp1 is connected with the connection point of the feedback resistor Rf and the gain resistor Rg, the negative input end thereof is connected with the output end of the error amplifier EA, and the output end thereof is connected with one input end of the first logic control unit; the second comparing unit comprises a second comparator comp2, an inverter and a nor gate; the positive input end of the second comparator comp2 is connected with the connection point of the feedback resistor Rf and the gain resistor Rg, the negative input end thereof is connected with the first threshold voltage Vth _1, and the output end thereof is connected with one input end of the nor gate after passing through the inverter; the other input end of the NOR gate is connected with the control signal Vctrl, and the output end of the NOR gate is connected with the other input end of the first logic control unit;
the pull-down unit comprises a third comparator comp3, a Delay unit Delay and a pull-down NMOS tube NMOS 1; the positive input end of the third comparator comp3 is connected with the connection point of the feedback resistor Rf and the gain resistor Rg, the negative input end thereof is connected with the second threshold voltage Vth _2, and the output end thereof outputs a control signal Vctrl after being delayed by the delay unit; the control signal Vctrl is connected with the grid electrode of a pull-down NMOS tube NMOS 1; the drain of the pull-down NMOS transistor NMOS1 is connected with the connection point of the feedback resistor Rf and the gain resistor Rg, and the source of the pull-down NMOS transistor NMOS1 is connected with the reference voltage Vref;
the first reference voltage Vref1 is a fixed value; the first threshold voltage Vth _1 is a fixed value; the second threshold voltage Vth _2 is a fixed value, and the second threshold voltage Vth _2 > the first threshold voltage Vth _1 > the reference voltage Vref > the first reference voltage Vref 1.
2. The DC-DC power architecture of claim 1, wherein: and the reference voltage Vref is Vref1+ B, wherein B takes 5-20 mV.
3. The DC-DC power architecture of claim 2, wherein: the value of B is 10 mV.
4. A control method for a DC-DC power supply architecture capable of realizing rapid switching of output power is characterized by comprising the following steps:
the driving module controls the on-off of the switch module;
the output voltage of the switch module provides an output voltage Vout2 to a load RL after passing through the LC module;
when the output voltage Vout2 needs to be adjusted to change the power supply of the power supply to the load RL, the central control unit adjusts the resistance value of the feedback resistor Rf in the sampling module through the digital-to-analog conversion unit DAC, and correspondingly adjusts the magnitude of the feedback voltage Vfb 2; a first comparator comp1 in the feedback control module compares the feedback voltage Vfb2 with a first reference voltage Vref1, a second comparator comp2 compares the feedback voltage Vfb2 with a first threshold voltage Vth _1, and a third comparator comp3 compares the feedback voltage Vfb2 with a second threshold voltage Vth _ 2;
when the feedback voltage Vfb2 is greater than the first reference voltage Vref1 and less than the first threshold voltage Vth _1, the first comparator comp1 outputs a corresponding negative feedback control signal, and the driving module drives the loop to adjust the output voltage Vout2 under the action of the negative feedback control signal;
when the feedback voltage Vfb2 is greater than the first threshold voltage Vth _1 and less than the second threshold voltage Vth _2, the first comparator comp1 outputs a low level; the second comparator comp2 outputs a low power consumption mode enable signal, and the driving module turns off other power consuming circuits in the power architecture loop except for the second comparing unit and the third comparing unit under the action of the low power consumption mode enable signal;
when the feedback voltage Vfb2 is greater than the second threshold voltage Vth _2, both the first comparator comp1 and the second comparator comp2 output a low level; the control signal Vctrl output by the third comparator comp3 becomes high, after the delay of the delay unit, the pull-down NMOS tube NMOS1 is controlled to pull down, the feedback voltage Vfb2 is pulled down to the reference voltage Vref, the power supply architecture loop is rapidly recovered, and the output power jump adjustment is accelerated by loop negative feedback; the reference voltage Vref is greater than the first reference voltage Vref1 and less than the first threshold voltage Vth _ 1.
5. The control method of the DC-DC power architecture capable of realizing the fast switching of the output power according to claim 4, characterized in that: the control signal Vctrl output by the third comparator comp3 has higher priority than the low power mode enable signal when going high.
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