CN115440683A - Double-core parallel high-power device packaging structure and preparation method thereof - Google Patents
Double-core parallel high-power device packaging structure and preparation method thereof Download PDFInfo
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- CN115440683A CN115440683A CN202211135091.0A CN202211135091A CN115440683A CN 115440683 A CN115440683 A CN 115440683A CN 202211135091 A CN202211135091 A CN 202211135091A CN 115440683 A CN115440683 A CN 115440683A
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- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
- H01L25/074—Stacked arrangements of non-apertured devices
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses a double-core parallel high-power device packaging structure and a preparation method thereof, and solves the problems of large mounting area and poor heat dissipation performance of the conventional packaging structure. The specific technical scheme is as follows: one end of a source metal sheet is connected with a lead frame foot rest welding area through a bonding layer, two side faces of the other end of the source metal sheet are respectively connected with source electrodes of two chips through the bonding layer, one end of a grid metal sheet is connected with the lead frame foot rest welding area through the bonding layer, two side faces of the other end of the grid metal sheet are respectively connected with two grids through the bonding layer, a drain electrode of one chip is connected with a drain metal sheet through the bonding layer, a drain electrode of the other chip is connected with a lead frame base island area through the bonding layer, and the drain metal sheet is connected with the lead frame base island area through the frame bonding layer; and the periphery of all the structures is filled and wrapped by plastic packaging material. The invention adopts a double-core overlapping structure, reduces the volume and the installation area of the device, and adopts a double-sided heat dissipation structure to increase a heat dissipation channel and improve the heat dissipation performance.
Description
Technical Field
The invention belongs to the technical field of power electronic devices, and relates to a double-core parallel high-power device packaging structure and a preparation method thereof.
Background
The packaging function is to provide electrical connection and mechanical bearing for the chip, so that the chip is convenient to operate and use, a standard mounting structure and size are provided for a user of a large-scale integrated circuit, the chip is prevented from being corroded by external force, scratches, water vapor or other harmful gases, and sometimes a plurality of chips can be packaged in the same packaging structure, so that the integrated circuit chip can play a normal function, and the high stability and reliability of the integrated circuit chip are ensured.
With the continuous development of consumer electronics, communication and other industries, the whole machine also changes towards multifunction, high power and miniaturization. Accordingly, the integration level and current capability of the integrated circuit are required to be higher and higher, and accordingly, the packaging density is required to be higher and higher, the number of leads is required to be higher and higher, the size is smaller and smaller, the weight is lighter and lighter, and the scientificity and rationality of the packaging structure directly influence the quality of the integrated circuit.
The existing double-core parallel high-power device packaging structure mainly adopts a plane structure, and the area required by installation is large. When the power device works, heat can be generated; high power semiconductor devices generate more heat due to higher power. For a power device, if the generated heat cannot be efficiently transferred to the external environment in time, the working performance of the semiconductor device will be greatly affected, and even the failure will be caused.
Disclosure of Invention
The invention aims to provide a double-core parallel power device packaging structure and a preparation method thereof, and solves the problems of large area required by double-core packaging device installation and poor heat dissipation performance of the conventional double-core parallel power device packaging structure.
The specific technical scheme of the invention is as follows:
a dual-chip parallel power device packaging structure comprises a first chip, a second chip, a lead frame, a source metal sheet, a grid metal sheet and a drain metal sheet, wherein the lead frame comprises a lead frame basal island region and a lead frame foot rest welding region; and the periphery of all the structures is filled and wrapped by plastic packaging material.
The first chip comprises a first chip source electrode, a first chip grid electrode and a first chip drain electrode, the first chip source electrode is connected with the source electrode metal sheet through a first source electrode bonding layer, the first chip grid electrode is connected with the grid electrode metal sheet through a first grid electrode bonding layer, and the first chip drain electrode is connected with the drain electrode metal sheet through a first drain electrode bonding layer;
the second chip comprises a second chip source electrode, a second chip grid electrode and a second chip drain electrode, the second chip source electrode is connected with the source electrode metal sheet through a second source electrode bonding layer, the second chip grid electrode is connected with the grid electrode metal sheet through a second grid electrode bonding layer, and the second chip drain electrode is connected with the lead frame base island region through a second drain electrode bonding layer.
A manufacturing method of a dual-chip parallel power device packaging structure is characterized in that a drain electrode of a second chip is combined with a lead frame base island region, a source electrode of the second chip is combined with a source electrode metal sheet, a grid electrode of the second chip is combined with a grid electrode metal sheet, the source electrode metal sheet is combined with the lead frame foot rest welding region, the grid electrode metal sheet is combined with the lead frame foot rest welding region, a source electrode of the first chip is combined with the source electrode metal sheet, the grid electrode of the first chip is combined with the grid electrode metal sheet, a drain electrode of the first chip is combined with the drain electrode metal sheet, the drain electrode metal sheet is combined with the lead frame base island region, all the combining processes use a bonding layer structure, and finally plastic packaging materials are used for filling and wrapping the components, so that the drain electrode metal sheet, the lead frame base island region and the lead frame foot rest welding region are exposed on the surface.
The double-core parallel power device packaging structure and the preparation method thereof adopt the double-core overlapping structure, reduce the size of the device and the area required by installation, and adopt the double-side heat dissipation structure, increase the heat dissipation channel, are beneficial to the heat dissipation of the device and improve the heat dissipation performance.
Drawings
Fig. 1 is a longitudinal sectional view of a package structure of a dual-core parallel power device according to the present invention;
fig. 2 is a plan view of the internal structure of the power device package structure;
fig. 3 is a top plan view of a dual core parallel power device package structure in accordance with the present invention;
fig. 4 is a plan view of the bottom structure of the package structure of the dual-core parallel power device according to the present invention.
In the figure: 10-molding compound, 21-drain metal sheet, 22-leadframe base island region, 23-source metal sheet, 24-gate metal sheet, 25-leadframe foot pad, 31-first drain bonding layer, 32-first gate bonding layer, 33-first source bonding layer, 34-drain frame bonding layer, 35-second source bonding layer, 36-second gate bonding layer, 37-second drain bonding layer, 38-gate frame bonding layer, 39-source frame bonding layer, 41-first chip, 42-second chip, 421-second chip source, 422-second chip gate.
Detailed Description
For the purpose of promoting an understanding of the present invention, the following detailed description of the embodiments of the present invention is provided in conjunction with the accompanying drawings, which are provided for the purpose of illustration only and are not intended to limit the scope of the present invention.
As shown in fig. 1 to 4, the invention discloses a dual-chip parallel power device package structure, which includes a first chip 41, a second chip 42, a lead frame, a source metal sheet 23, a gate metal sheet 24, and a drain metal sheet 21, wherein the lead frame includes a lead frame island region 22 and a lead frame foot rest welding region 25.
One end of the source metal piece 23 is connected to the lead frame foot rest land 25 through a source frame bonding layer 39, the other two side faces are respectively connected to the sources of the first chip 41 and the second chip 42 through bonding layers, one end of the gate metal piece 24 is connected to the lead frame foot rest land 25 through a gate frame bonding layer 38, the other two side faces are respectively connected to the gates of the first chip 41 and the second chip 42 through bonding layers, the drain of the first chip 41 is connected to the drain metal piece 21 through a first drain bonding layer 31, the drain of the second chip 42 is connected to the lead frame island region 22 through a second drain bonding layer 37, and the drain metal piece 21 and the lead frame island region 22 are connected through a drain frame bonding layer 34; and the periphery of all the structures is filled and wrapped by plastic packaging material.
In the structure, a five-layer structure is formed by sequentially arranging a drain metal sheet 21, a first chip 41, a source metal sheet 23, a gate metal sheet 24, a second chip 42 and a lead frame from top to bottom, wherein the first chip 41 is connected with the second chip 42 in parallel, specifically, a source electrode of the first chip is connected with the source metal sheet 23 through a first source bonding layer 33, a gate electrode of the first chip is connected with the gate metal sheet 24 through a first gate bonding layer 32, a drain electrode of the first chip is connected with the drain metal sheet 21 through a first drain bonding layer 31, a source electrode 421 of the second chip is connected with the source metal sheet 23 through a second source bonding layer 35, a gate electrode 422 of the second chip is connected with the gate metal sheet 24 through a second gate bonding layer 36, a drain electrode of the second chip is connected with a lead frame base region 22 through a second drain bonding layer 37, and the first chip 41 and the second chip 42 are in an up-down stacked structure, so that the total volume of the power device can be effectively reduced.
Based on the double-core parallel power device packaging structure, the preparation method specifically comprises the following steps:
the drain electrode of the second chip 42 is combined with the lead frame base island region 22, the source electrode 421 of the second chip is combined with the source metal sheet 23, the gate electrode 422 of the second chip is combined with the gate metal sheet 24, the source metal sheet 23 is combined with the lead frame foot frame welding region 25, the gate metal sheet 24 is combined with the lead frame foot frame welding region 25, the source electrode of the first chip 41 is combined with the source metal sheet 23, the gate electrode of the first chip 41 is combined with the gate metal sheet 24, the drain electrode of the first chip 41 is combined with the drain metal sheet 21, the drain metal sheet 21 is combined with the lead frame base island region 22 by welding, sintering or bonding, and finally, the bonding layer structure is used for filling and wrapping the components by using plastic packaging materials, and the drain metal sheet 21, the lead frame base island region 22 and the lead frame foot frame welding region 25 are exposed on the surface of the power device, so that a heat dissipation channel is increased for heat dissipation of the device.
The invention is not limited to the examples, and any equivalent changes to the technical solution of the invention by a person skilled in the art after reading the description of the invention are covered by the claims of the invention.
Claims (3)
1. The utility model provides a two parallelly connected power device packaging structure of core which characterized in that:
the lead frame comprises a first chip (41), a second chip (42), a lead frame, a source metal sheet (23), a gate metal sheet (24) and a drain metal sheet (21), wherein the lead frame comprises a lead frame base island region (22) and a lead frame foot rest welding region (25), one end of the source metal sheet (23) is connected with the lead frame foot rest welding region (25) through a source frame bonding layer (39), two side faces of the other end of the source metal sheet are respectively connected with the source of the first chip (41) and the source of the second chip (42) through bonding layers, one end of the gate metal sheet (24) is connected with the lead frame foot rest welding region (25) through a gate frame bonding layer (38), two side faces of the other end of the gate metal sheet are respectively connected with the gates of the first chip (41) and the second chip (42) through bonding layers, the drain of the first chip (41) is connected with the drain metal sheet (21) through a first drain bonding layer (31), the drain of the second chip (42) is connected with the lead frame base island region (22) through a second drain bonding layer (37), and the drain metal sheet (21) is connected with the lead frame base region (22) through a drain frame bonding layer (34); and the periphery of all the structures is filled and wrapped by plastic packaging material.
2. The package structure of claim 1, wherein:
the first chip (41) comprises a first chip source electrode, a first chip grid electrode and a first chip drain electrode, wherein the first chip source electrode is connected with the source metal sheet (23) through a first source electrode bonding layer (33), the first chip grid electrode is connected with the grid metal sheet (24) through a first grid electrode bonding layer (32), and the first chip drain electrode is connected with the drain metal sheet (21) through a first drain electrode bonding layer (31);
the second chip (42) comprises a second chip source electrode (421), a second chip grid electrode (422) and a second chip drain electrode, wherein the second chip source electrode (421) is connected with the source metal sheet (23) through a second source bonding layer (35), the second chip grid electrode (422) is connected with the grid metal sheet (24) through a second grid bonding layer (36), and the second chip drain electrode is connected with the lead frame base island region (22) through a second drain bonding layer (37).
3. A preparation method of a double-core parallel power device packaging structure is characterized by comprising the following steps:
the drain electrode of the second chip (42) is bonded to the lead frame base island region (22), the source electrode (421) of the second chip is bonded to the source metal piece (23), the gate electrode (422) of the second chip is bonded to the gate metal piece (24), the source metal piece (23) is bonded to the lead frame leg land region (25), the gate metal piece (24) is bonded to the lead frame leg land region (25), the source electrode of the first chip (41) is bonded to the source metal piece (23), the gate electrode of the first chip (41) is bonded to the gate metal piece (24), the drain electrode of the first chip (41) is bonded to the drain metal piece (21), and the drain metal piece (21) is bonded to the lead frame base island region (22) by means of soldering, sintering or bonding, and the above bonding processes are all carried out by filling and wrapping the above components with a molding compound, and exposing the drain metal piece (21), the bonding layer base island region (22), and the lead frame leg land region (25) on the surface.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211135091.0A CN115440683A (en) | 2022-09-19 | 2022-09-19 | Double-core parallel high-power device packaging structure and preparation method thereof |
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| CN202211135091.0A CN115440683A (en) | 2022-09-19 | 2022-09-19 | Double-core parallel high-power device packaging structure and preparation method thereof |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050224945A1 (en) * | 2004-04-09 | 2005-10-13 | Kabushiki Kaisha Toshiba | Power semiconductor device package |
| US20080150105A1 (en) * | 2005-06-13 | 2008-06-26 | Infineon Technologies Ag | Power Semiconductor Component Stack Using Lead Technology with Surface-Mountable External Contacts and a Method for Producing the Same |
| US20140063744A1 (en) * | 2012-09-05 | 2014-03-06 | Texas Instruments Incorporated | Vertically Stacked Power FETS and Synchronous Buck Converter Having Low On-Resistance |
| US20170092596A1 (en) * | 2014-06-13 | 2017-03-30 | Rohm Co., Ltd. | Power module and fabrication method for the same |
| KR20210041197A (en) * | 2019-10-07 | 2021-04-15 | 제엠제코(주) | Semiconductor package for multi chip and method of fabricating the same |
| US20220122906A1 (en) * | 2020-10-16 | 2022-04-21 | Infineon Technologies Ag | Stacked transistor chip package with source coupling |
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2022
- 2022-09-19 CN CN202211135091.0A patent/CN115440683A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050224945A1 (en) * | 2004-04-09 | 2005-10-13 | Kabushiki Kaisha Toshiba | Power semiconductor device package |
| US20080150105A1 (en) * | 2005-06-13 | 2008-06-26 | Infineon Technologies Ag | Power Semiconductor Component Stack Using Lead Technology with Surface-Mountable External Contacts and a Method for Producing the Same |
| US20140063744A1 (en) * | 2012-09-05 | 2014-03-06 | Texas Instruments Incorporated | Vertically Stacked Power FETS and Synchronous Buck Converter Having Low On-Resistance |
| US20170092596A1 (en) * | 2014-06-13 | 2017-03-30 | Rohm Co., Ltd. | Power module and fabrication method for the same |
| KR20210041197A (en) * | 2019-10-07 | 2021-04-15 | 제엠제코(주) | Semiconductor package for multi chip and method of fabricating the same |
| US20220122906A1 (en) * | 2020-10-16 | 2022-04-21 | Infineon Technologies Ag | Stacked transistor chip package with source coupling |
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