CN203521394U - Chip packaging structure - Google Patents
Chip packaging structure Download PDFInfo
- Publication number
- CN203521394U CN203521394U CN201320581410.0U CN201320581410U CN203521394U CN 203521394 U CN203521394 U CN 203521394U CN 201320581410 U CN201320581410 U CN 201320581410U CN 203521394 U CN203521394 U CN 203521394U
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- Prior art keywords
- chip
- pad
- groove
- circuit board
- packaging structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A chip packaging structure comprises a chip and a packaging circuit board, wherein the chip comprises a chip functional zone, a plurality of first pads outside the chip functional zone and a groove on the edge of the chip, a second pad which is positioned on the bottom surface of the groove and electrically connected with the first pad through a metallic interconnection layer, a passivation layer covering the metallic interconnection layer and first pad and exposing the second pad, and a connecting structure positioned on the surface of the second pad. The chip and the packaging circuit board are fixedly connected through a connection structure. Since the connecting structure for fixed connection is positioned in the groove, the total thickness of the chip packaging structure is smaller than the sum of the thickness of the chip, the height of the connecting structure and the thickness of the packaging circuit board. The chip packaging structure makes the product smaller.
Description
Technical field
The utility model relates to semiconductor packaging, particularly a kind of chip-packaging structure.
Background technology
Development along with scientific and technological level, increasing consumption electronic product is more and more tending towards miniaturization to the requirement of size, the for example day by day frivolous miniaturization of current smart mobile phone, to meet that consumers in general are easy to carry to smart mobile phone and powerful, the expectation of high intelligence.Because consumption electronic product is more and more tending towards miniaturization, at present the encapsulation technology of the electronic chip in consumption electronic product has been proposed to more and more higher requirement.
Publication number is that the Chinese patent literature of CN102844769A discloses a kind of sensor-packaging structure, please refer to Fig. 1, cross-sectional view for described sensor-packaging structure, comprise: substrate 10, the induction chip 12 that is positioned at substrate 10 surfaces is connected pad 11 with first, be positioned at second of described induction chip 12 surfaces and connect pad 14, described the first connection pad 11 and second connects between pad 14 and is connected by wire 15; Be positioned at described induction chip 12 and cover the encapsulated layer 16 of described wire 15 around, described encapsulated layer 16 covers wire 15 completely, the second connection pad 14 surfaces are connected pad 11 surfaces, and utilize described encapsulated layer 16 that induction chip 12 is fixing with substrate 10 with first.
Because part encapsulated layer 16 is positioned at induction chip 12 surfaces, the gross thickness that makes described sensor-packaging structure is the thickness of substrate 10, the thickness of induction chip 12 and the thickness sum that is positioned at the encapsulated layer 16 on induction chip 12 surfaces, the thickness of described sensor-packaging structure is larger, is unfavorable for product miniaturization.
Utility model content
The problem that the utility model solves is to provide a kind of chip-packaging structure, can effectively reduce the gross thickness of chip-packaging structure.
For addressing the above problem, the utility model provides a kind of chip-packaging structure, comprising: chip and dimensional packaged circuit board; Described chip comprises chip functions district, be positioned at some first pads in outside, described chip functions district and be positioned at the groove of chip edge, be positioned at the second pad of described trench bottom surfaces, between described the second pad and the first pad, by metal interconnecting layer, be electrically connected to; Cover described metal interconnecting layer, the first pad and expose the passivation layer of the second pad; Be positioned at the syndeton of described the second bond pad surface, by described syndeton, chip be fixedly connected with dimensional packaged circuit board.
Optionally, described syndeton is the copper post that tin ball, copper post or top surface have gold layer.
Optionally, when described the first pad is positioned at the both sides in chip functions district, described groove is positioned at the both sides of the edge with the first pad of each chip; When described the first pad is positioned at the surrounding in chip functions district, described groove is positioned at the edge with the first pad of each chip.
Optionally, described dimensional packaged circuit board is printed circuit board (PCB) or flexible PCB.
Optionally, the height of described syndeton is less than the degree of depth of described groove.
Optionally, the degree of depth of described groove equals the thickness sum of height and the dimensional packaged circuit board of described syndeton.
Optionally, the depth bounds of described groove is 50 microns～200 microns.
Compared with prior art, the technical solution of the utility model has the following advantages:
The utility model utilizes the syndeton in the groove of chip edge that chip is fixedly connected with dimensional packaged circuit board, because described syndeton is positioned at the groove of chip edge, therefore the gross thickness of the chip-packaging structure of the utility model embodiment is less than the thickness sum of the thickness of chip, the height of syndeton and dimensional packaged circuit board, thereby is conducive to product miniaturization.
Further, when the degree of depth of described groove equals the thickness sum of height and the dimensional packaged circuit board of described syndeton, make the gross thickness of described chip-packaging structure only equal the thickness of chip, thereby can significantly reduce the package dimension of chip, be more conducive to the miniaturization of electronic product.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of a kind of sensor-packaging structure of prior art;
Fig. 2 to Figure 13 is the structural representation of forming process of the chip-packaging structure of the utility model embodiment.
Embodiment
Due to the gross thickness of the sensor-packaging structure of the prior art thickness that is substrate, the thickness of induction chip and the thickness sum that is positioned at the encapsulated layer on induction chip surface, the gross thickness of described sensor-packaging structure is larger, be unfavorable for product miniaturization, therefore, the utility model provides a kind of chip-packaging structure, utilize the syndeton in the groove of chip edge that chip is fixedly connected with dimensional packaged circuit board, because the syndeton for being fixedly connected with is positioned at described groove, therefore the gross thickness of the chip-packaging structure of the utility model embodiment is less than the thickness of chip, the thickness sum of the height of syndeton and dimensional packaged circuit board, thereby be conducive to product miniaturization.
For above-mentioned purpose of the present utility model, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiment of the utility model is described in detail.
The utility model embodiment provides a kind of formation method of chip-packaging structure, please refer to Fig. 2～Figure 13, is the structural representation of the formation method of described chip-packaging structure.
Please also refer to Fig. 2, Fig. 3 and Fig. 4, Fig. 2 is the plan structure schematic diagram of whole wafer to be wrapped, Fig. 3 is the plan structure schematic diagram of part wafer to be wrapped, Fig. 4 is the cross-sectional view along the part wafer to be wrapped of the AA ' line direction of Fig. 3, wafer to be wrapped 100 is provided, described wafer to be wrapped 100 comprises several chips 110 and the Cutting Road between chip 110 120, and each chip 110 comprises chip functions district 111 and is positioned at some first pads 112 in 111 outsides, described chip functions district.
Described wafer to be wrapped 100 comprises some chip 110 and Cutting Roads between chip 110 120 that matrix is arranged that are, and follow-uply along described Cutting Road 120, wafer to be wrapped 100 is cut into several discrete chips when wafer to be wrapped 100 is cut into slices.
Each chip 110 of described wafer to be wrapped 100 comprises chip functions district 111 and is positioned at some first pads 112 in 111 outsides, described chip functions district.Core circuit or sensor unit that described chip functions district 111 is chip, such as the photosensitive unit of imageing sensor, fingerprint sensing unit etc.Described the first pad 112Yu chip functions district 111 is electrically connected to, for chip functions district 111 is electrically connected to the dimensional packaged circuit board of follow-up encapsulation.In the present embodiment, described chip 110 is fingerprint sensor chip, in described chip functions district 111, has fingerprint sensing unit.
In the present embodiment, described the first pad 112 is positioned at the both sides in chip functions district 111, and follow-up Cutting Road 120 correspondence positions at each chip 110 with the both sides of the first pad 112 form groove.In other embodiments, when described the first pad is positioned at the surrounding in chip functions district, the follow-up Cutting Road correspondence position at each chip with the surrounding of the first pad forms groove.
Please refer to Fig. 5 and Fig. 6, Fig. 5 is the plan structure schematic diagram of described part wafer to be wrapped, Fig. 6 is the cross-sectional view along the part wafer to be wrapped of the AA ' line direction of Fig. 5, Cutting Road 120 directions along wafer to be wrapped 100 are carried out etching to wafer to be wrapped 110, form groove 130, the width of described groove 130 is greater than the width of Cutting Road 120.
In the present embodiment, the technique that forms described groove 130 comprises: on described wafer to be wrapped 100 surfaces, form the first photoresist layer (not shown), described the first photoresist layer is carried out to exposure imaging, form patterned the first photoresist layer, described patterned the first photoresist layer is corresponding to the position of the groove of follow-up formation; Described patterned the first photoresist layer of take is mask, and etching is carried out in described wafer to be wrapped 100 surfaces, forms groove 130.
The position of described groove 130 is corresponding to the position of Cutting Road 120, and the length direction of described groove 130 is parallel with corresponding Cutting Road 120 directions, and the Width of described groove 130 is parallel with corresponding Cutting Road 120 directions.In the present embodiment, described the first pad 112 is positioned at the both sides in chip functions district 111, therefore at each chip 110, has the Cutting Road 120 correspondence positions formation grooves 130 of the both sides of the first pad 112.In other embodiments, when described the first pad is positioned at the surrounding in chip functions district, the Cutting Road correspondence position at each chip with the surrounding of the first pad forms groove.
In the present embodiment, the length of the groove 130 of each chip 110 correspondence equals the length of side of chip 110, while etching being carried out in described wafer to be wrapped 100 surfaces, the position of all horizontal or all 120 correspondences of Cutting Road longitudinally is all cut the groove 130 forming.In other embodiments, please refer to Fig. 7, the length of the groove 130 of each chip 110 correspondence also can be less than the length of side of chip 110.
In the present embodiment, the position of center line of described groove 130 and Cutting Road 120 position of center line overlaids, and because the width of described groove 130 is greater than the width of Cutting Road 120, be positioned at follow-up the second pad and the syndeton of being used to form in groove 130 bottoms of Cutting Road 120 both sides.In other embodiments, the position of center line of described groove and Cutting Road position of center line have a little bias, but described Cutting Road is positioned at the region of groove completely, and are positioned at follow-up the second pad and the syndeton of being used to form of channel bottom of Cutting Road both sides.
In the present embodiment, the depth bounds of described groove 130 is 50 microns～200 microns.In other embodiments, the degree of depth of described groove and width can be also other suitable values.
Please refer to Fig. 8 and Fig. 9, Fig. 8 is the plan structure schematic diagram of described part wafer to be wrapped, Fig. 9 is the cross-sectional view along the part wafer to be wrapped of the AA ' line direction of Fig. 8, groove 130 lower surface in described Cutting Road 120 both sides form the second pad 113, at the sidewall of described wafer to be wrapped 100 surfaces, groove 130, form with lower surface the metal interconnecting layer 114 that is connected the first pad 112 and the second pad 113.
In the present embodiment, the concrete technology that forms described the second pad 113 and metal interconnecting layer 114 comprises: utilize physical gas-phase deposition to form metal interconnected film (not shown) in sidewall and the lower surface of described wafer to be wrapped 100 surfaces, groove 130, described metal interconnected film is carried out to etching, form second pad 113 and the metal interconnecting layer 114 that is connected described the first pad 112 and the second pad 113 of groove 130 lower surface that are positioned at Cutting Road 120 both sides.Described the second pad 113 is corresponding one by one with the first pad 112.The material of described the second pad 113 and metal interconnecting layer 114 is aluminium, aluminium copper etc.
In other embodiments, also can adopt electroplating technology to form described the second pad and metal interconnecting layer.In other embodiments, described the second pad and metal interconnecting layer also can adopt different process separately to form.
Please refer to Figure 10, at described the first pad 112 and metal interconnecting layer 114 surfaces, form passivation layer 115, and described passivation layer 115 exposes the second pad 113 surfaces.
Described passivation layer 115, for the first pad 112 and metal interconnecting layer 114 are isolated from the outside, avoids extraneous steam, foreign material can affect the electric property of the first pad 112 and metal interconnecting layer 114.The material of described passivation layer 115 is silica, silicon nitride, silicon oxynitride, fire sand, resin etc.In the present embodiment, the material of described passivation layer 115 is silica, the concrete technology that forms described passivation layer 115 is: on described wafer to be wrapped 100 surfaces, the first pad 112, the second pad 113 and metal interconnecting layer 114 surfaces form passivation films, passivation film to described the second pad 113He chip functions district 111 correspondence positions carries out etching, until expose described the second pad 113He chip functions district 111, form the passivation layer 115 that covers described the first pad 112 and metal interconnecting layer 114 surfaces and expose described the second pad 113 surfaces.Described the second pad 113 follow-up syndetons that are used to form in surface that expose.
In the present embodiment, because described chip 110 is fingerprint sensor chip, so etching has been removed the passivation film on 111 surfaces, described chip functions district.In other embodiments, also can not remove the passivation film on surface, described chip functions district, only remove the passivation layer of the second bond pad surface.
Please refer to Figure 11, on described the second pad 113 surfaces, form syndeton 135.
Described syndeton 135 is fixedly connected with chip for follow-up with dimensional packaged circuit board.The copper post that described syndeton 135 is golden layer for tin ball, copper post or top surface have.
In the present embodiment, described syndeton 135 is copper post, and the technique that forms described copper post comprises: on described wafer to be wrapped 100 surfaces, form the mask layer (not shown) with through hole, described via bottoms exposes described the second pad 113 surfaces; Utilize electroplating technology in described through hole, to form copper post, the height of described copper post is less than the height of described through hole and is less than the degree of depth of described groove; Remove described mask layer.In the present embodiment, described mask layer is photoresist layer, and in other embodiments, described mask layer can also be other hard mask layers, such as silicon oxide layer, silicon nitride layer, resin bed etc.Because the syndeton 135 for being fixedly connected with is positioned at described groove 130, therefore the gross thickness of the chip-packaging structure of the utility model embodiment is less than the thickness sum of the thickness of chip, the height of syndeton and dimensional packaged circuit board, thereby is conducive to product miniaturization.And because the height of described copper post is less than the degree of depth of described groove, while therefore utilizing described syndeton 135 that chip is fixedly connected with dimensional packaged circuit board, the gross thickness of the final chip-packaging structure forming is less than the thickness sum of thickness and the dimensional packaged circuit board of chip, is further conducive to the final electronics miniaturization forming.
In other embodiments, described syndeton can also have the copper post of gold layer for top surface, form technique and comprise: on described wafer to be wrapped surface, form the mask layer with through hole, described via bottoms exposes described the second bond pad surface; Utilize electroplating technology in described through hole, to form copper post, the height of described copper post is less than the height of described through hole and is less than the degree of depth of described groove; Utilize electroplating technology or chemical vapor deposition method to form gold layer at the top surface of copper post; Remove described mask layer.Because the conducting resistance of gold layer is less, be conducive to improve On current, and ductility is better, thereby more easily utilizes the mode pad phase bonding corresponding with dimensional packaged circuit board of metal bonding to be fixedly connected with.
When described syndeton 135 has the copper post of gold layer for copper post or top surface, first form the copper post that described copper post or top surface have gold layer, more described wafer to be wrapped cut to the discrete chip of formation.
In other embodiments, when described syndeton is tin ball, first described wafer to be wrapped is cut and forms discrete chip, then form tin ball in the second bond pad surface exposing, utilize described tin ball that described discrete chip is fixedly connected with dimensional packaged circuit board.
Please refer to Figure 12, along Cutting Road, 120(please refer to Figure 11) wafer to be wrapped 100 is cut and forms discrete chip 110.
The technique that wafer to be wrapped 100 is cut into slices is slicer cutting or laser cutting, and wherein because laser cutting has less kerf width, so the present embodiment adopts laser to cut wafer to be wrapped 100.Described cutting technique cuts along 120 pairs of wafers to be wrapped 100 of Cutting Road, and because the position that Cutting Road is corresponding at least partly forms groove, the position attenuation of the wafer to be wrapped 100 of correspondence position, utilize successfully wafer to be wrapped 100 to be cut less clipping time, and be not easy wafer to be wrapped 100 to cause damage.
Please refer to Figure 13, utilize described syndeton 135 that described discrete chip 110 is fixedly connected with dimensional packaged circuit board 140.
Described dimensional packaged circuit board 140 is printed circuit board (PCB) (PCB) or flexible PCB (FPC), described dimensional packaged circuit board 140 has pad (not shown) and metal wire (not shown), described syndeton 135 is connected with the pad of dimensional packaged circuit board 140, and discrete chip 110 is fixedly connected with dimensional packaged circuit board 140.The thickness of described dimensional packaged circuit board 140 can be less than, be equal to or greater than the degree of depth of described groove.In the present embodiment, the height sum of the thickness of described dimensional packaged circuit board 140 and syndeton 135 equals the degree of depth of groove, make the gross thickness of described chip-packaging structure only equal the thickness of chip, thereby can significantly reduce the package dimension of chip, be conducive to the miniaturization of electronic product.
In the present embodiment, described syndeton 135 is copper post, and the described copper post bonding that is connected with the pad of dimensional packaged circuit board 140 by metal bonding technique, makes described discrete chip 110 be fixedly connected with dimensional packaged circuit board 140.Described metal bonding technique is that eutectic bonding, metal are diffusion interlinked, wherein a kind of such as anode linkage, adhesive bond.
In other embodiments, described syndeton is the copper post that top surface has gold layer, the copper post that described top surface has the gold layer bonding that is connected with the pad of dimensional packaged circuit board by metal bonding technique, makes described discrete chip be fixedly connected with dimensional packaged circuit board.Described metal bonding technique is that eutectic bonding, metal are diffusion interlinked, wherein a kind of such as anode linkage, adhesive bond.
In other embodiments, when described syndeton is tin ball, wafer to be wrapped is cut and formed after discrete chip, the second bond pad surface exposing at chip is formed for welding tin ball, and by welding procedure, described tin ball and the pad of dimensional packaged circuit board are welded mutually, thereby described discrete chip is fixedly connected with dimensional packaged circuit board.
Utilize above-mentioned formation method, the utility model embodiment also provides a kind of chip-packaging structure, please refer to Figure 13, and the cross-sectional view for described chip-packaging structure, comprising: chip 110 and dimensional packaged circuit board 140; Described chip 110 comprises chip functions district 111, be positioned at some first pads 112 in 111 outsides, described chip functions district and be positioned at the groove at chip 110 edges, be positioned at the second pad 113 of described trench bottom surfaces, between described the second pad 113 and the first pad 112, by metal interconnecting layer 114, be electrically connected to, cover described metal interconnecting layer 114, the first pad 112 and expose the passivation layer 115 of the second pad 113, be positioned at the syndeton 135 on described the second pad 114 surfaces; By described syndeton 135, chip 110 is fixedly connected with dimensional packaged circuit board 140.
The copper post that described syndeton 135 is golden layer for tin ball, copper post or top surface have.The height of described syndeton 135 is greater than, is less than or equal to the degree of depth of described groove.In the present embodiment, described syndeton 135 is less than the degree of depth of described groove, and the degree of depth of described groove equals the thickness sum of height and the dimensional packaged circuit board of described syndeton, thereby can effectively reduce the thickness of chip-packaging structure, be conducive to the miniaturization of electronic product.
In the present embodiment, when described the first pad 112 is positioned at the both sides in chip functions district 111, described groove is positioned at the both sides of the edge with the first pad 112 of each chip 110.In other embodiments, when described the first pad is positioned at the surrounding in chip functions district, described groove is positioned at the edge with the first pad of each chip.
In the present embodiment, the depth bounds of described groove is 50 microns～200 microns.In other embodiments, the degree of depth of described groove can be also other suitable values.
Although the utility model discloses as above, the utility model is not defined in this.Any those skilled in the art, within not departing from spirit and scope of the present utility model, all can make various changes or modifications, and therefore protection range of the present utility model should be as the criterion with claim limited range.
Claims (7)
1. a chip-packaging structure, is characterized in that, comprising:
Chip and dimensional packaged circuit board;
Described chip comprises chip functions district, be positioned at some first pads in outside, described chip functions district and be positioned at the groove of chip edge, be positioned at the second pad of described trench bottom surfaces, between described the second pad and the first pad, by metal interconnecting layer, be electrically connected to;
Cover described metal interconnecting layer, the first pad and expose the passivation layer of the second pad;
Be positioned at the syndeton of described the second bond pad surface, by described syndeton, chip be fixedly connected with dimensional packaged circuit board.
2. chip-packaging structure as claimed in claim 1, is characterized in that, described syndeton is the copper post that tin ball, copper post or top surface have gold layer.
3. chip-packaging structure as claimed in claim 1, is characterized in that, when described the first pad is positioned at the both sides in chip functions district, described groove is positioned at the both sides of the edge with the first pad of each chip; When described the first pad is positioned at the surrounding in chip functions district, described groove is positioned at the edge with the first pad of each chip.
4. chip-packaging structure as claimed in claim 1, is characterized in that, described dimensional packaged circuit board is printed circuit board (PCB) or flexible PCB.
5. chip-packaging structure as claimed in claim 1, is characterized in that, the height of described syndeton is less than the degree of depth of described groove.
6. chip-packaging structure as claimed in claim 1, is characterized in that, the degree of depth of described groove equals the thickness sum of height and the dimensional packaged circuit board of described syndeton.
7. chip-packaging structure as claimed in claim 1, is characterized in that, the depth bounds of described groove is 50 microns～200 microns.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320581410.0U CN203521394U (en) | 2013-09-18 | 2013-09-18 | Chip packaging structure |
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| CN201320581410.0U CN203521394U (en) | 2013-09-18 | 2013-09-18 | Chip packaging structure |
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| CN203521394U true CN203521394U (en) | 2014-04-02 |
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| CN201320581410.0U Expired - Lifetime CN203521394U (en) | 2013-09-18 | 2013-09-18 | Chip packaging structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016037574A1 (en) * | 2014-09-12 | 2016-03-17 | 苏州晶方半导体科技股份有限公司 | Chip packaging method and package structure |
| CN105810645A (en) * | 2015-07-15 | 2016-07-27 | 维沃移动通信有限公司 | Biological identification chip packaging structure and mobile terminal |
-
2013
- 2013-09-18 CN CN201320581410.0U patent/CN203521394U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016037574A1 (en) * | 2014-09-12 | 2016-03-17 | 苏州晶方半导体科技股份有限公司 | Chip packaging method and package structure |
| US10090217B2 (en) | 2014-09-12 | 2018-10-02 | China Wafer Level Csp Co., Ltd. | Chip packaging method and package structure |
| CN105810645A (en) * | 2015-07-15 | 2016-07-27 | 维沃移动通信有限公司 | Biological identification chip packaging structure and mobile terminal |
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