CN115440658A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method of forming the same, the semiconductor structure comprising: the bulge part is separated from the substrate of the device region; a channel structure on the protrusion; the isolation layer is positioned on the substrate, surrounds the convex part and exposes the channel structure; the buried power rail penetrates through the isolation layer and the substrate with partial thickness in the power rail area, and the buried power rail and the protruding part are arranged in parallel at intervals; a gate structure located on the isolation layer and crossing the channel structure; the source-drain doped region is positioned in the channel structures at two sides of the grid structure; the interlayer dielectric layer is positioned on the isolation layer at the side part of the grid structure and covers the source drain doped region; and the source-drain interconnection layer penetrates through the source-drain doped region and the interlayer dielectric layer on the top of the buried power rail, is in contact with the source-drain doped region, and contacts the bottom of the source-drain interconnection layer with the top surface of the buried power rail, so that the source-drain interconnection layer and the buried power rail are electrically connected without a contact plug (Via), and the electrical connection performance between the source-drain interconnection layer and the buried power rail is optimized.

Description

Semiconductor structures and methods of forming them

technical field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

In order to meet the continuous shrinking needs of logic chips, in order to optimize the power supply capability when the metal pitch is very tight, a current method is to move the power rails down to the substrate to form buried power rails (Buried PowerRails, BPR).

In the buried power rail structure, the power rail is buried in the substrate and goes deep into the Shallow Trench Isolation (STI) module, which is conducive to the release of interconnect wiring resources; moreover, the buried power rail increases the BEOL resistance by using pitch scaling. technology provides lower resistive local current distribution; in addition, buried power rails are also beneficial to reduce the grid-like distribution of VDD, VSS, word lines and bit lines affected by routing congestion and resistance degradation, improving write margin and read speed. In addition, in transistors, the buried power rail is usually connected to the source-drain interconnection layer, thereby supplying power to the source-drain doped region through the source-drain interconnection layer.

However, current electrical connections between buried power rails and source-drain interconnect layers are poor.

Contents of the invention

The problem to be solved by the embodiments of the present invention is to provide a semiconductor structure and its forming method to optimize the electrical connection performance between the source-drain interconnection layer and the buried power rail.

In order to solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate including a plurality of discrete device regions and a power rail region located between the device regions; a raised portion separated from the device regions on the substrate; the channel structure is located on the raised portion; the isolation layer is located on the substrate and surrounds the raised portion and exposes the channel structure; the buried power rail runs through the power supply In the isolation layer of the track region and part of the thickness of the substrate, the buried power rail and the raised part are arranged in parallel and spaced apart; the gate structure is located on the isolation layer and crosses the channel structure; source and drain doping region, located in the channel structure on both sides of the gate structure; an interlayer dielectric layer, located on the isolation layer on the side of the gate structure and covering the source-drain doped region; a source-drain interconnection layer, penetrating through the source-drain doped region and the interlayer dielectric layer on top of the buried power rail, the source-drain interconnection layer is in contact with the source-drain doped region, and the bottom of the source-drain interconnection layer make contact with the top surface of the buried power rail.

Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, including a plurality of discrete device regions and power rail regions between the device regions, and the substrate of the device regions A discrete raised part is formed on the raised part, and a channel structure is formed on the raised part, and an isolation layer surrounding the raised part is formed on the substrate, and the isolation layer exposes the channel structure, Buried power rails are formed in the isolation layer of the power rail region and part of the thickness of the substrate, and the buried power rails are arranged in parallel with the raised portion at intervals. The gate structure of the channel structure, the source-drain doped region in the channel structure located on both sides of the gate structure, and the isolation layer located on the side of the gate structure and covering the source-drain doped region An interlayer dielectric layer; forming a source-drain interconnection layer penetrating through the source-drain doped region and the interlayer dielectric layer on the top of the buried power rail, the source-drain interconnection layer being identical to the source-drain doped region contact, and the bottom of the source-drain interconnect layer is in contact with the top surface of the buried power rail.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

In the semiconductor structure provided by the embodiment of the present invention, the source-drain interconnection layer is in contact with the source-drain doped region, and the bottom of the source-drain interconnection layer is also in contact with the top surface of the buried power rail, so that The source-drain interconnect layer and the buried power rail do not need to be electrically connected through a contact plug (Via), which not only shortens the current transmission path between the source-drain interconnect layer and the buried power rail, but also It also prevents the excessive resistance of the contact plug from adversely affecting the electrical connection performance between the source-drain interconnection layer and the buried power rail, thereby optimizing the electrical connection performance between the source-drain interconnection layer and the buried power rail, and improving power supply efficiency.

In the method for forming a semiconductor structure provided in an embodiment of the present invention, in the step of forming a source-drain interconnection layer, the source-drain interconnection layer is in contact with the source-drain doped region, and the source-drain interconnection layer The bottom of the bottom is also in contact with the top surface of the buried power rail, so that there is no need to realize an electrical connection through a contact plug (Via) between the source-drain interconnection layer and the buried power rail, which not only shortens the source-drain The current transmission path between the interconnection layer and the buried power rail, and also prevents the excessive resistance of the contact plug from adversely affecting the electrical connection performance between the source-drain interconnection layer and the buried power rail, thereby optimizing the source-drain The electrical connection performance between interconnect layers and buried power rails improves power supply efficiency.

Description of drawings

FIG. 1 is a schematic diagram of a partial cross-sectional structure of a semiconductor structure;

2 to 3 are structural schematic diagrams of an embodiment of the semiconductor structure of the present invention;

4 to 14 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

detailed description

It can be seen from the background art that the current electrical connection performance between the buried power rail and the source-drain interconnection layer is poor.

Specifically, referring to FIG. 1 , it is a schematic diagram of a partial cross-sectional structure of a semiconductor structure. The source-drain interconnection layer 1 penetrates the interlayer dielectric layer 3 on the top of the source-drain doped region 2, and is used to realize the connection between the source-drain doped region 2 and the The electrical connection between external circuits, while the buried power rail 4 is located in the substrate 5, the top surface of the buried power rail 4 is lower than the bottom surface of the source-drain interconnection layer 1, therefore, as shown in Figure 1, the source-drain interconnection layer 1 and the buried power rail 4 generally require a power rail contact plug (Via) 6 to realize electrical connection.

Wherein, the aspect ratio of the power rail contact plug 6 is usually relatively large, resulting in a high resistance of the power rail contact plug 6, which in turn leads to poor electrical connection performance between the source-drain interconnection layer and the buried power rail 4, It affects the power supply efficiency to the source-drain doped region 2 . In particular, with the continuous shrinking of the device size, the critical dimensions of the power rail contact plug 6 are also continuously reduced, and the aspect ratio of the power rail contact plug 6 is continuously increased. 1 to the performance of the electrical connection between the buried power rail 4 is increasingly not negligible.

In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, the source-drain interconnection layer is in contact with the source-drain doped region, and the bottom of the source-drain interconnection layer is also in contact with the top surface of the buried power rail, so that the source-drain interconnection layer There is no need for contact plugs (Via) to realize electrical connection between the interconnection layer and the buried power rail, which not only shortens the current transmission path between the source-drain interconnection layer and the buried power rail, but also prevents the resistance of the contact plug from being too high. Large adverse effects on the electrical connection performance between the source-drain interconnection layer and the buried power rail, thereby optimizing the electrical connection performance between the source-drain interconnection layer and the buried power rail, and improving power supply efficiency.

In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. Referring to FIG. 2 to FIG. 3 , which are respectively a top view and a cross-sectional view along the a-a1 direction of FIG. 2 , are schematic structural diagrams of an embodiment of the semiconductor structure of the present invention.

As shown in FIG. 2 and FIG. 3 , in this embodiment, the semiconductor structure includes: a substrate 100, including a plurality of discrete device regions 100a and a power rail region 100b between the device regions 100a; On the substrate 100 of the device region 100a; the channel structure 110 is located on the raised portion 105; the isolation layer 115 is located on the substrate 100 and surrounds the raised portion 105, and exposes the channel structure 110; the buried power rail 120 runs through In the isolation layer 115 of the power rail region 100b and the partial thickness substrate 100, the buried power rail 120 and the raised portion 105 are arranged in parallel and at intervals; the gate structure 130 is located on the isolation layer 115 and crosses the channel structure 110; The source-drain doped region 140 is located in the channel structure 110 on both sides of the gate structure 130; the interlayer dielectric layer 150 is located on the isolation layer 115 on the side of the gate structure 130 and covers the source-drain doped region 140; the source The drain interconnection layer 180 runs through the source-drain doped region 140 and the interlayer dielectric layer 150 on the top of the buried power supply rail 120, the source-drain interconnection layer 180 is in contact with the source-drain doped region 140, and the source-drain interconnection layer 180 The bottom is in contact with the top surface of the buried power rail 120 .

The substrate 100 is used to provide a process platform for the formation of semiconductor structures. The material of the substrate 100 includes: one or more of single crystal silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and gallium indium. In this embodiment, the substrate 100 is a silicon substrate.

The device region 100a is used to form field effect transistors, such as one or both of PMOS transistors and NMOS transistors. The power rail area 100b is used to place buried power rails 120 .

In this embodiment, the protruding portion 105 and the substrate 100 are integrated, and the material of the protruding portion 105 is the same as that of the substrate 100 , both being silicon. In other embodiments, the material of the raised part may be different from that of the substrate, and the material of the raised part may be other suitable materials, such as germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and One or more of indium gallium oxides.

The channel structure 110 is used to provide the conduction channel of the field effect transistor during device operation. In this embodiment, there are multiple channel structures 110 , and the multiple channel structures 110 are arranged in parallel and spaced apart.

As an example, the device region 100a is used to form a Fin Field Effect Transistor (FinFET). Correspondingly, the channel structure 110 is a fin. Specifically, the fin is connected to the raised portion 105 . In this embodiment, the fin portion and the protruding portion 105 are integrally formed.

In this embodiment, the material of the fin is the same as that of the substrate 100 , and the material of the fin is silicon. In other embodiments, the material of the fins may also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium, or other materials suitable for forming fins. The semiconductor material of the fin part can also be different from the material of the substrate.

In other embodiments, when the first device and the second device are Gate-All Around (GAA) transistors or fork gate transistors (Forksheet), the channel structure can also be a channel structure layer, and the channel The channel structure layer and the protruding part are arranged at intervals, and the channel structure layer includes one or more channel layers arranged at intervals in sequence.

In this embodiment, both the channel structure 110 and the protruding portion 105 extend laterally, and the plurality of protruding portions 105 or the plurality of channel structures 110 are arranged at intervals along the longitudinal direction. Wherein, the horizontal direction is perpendicular to the vertical direction.

The isolation layer 115 is used to isolate adjacent raised portions 105 , and the isolation layer 115 is also used to isolate the substrate 100 from subsequent gate structures. In this embodiment, the isolation layer 115 is a shallow trench isolation layer (STI), and the material of the isolation layer 115 is an insulating material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride.

In this embodiment, the top surface of the isolation layer 115 is flush with the top surface of the protruding portion 105 .

In this embodiment, the buried power rail 120 is used to provide power to the various components of the chip. In this embodiment, the buried power rail 120 is located in the substrate 100 of the power rail region 100b, and the buried power rail 120 is a buried power rail (Buried Power Rails, BPR), which is conducive to releasing the wiring resources of the back-end interconnection, and has It is beneficial to reduce the height of standard cells to meet the needs of continuous logic chip miniaturization. In addition, the technology of increasing the resistance of the back end (BackEnd of Line, BEOL) by using the embedded power rail is also conducive to providing lower The resistive local current distribution.

Both the buried power rail 120 and the channel structure 110 extend laterally, and there is an interval between the buried power rail 120 and the channel structure 110 . The direction perpendicular to the transverse direction is the longitudinal direction.

The material for burying the power rail 120 is a conductive material. In this embodiment, the material for burying the power rail 120 is a metal material, such as one or more of Co, W, Ni and Ru. By selecting these materials, the resistivity of the buried power supply rail 120 is low, which is beneficial to improve RC delay, improve chip processing speed and power supply efficiency.

In this embodiment, the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115 .

The top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115, so that the top surface of the buried power rail 120 exposes the top surface of the isolation layer 115, the height of the top surface of the buried power rail 120 is relatively high, and the source-drain interconnection layer The bottom of the 180 is more likely to be in contact with the top surface of the buried power rail 120, which is beneficial to reducing the process difficulty of forming the source-drain interconnection layer, and improving process compatibility and process stability.

In other embodiments, the top surface of the buried power rail is higher than the top surface of the substrate and lower than the top surface of the isolation layer; the semiconductor structure further includes: a capping dielectric layer located in the isolation layer and located on the top surface of the buried power rail.

The capping dielectric layer is used to isolate the buried power rail from the gate structure, or to isolate the buried power rail from other conductive structures on the isolation layer. The material covering the dielectric layer is a dielectric material, such as one or more of silicon oxide, silicon oxynitride and silicon nitride. As an example, the covering dielectric layer is made of the same material as the isolation layer, which is beneficial to improve process compatibility.

Specifically, the top surface of the covering dielectric layer is flush with the top surface of the isolation layer, so that the top surface of the isolation layer is a flat surface, thereby facilitating the formation of the gate structure.

The top surface of the buried power rail 120 is lower than or flush with the top surface of the isolation layer 115; along the direction perpendicular to the surface of the substrate 100, the distance between the top surface of the buried power rail 120 and the top surface of the isolation layer 115 should not be too large , otherwise the covering dielectric layer on the top surface of the buried power rail 120 is too thick, the source-drain interconnection layer needs to penetrate through the covering dielectric layer to be in contact with the top surface of the buried power rail 120, and the covering dielectric layer on the top surface of the buried power rail 120 is too thick Accordingly, the source-drain interconnection layer 180 is too deep, which easily increases the difficulty of forming the source-drain interconnection layer 180 , and also tends to reduce process compatibility and increase process risk. Therefore, in this embodiment, along the direction perpendicular to the surface of the substrate 100 , the distance between the top surface of the buried power rail 120 and the top surface of the isolation layer 115 is 0 nm to 15 nm.

Wherein, when the distance between the top surface of the buried power rail 120 and the top surface of the isolation layer 115 is 0 nm, the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115 .

In this embodiment, the semiconductor structure further includes: an insulating layer 125 located between the buried power rail 120 and the substrate 100 , and between the buried power rail 120 and the isolation layer 115 . The insulating layer 125 is used to achieve electrical isolation between the buried power rail 120 and the substrate 100 . The material of the insulating layer 125 is an insulating material, such as one or more of silicon oxide, silicon oxynitride and silicon nitride.

When the device is in operation, the gate structure 130 is used to control the conduction channel to be turned on or off.

Specifically, in this embodiment, the gate structure 130 spans the fin and covers part of the top and part of the sidewall of the fin. In other embodiments, when the channel structure is a channel structure layer suspended from the protrusion, the gate structure straddles the channel structure layer and surrounds the channel layer.

The extending direction of the gate structure 130 is perpendicular to the extending direction of the channel structure 110 , that is, the gate structure 130 extends longitudinally. In this embodiment, there are multiple gate structures 130 , and the multiple gate structures 130 are arranged at intervals along the lateral direction.

In this embodiment, the gate structure 130 is a metal gate (Metal Gate) structure. In other embodiments, the gate structure may also be other types of gate structures, such as polysilicon or amorphous silicon gate structures.

The material of the gate structure 130 is a conductive material. The material of the gate structure 130 includes any of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt and Ni one or more. Specifically, the gate structure 130 may include a work function layer (not shown) and a metal electrode layer on the work function layer, or the gate structure 130 is a work function layer, or the gate structure 130 is a metal electrode layer.

In this embodiment, the semiconductor structure further includes: a gate dielectric layer (not shown in the figure), located between the gate structure 130 and the channel structure 110 . In this embodiment, the gate dielectric layer is also located between the gate structure 130 and the top surface of the isolation layer 115 . The gate dielectric layer is used to realize the insulation between the gate structure 130 and the conductive channel.

Specifically, when the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115, the gate dielectric layer is also located between the gate structure 130 and the buried power rail 120, so as to realize the connection between the gate structure 130 and the buried power rail 120. insulation between. In other embodiments, when the top surface of the buried power rail is lower than the top surface of the isolation layer, and a covering dielectric layer is formed on the top surface of the buried power rail, the gate dielectric layer is also located between the gate structure and the covering dielectric layer. between.

The material of the gate dielectric layer includes one or more of HfO ₂ , ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La ₂ O ₃ , Al ₂ O ₃ , silicon oxide and silicon oxide doped with nitrogen. Specifically, the gate dielectric layer may include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer, or the gate dielectric layer is a gate oxide layer, or the gate dielectric layer is a high-k gate dielectric layer.

The semiconductor structure further includes: sidewalls (not shown in the figure) located on the sidewalls of the gate structure 130 . The sidewall is used to protect the sidewall of the gate structure 130 and also used to define the formation position of the source-drain doped region 140 .

The source-drain doped region 140 is used as the source or drain of the field effect transistor, and the source-drain doped region 140 is used to provide a carrier source when the field effect transistor is working. Specifically, the source-drain doped region 140 is located in the channel structure 110 on both sides of the gate structure 130 and the spacer. In this embodiment, the source-drain doped region 140 is located in the fins on both sides of the gate structure 130 and the sidewall.

In this embodiment, the source-drain doped region 140 includes a stress layer doped with ions, and the stress layer is used to provide stress for the channel region, thereby increasing the mobility of carriers. When forming a PMOS transistor, the source-drain doped region 140 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe; when forming an NMOS transistor, the source-drain doped region 140 includes a stress layer doped with N-type ions. A stress layer of ions, the material of the stress layer is Si or SiC.

The interlayer dielectric layer 150 is used to isolate adjacent devices, and is also used to electrically isolate adjacent conductive structures. In this embodiment, the interlayer dielectric layer 150 is located on the isolation layer 115 at the side of the gate structure 130 .

In this embodiment, the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115 , and the interlayer dielectric layer 150 also covers the top surface of the buried power rail 120 . In other embodiments, when the top surface of the buried power rail is lower than the top surface of the isolation layer, and the covering dielectric layer is formed on the top of the buried power rail, the interlayer dielectric layer also covers the covering dielectric layer.

The material of the interlayer dielectric layer 150 is insulating material. In this embodiment, the material of the interlayer dielectric layer 150 is silicon oxide. It should be noted that, for the convenience of illustration and description, only the isolation layer 115 and the interlayer dielectric layer 150 are illustrated in the cross-sectional view.

The source-drain interconnection layer 180 is in contact with the source-drain doped region 140 to realize electrical connection between the source-drain doped region 140 and external circuits or other interconnection structures. The bottom of the source-drain interconnection layer 180 is in contact with the top surface of the buried power supply rail 120, so that the source-drain interconnection layer 180 and the buried power supply rail 120 can be electrically connected, and then when the device is working, the buried power supply rail 120 can be connected to The source-drain doped region 140 supplies power.

Moreover, the bottom of the source-drain interconnection layer 180 is in contact with the top surface of the buried power supply rail 120, so that the electrical connection between the source-drain interconnection layer 180 and the buried power supply rail 120 does not need to be electrically connected through a contact plug (Via), which not only The current transmission path between the source-drain interconnection layer 180 and the buried power supply rail 120 is shortened, and it is also beneficial to prevent the resistance of the contact plug from adversely affecting the electrical connection performance between the source-drain interconnection layer and the buried power supply rail. , thereby optimizing the electrical connection performance between the source-drain interconnection layer 180 and the buried power rail 120 and improving power supply efficiency.

Specifically, in this embodiment, the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115, so that the source-drain interconnection layer 180 penetrates the source-drain doped region 140 and the interlayer dielectric on the top of the buried power rail 120 layer 150, the source-drain interconnection layer 180 can be in contact with the source-drain doped region 140, and the bottom surface of the source-drain interconnection layer 180 can be in contact with the buried power rail 120, which is beneficial to reduce the source-drain interconnection layer. Difficulty of direct contact between 180 and buried power rail 120.

In other embodiments, when the top surface of the buried power rail is lower than the top surface of the isolation layer, and a covering dielectric layer is formed on the top surface of the buried power rail, the source-drain interconnection layer correspondingly penetrates the top of the source-drain doped region The interlayer dielectric layer on the top, and the cover dielectric layer and interlayer dielectric layer on the top of the buried power rail can also realize the contact between the source and drain interconnection layer and the source and drain doped region, and the bottom of the source and drain interconnection layer and the buried purpose of touching the top surface of the power rail.

In this embodiment, the source-drain interconnection layer 180 extends longitudinally, and the extension direction of the source-drain interconnection layer 180 is perpendicular to the extension direction of the buried power rail 120 .

In this embodiment, the bottom of the source-drain interconnect layer 180 is flush with the top surface of the buried power rail 120, so that the bottom of the source-drain interconnect layer 180 is in contact with the top surface of the buried power rail 120, and the source and drain The bottom surface of the interconnection layer 180 is not too low, which is beneficial to improve process compatibility and process stability.

In other embodiments, the bottom of the source-drain interconnection layer can also be lower than the top surface of the buried power rail and higher than the top surface of the substrate, correspondingly, the bottom of the source-drain interconnection layer and the top surface of the buried power rail In addition, it is also beneficial to ensure that the bottom of each source-drain interconnection layer can be in contact with the top surface of the buried power rail, reducing the inconsistency of the bottom height of the source-drain interconnection layer, which causes some source-drain interconnection layers to be incompatible with The possibility of contacting the buried power supply rail correspondingly guarantees the electrical connection performance between the source-drain interconnection layer and the buried power supply. Specifically, the source-drain interconnection layer also penetrates part of the thickness of the isolation layer.

The material of the source-drain interconnection layer 180 is a conductive material, and the material of the source-drain interconnection layer 180 includes one or more of W, Co, Cu, Ru and Ni. The resistivity of the material is low, which is beneficial to reduce the resistance of the source-drain interconnection layer 180 , thereby reducing the RC delay and improving the performance of the semiconductor structure.

In this embodiment, the semiconductor structure further includes: a silicide layer 170 located between the source-drain interconnection layer 180 and the source-drain doped region 140 . The silicide layer 170 is used to reduce the contact resistance between the source-drain interconnection layer 180 and the source-drain doped region 140, and, when the device is in operation, current flows through the source-drain interconnection layer 180 and passes through the surface of the silicide layer 170 . In this embodiment, the material of the silicide layer 170 may be nickel silicon compound, cobalt silicon compound or titanium silicon compound.

In an optional solution, the semiconductor structure further includes: a separation layer 190 , which runs through a part of the source-drain interconnection layer 180 located in the power rail region 100b, and the division layer 190 longitudinally divides the source-drain interconnection layer 180 located in the adjacent device region 100a.

By setting the division layer 190, the source-drain interconnection layer 180 can be disconnected at the position that does not need to be connected based on design requirements, and the source-drain interconnection layer 180 that does not need to be electrically connected to the buried power rail 120 can be connected to the buried power supply rail 120. The isolation between the rails 120 improves the design freedom of the source-drain interconnection layer 180 .

In other embodiments, based on actual process requirements, no partition layer may be provided in the semiconductor structure, and the source-drain interconnection layers of adjacent device regions along the vertical direction are connected.

As an example, the step of forming the source-drain interconnection layer 180 includes: forming a source-drain interconnection groove penetrating through the source-drain doped region 140 and burying the interlayer dielectric layer 150 on the top of the power rail 120; A source-drain interconnection layer 180 is formed.

Wherein, in the step of forming the source-drain interconnection trench, a part of the width of the interlayer dielectric layer 150 located between the adjacent device regions 100 a in the longitudinal direction is reserved as the partition layer 190 . Correspondingly, the material of the partition layer 190 is the same as that of the interlayer dielectric layer 150 . In other embodiments, the material of the split layer may also be different from that of the interlayer dielectric layer, and the material of the split layer may also be other materials with electrical isolation.

As an example, the source-drain interconnection layer 180 located on any side of the partition layer 190 is in contact with the buried power rail 120 .

Correspondingly, the present invention also provides a method for forming a semiconductor structure. 4 to 14 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 4 to FIG. 8, a substrate 100 is provided, including a plurality of discrete device regions 100a and a power rail region 100b between the device regions 100a, and a discrete raised portion 105 is formed on the substrate 100 of the device region 100a, A channel structure 110 is formed on the raised portion 105, an isolation layer 115 surrounding the raised portion 105 is formed on the substrate 100, the isolation layer 115 exposes the channel structure 110, the isolation layer 115 of the power track region 100b and a part of the thickness liner A buried power rail 120 is formed in the bottom 100 , and the buried power rail 120 and the raised portion 105 are arranged in parallel and at intervals.

The substrate 100 is used to provide a process platform for subsequent processes. The material of the substrate 100 includes: one or more of single crystal silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and gallium indium. In this embodiment, the substrate 100 is a silicon substrate.

The device region 100a is used to form field effect transistors, such as one or both of PMOS transistors and NMOS transistors. The power rail area 100b is used to place buried power rails 120 .

In this embodiment, the protruding portion 105 and the substrate 100 are integrated, and the material of the protruding portion 105 is the same as that of the substrate 100 , both being silicon. For a detailed description of the material of the protruding portion 105 , please refer to the corresponding description in the foregoing embodiments, and details are not repeated here.

The channel structure 110 is used to provide the conduction channel of the field effect transistor during device operation. In this embodiment, there are multiple channel structures 110 , and the multiple channel structures 110 are arranged in parallel and spaced apart.

As an example, the device region 100a is used to form a Fin Field Effect Transistor (FinFET). Correspondingly, the channel structure 110 is a fin. Specifically, the fin is connected to the raised portion 105 . In this embodiment, the fin portion and the protruding portion 105 are integrally formed.

In this embodiment, the material of the fin is the same as that of the substrate 100 , and the material of the fin is silicon. For the detailed description of the material of the fin, please refer to the corresponding description in the foregoing embodiments, which will not be repeated here.

In other embodiments, when the first device and the second device are all-enclosed gate transistors or fork-shaped gate transistors, the channel structure may also be a channel structure layer, and the distance between the channel structure layer and the protrusion is It is provided that the channel structure layer includes one or more channel layers arranged at intervals in sequence. Specifically, in the step of providing the substrate, a sacrificial layer is also formed between the channel layer and the raised portion, or between adjacent channel layers, and the sacrificial layer is used to support the channel layer, so as to facilitate the subsequent implementation of the channel layer. The gap setting of the channel layer provides a process basis, and the sacrificial layer is also used to occupy a space for the subsequent formation of the gate structure.

In this embodiment, both the channel structure 110 and the protruding portion 105 extend laterally, and the plurality of protruding portions 105 or the plurality of channel structures 110 are arranged at intervals along the longitudinal direction. Wherein, the horizontal direction is perpendicular to the vertical direction.

The isolation layer 115 is used to isolate adjacent raised portions 105 , and the isolation layer 115 is also used to isolate the substrate 100 from subsequent gate structures. The isolation layer 115 includes one or more of silicon oxide, silicon oxynitride, and silicon nitride. In this embodiment, the top surface of the isolation layer 115 is flush with the top surface of the protruding portion 105 .

Buried power rails 120 are used to provide power to the various components of the chip. In this embodiment, the buried power rail 120 is located in the substrate 100 of the power rail region 100b, and the buried power rail 120 is a buried power rail (BPR), which is conducive to releasing the wiring resources of the back-end interconnection and lowering the standard The height of the unit is to meet the needs of continuous logic chip scaling. In addition, the technology of increasing the resistance of the back end (BEOL) by using the pitch reduction of the embedded power rail is also beneficial to provide lower resistance local current distribution.

The buried power rail 120 is an elongated structure, the buried power rail 120 and the channel structure 110 both extend laterally, and there is an interval between the buried power rail 120 and the channel structure 110 .

The material for burying the power rail 120 is a conductive material. In this embodiment, the material for burying the power rail 120 is a metal material, such as one or more of Co, W, Ni and Ru. By selecting these materials, the resistivity of the buried power rail 120 is low, which is beneficial to improving RC delay and increasing the processing speed of the chip.

In this embodiment, the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115 .

The top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115, so that the top surface of the buried power rail 120 exposes the top surface of the isolation layer 115, and the height of the top surface of the buried power rail 120 is relatively high. In the step of drain doping region and the source-drain interconnection layer in contact with the top surface of the buried power supply rail 120, the source-drain interconnection layer is more likely to be in contact with the top surface of the buried power supply rail 120, which is beneficial to reduce the formation of the source-drain interconnection layer. process difficulty, improve process compatibility and process stability.

In other embodiments, the top surface of the buried power rail is higher than the top surface of the substrate and lower than the top surface of the isolation layer, and a covering dielectric layer located on the top surface of the buried power rail is also formed in the isolation layer.

A covering dielectric layer in the isolation layer is also formed on the top surface of the buried power rail, so that the formation of the buried power rail and subsequent processes are compatible with existing processes.

The capping dielectric layer is used to isolate the buried power rail from the gate structure, or to isolate the buried power rail from other conductive structures on the isolation layer. The material covering the dielectric layer is a dielectric material, such as one or more of silicon oxide, silicon oxynitride and silicon nitride. As an example, the covering dielectric layer is made of the same material as the isolation layer, which is beneficial to improve process compatibility.

Specifically, the top surface of the covering dielectric layer is flush with the top surface of the isolation layer, so that the top surface of the isolation layer is a flat surface, thereby facilitating the formation of subsequent gate structures.

The top surface of the buried power rail 120 is lower than or flush with the top surface of the isolation layer 115; along the direction perpendicular to the surface of the substrate 100, the distance between the top surface of the buried power rail 120 and the top surface of the isolation layer 115 should not be too large , otherwise the covering dielectric layer on the top surface of the buried power supply rail 120 is too thick. In the subsequent step of forming the source-drain interconnection layer, the source-drain interconnection layer needs to penetrate through the covering dielectric layer to be in contact with the top surface of the buried power supply rail 120. The covering dielectric layer on the top surface of the power rail 120 is too thick, correspondingly causing the source-drain interconnection layer to be too deep, which easily increases the difficulty of forming the source-drain interconnection layer, and also tends to reduce process compatibility and increase process risk. Therefore, in this embodiment, along the direction perpendicular to the surface of the substrate 100 , the distance between the top surface of the buried power rail 120 and the top surface of the isolation layer 115 is 0 nm to 15 nm.

Wherein, when the distance between the top surface of the buried power rail 120 and the top surface of the isolation layer 115 is 0 nm, the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115 .

It should be noted that, in this embodiment, an insulating layer 125 is formed between the buried power rail 120 and the substrate 100 , and between the buried power rail 120 and the isolation layer 115 . The insulating layer 125 is used to achieve electrical isolation between the buried power rail 120 and the substrate 100 . The material of the insulating layer 125 is an insulating material, such as one or more of silicon oxide, silicon oxynitride and silicon nitride.

The steps of providing the substrate 100 in this embodiment will be described in detail below with reference to the accompanying drawings.

As shown in FIG. 4, a substrate 100, a raised portion 105 separated on the substrate 100 in the device region 100a, and a channel structure 110 located on the raised portion 105 are provided; And the isolation material layer 135 covering the channel structure 110 . The isolation material layer 135 is used for subsequent formation of an isolation layer, and also protects the channel structure 110 and the raised portion 105 during the process of forming the buried power rail.

As an example, using a flow chemical vapor deposition (FCVD) process to form an isolation film is conducive to improving the gap filling capability of the isolation film, thereby reducing the probability of defects such as voids in the isolation film; using a chemical mechanical planarization process. The film is planarized, which is beneficial to improve the flatness of the top surface of the isolation material layer 135 .

As shown in FIG. 5 , an isolation material layer 135 penetrating through the power rail region 100 b and a trench 145 with a partial thickness of the substrate 100 are formed. The trench 145 is used to define the formation position of the buried power rail and provide a space for the buried power rail. Specifically, using an anisotropic etching process, the isolation material layer 135 of the power rail region 100b and the substrate 100 with a partial thickness are sequentially etched to form the trench 145 . The anisotropic etching process has the characteristics of anisotropic etching, which is conducive to improving the control of the etching profile and the dimensional accuracy of the trench.

As shown in FIG. 6 , the buried power rail 120 is formed in the trench 145 , the top surface of the buried power rail 120 is higher than the top surface of the substrate 100 , and is lower or flush with the top surface of the raised portion 105 .

Specifically, the step of forming the buried power rail 120 in the trench 145 includes: forming a power rail material layer (not shown in the figure) in the trench 145, and the power rail material layer is also located on the top of the isolation material layer 135; removing part of the thickness layer of power rail material.

In this embodiment, the forming method further includes: before forming the power rail material layer in the trench 145 , forming the insulating film 101 on the bottom and sidewalls of the trench 145 and the top surface of the isolation material layer 135 . The insulating film 101 is used for subsequently forming an insulating layer to realize electrical isolation between the buried power rail and the substrate 100 .

As shown in FIG. 7 , a dielectric material layer 103 filling the trench 145 is formed on the buried power rail 120 .

The dielectric material layer 103 is used to protect the buried power rail 120 during subsequent etching of the isolation material layer 135 . In a specific implementation, when the top surface of the isolation layer formed by subsequent etching of the isolation material layer 135 is higher than the top surface of the buried power rail 120 , the dielectric material layer 103 is also used to form a covering dielectric layer.

As an example, the dielectric material layer 103 is formed by a flow chemical vapor deposition (FCVD) process.

As shown in FIG. 8, in this embodiment, the top surface of the buried power rail 120 is flush with the top surface of the raised portion 105, and the dielectric material layer 103 and the isolation material layer 135 higher than the top surface of the buried power rail 120 are removed, and the remaining The isolation material layer 135 is used as the isolation layer 115 . The top surface of the isolation layer 115 is flush with the top surfaces of the buried power rail 120 and the raised portion 105 .

In other embodiments, when the top surface of the buried power supply rail is lower than the top surface of the raised portion, part of the thickness of the dielectric material layer and the isolation material layer are removed, and the remaining isolation material layer is used as an isolation layer, and the rest is located on the buried power supply rail. The layer of dielectric material on the top surface of the rail serves as a covering dielectric layer. Accordingly, the top surface of the isolation layer is higher than the top surface of the buried power rail. Specifically, the top surface of the covering dielectric layer is flush with the top surface of the isolation layer.

Referring to FIGS. 9 and 10 , FIG. 9 is a top view, and FIG. 10 is a cross-sectional view along the a-a1 direction of FIG. The source-drain doped region 140 in the channel structure 110 on both sides, and the interlayer dielectric layer 150 located on the isolation layer 115 at the side of the gate structure 130 and covering the source-drain doped region 140 .

When the device is in operation, the gate structure 130 is used to control the conduction channel to be turned on or off.

Specifically, in this embodiment, the gate structure 130 spans the fin and covers part of the top and part of the sidewall of the fin. In other embodiments, when the channel structure is a channel structure layer suspended from the protrusion, the gate structure straddles the channel structure layer and surrounds the channel layer.

The extending direction of the gate structure 130 is perpendicular to the extending direction of the channel structure 110 , that is, the gate structure 130 extends longitudinally. In this embodiment, there are multiple gate structures 130 , and the multiple gate structures 130 are arranged at intervals along the lateral direction.

In this embodiment, the gate structure 130 is a metal gate (Metal Gate) structure. In other embodiments, the gate structure may also be other types of gate structures, such as polysilicon or amorphous silicon gate structures.

The material of the gate structure 130 is a conductive material. The material of the gate structure 130 includes any of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt and Ni one or more. Specifically, the gate structure 130 may include a work function layer (not shown) and a metal electrode layer on the work function layer, or the gate structure 130 is a work function layer, or the gate structure 130 is a metal electrode layer.

It should be noted that, in this embodiment, a gate dielectric layer (not shown) is further formed between the gate structure 130 and the channel structure 110 . In this embodiment, the gate dielectric layer is also located between the gate structure 130 and the top surface of the isolation layer 115 . The gate dielectric layer is used to realize the insulation between the gate structure 130 and the conductive channel.

Specifically, in this embodiment, when the top surface of the buried power supply rail 120 is flush with the top surface of the isolation layer 115, the gate dielectric layer is also located between the gate structure 130 and the buried power supply rail 120 to realize the gate structure 130. Insulation from buried power rail 120 . In other embodiments, when the top surface of the buried power rail is lower than the top surface of the isolation layer, and a covering dielectric layer is formed on the top surface of the buried power rail, the gate dielectric layer is also located between the gate structure and the covering dielectric layer .

The material of the gate dielectric layer includes: one or more of HfO ₂ , ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La ₂ O ₃ , Al ₂ O ₃ , silicon oxide and silicon oxide doped with nitrogen. Specifically, the gate dielectric layer may include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer, or the gate dielectric layer is a gate oxide layer, or the gate dielectric layer is a high-k gate dielectric layer.

It should be noted that sidewalls (not shown) may also be formed on the sidewalls of the gate structure 130 for protecting the sidewalls of the gate structure 130 and defining the formation positions of the source-drain doped regions 140 .

The source-drain doped region 140 is used as the source or drain of the field effect transistor, and the source-drain doped region 140 is used to provide a carrier source when the field effect transistor is working. In this embodiment, the source-drain doped regions 140 are located in the fins on both sides of the gate structure 130 . For a detailed description of the material of the source-drain doped region 140 , please refer to the corresponding description in the foregoing embodiments, and details are not repeated here.

The interlayer dielectric layer 150 is used to isolate adjacent devices, and is also used to electrically isolate adjacent conductive structures. In this embodiment, the interlayer dielectric layer 150 is located on the isolation layer 115 at the side of the gate structure 130 .

In this embodiment, the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115 , and the interlayer dielectric layer 150 also covers the top surface of the buried power rail 120 . In other embodiments, when the top surface of the buried power rail is lower than the top surface of the isolation layer, and the covering dielectric layer is formed on the top of the buried power rail, the interlayer dielectric layer also covers the covering dielectric layer.

The material of the interlayer dielectric layer 150 is insulating material. In this embodiment, the material of the interlayer dielectric layer 150 is silicon oxide. It should be noted that, for the convenience of illustration and description, only the isolation layer 115 and the interlayer dielectric layer 150 are illustrated in the cross-sectional view.

As an embodiment, the step of forming the gate structure 130, the source-drain doped region 140 and the interlayer dielectric layer 150 may include: forming a dummy gate structure (not shown) across the channel structure 110 in the isolation layer 115; Forming sidewalls on the sidewalls of the dummy gate structure; forming source-drain doped regions 140 in the channel structure 110 on both sides of the dummy gate structure and the sidewall; forming an interlayer dielectric layer 150 on the isolation layer 115 exposed by the dummy gate structure ; removing the dummy gate structure to form a gate opening (not shown); forming a gate structure 130 in the gate opening.

Wherein, the dummy gate structure is used to occupy a space position for forming the gate structure. Specifically, the dummy gate structure may include a dummy gate oxide layer (not shown in the figure) and a dummy gate layer (not shown in the figure) on the dummy gate oxide layer. As an example, the material of the dummy gate oxide layer is silicon oxide or silicon oxynitride; the material of the dummy gate layer is polysilicon or amorphous silicon.

The gate opening is used to provide a space for forming the gate structure. In this embodiment, the channel structure is taken as an example for description. In other embodiments, when the channel structure is a channel structure layer suspended from the raised portion, after the gate opening is formed, the gate opening exposes the channel structure layer and the sacrificial layer; correspondingly, in After forming the gate opening, the forming method further includes: removing the sacrificial layer to form a through groove. The through groove and the gate opening are connected, and the through groove and the gate opening together provide a space position for forming the gate structure.

Referring to FIG. 11 to FIG. 14 , a source-drain interconnection layer 180 is formed through the source-drain doped region 140 and the interlayer dielectric layer 150 buried on top of the power rail 120 , the source-drain interconnection layer 180 is doped with the source-drain The impurity region 140 is in contact, and the bottom of the source-drain interconnect layer 180 is in contact with the top surface of the buried power rail 120 .

The source-drain interconnection layer 180 is in contact with the source-drain doped region 140 to realize electrical connection between the source-drain doped region 140 and external circuits or other interconnection structures.

The bottom of the source-drain interconnection layer 180 is in contact with the top surface of the buried power supply rail 120, so that the source-drain interconnection layer 180 and the buried power supply rail 120 can be electrically connected, and then when the device is working, the buried power supply rail 120 can be connected to The source-drain doped region 140 supplies power.

Moreover, the bottom of the source-drain interconnection layer 180 is in contact with the top surface of the buried power supply rail 120, so that the electrical connection between the source-drain interconnection layer 180 and the buried power supply rail 120 does not need to be electrically connected through a contact plug (Via), which not only shortens the The current transmission path between the source-drain interconnection layer 180 and the buried power rail 120, and also prevent the excessive resistance of the contact plug from adversely affecting the electrical connection performance between the source-drain interconnection layer and the buried power rail, and optimize the source The electrical connection performance between the drain interconnection layer 180 and the buried power rail 120 improves power supply efficiency.

Specifically, in this embodiment, the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115, so that the source-drain interconnection layer 180 penetrates the source-drain doped region 140 and the interlayer dielectric on the top of the buried power rail 120 layer 150, the source-drain interconnection layer 180 can be in contact with the source-drain doped region 140, and the bottom surface of the source-drain interconnection layer 180 can be in contact with the buried power rail 120, which is beneficial to reduce the source-drain interconnection layer. Difficulty of direct contact between 180 and buried power rail 120.

In other embodiments, when the top surface of the buried power rail is lower than the top surface of the isolation layer, and a covering dielectric layer is formed on the top surface of the buried power rail, the source-drain interconnection layer penetrates through the top of the source-drain doped region. The interlayer dielectric layer, as well as the cover dielectric layer and the interlayer dielectric layer on the top of the buried power rail, also enable the source-drain interconnect layer to be in contact with the source-drain doped region, and the bottom of the source-drain interconnect layer to be in contact with the buried power rail The purpose of top surface contact.

In this embodiment, the source-drain interconnection layer 180 extends longitudinally, and the extension direction of the source-drain interconnection layer 180 is perpendicular to the extension direction of the buried power rail 120 .

In this embodiment, the bottom of the source-drain interconnect layer 180 is flush with the top surface of the buried power rail 120, so that the bottom of the source-drain interconnect layer 180 is in contact with the top surface of the buried power rail 120, and the source and drain The bottom surface of the interconnection layer 180 is not too low, which is beneficial to improve process compatibility and process stability.

In other embodiments, the bottom of the source-drain interconnection layer can also be lower than the top surface of the buried power rail and higher than the top surface of the substrate, correspondingly, the bottom of the source-drain interconnection layer and the top surface of the buried power rail In addition, it is also beneficial to ensure that the bottom of each source-drain interconnection layer can be in contact with the top surface of the buried power rail, reducing the inconsistency of the bottom height of the source-drain interconnection layer, which causes some source-drain interconnection layers to be incompatible with The possibility of contacting the buried power supply rail correspondingly guarantees the electrical connection performance between the source-drain interconnection layer and the buried power supply. Specifically, the source-drain interconnection layer also penetrates part of the thickness of the isolation layer.

The material of the source-drain interconnection layer 180 is a conductive material, and the material of the source-drain interconnection layer 180 includes one or more of W, Co, Cu, Ru and Ni. The resistivity of the material is low, which is beneficial to reduce the resistance of the source-drain interconnection layer 180 , thereby reducing the RC delay and improving the performance of the semiconductor structure.

The specific steps of forming the source-drain interconnection layer 180 in this embodiment will be described in detail below with reference to the accompanying drawings.

As shown in FIG. 11 , a source-drain interconnection groove 160 is formed to penetrate the source-drain doped region 140 and the interlayer dielectric layer 150 on the top of the buried power rail 120 , and the source-drain interconnection groove 160 exposes the top surface of the buried power rail 120 and the source-drain doped region 140. The source-drain interconnection groove 160 is used to provide a space for forming the source-drain interconnection layer. The bottom of the source-drain interconnection groove 160 exposes the top surface of the buried power rail 120 and the source-drain doped region 140, so that the subsequent source-drain interconnection layer can be in contact with the top surface of the buried power rail 120 and the source-drain doped region 140 .

In this embodiment, before the source-drain interconnection groove 160 is formed, a hard mask layer 155 is formed on the interlayer dielectric layer 150, and the hard mask layer 155 is formed with the source-drain doped region 140 and the buried power rail 120. The upper mask opening (not labeled). The hard mask layer 155 is used as an etching mask for forming the source-drain interconnection trench 160 . The mask opening is used to define the shape and position of the source-drain interconnect trench.

The hard mask layer 155 is selected from a material having etching selectivity with the material of the interlayer dielectric layer 150 , such as titanium nitride, titanium oxide or silicon nitride. As an example, the material of the hard mask layer 155 is titanium nitride.

Specifically, the step of forming the source-drain interconnection groove 160 includes: using the hard mask layer 155 as a mask, performing main etching on the source-drain doped region 140 and the interlayer dielectric layer 150 on top of the buried power rail 120 (Main Etch), forming an initial interconnection groove (not shown in the figure), exposing the source and drain doped region 140; performing over etching (Over etch) on the bottom of the initial interconnection groove, so that the initial interconnection groove exposes the buried power supply On top of the rail 120, a source-drain interconnect trench 160 is formed.

In the step of forming the source-drain interconnection groove 160, the bottom of the initial interconnection groove is over-etched, so that the source-drain interconnection groove 160 can expose the top surface of the buried power supply rail 120, so that the existing The process of forming the source-drain interconnection groove 160 and the source-drain interconnection layer, and no additional process is introduced, and the changes to the existing process are small, which is conducive to improving process compatibility and process stability, and is also conducive to saving costs .

In this embodiment, over-etching the bottom of the initial interconnection trench refers to over-etching the dielectric material at the bottom of the initial interconnection trench.

Specifically, in this embodiment, the top surface of the buried power rail 120 is flush with the top surface of the isolation layer 115, and the dielectric material on the top of the buried power rail 120 includes the interlayer dielectric layer 150. Therefore, the bottom of the initial interconnection trench The dielectric material includes an interlayer dielectric layer 150 , and the interlayer dielectric layer 150 at the bottom of the initial interconnect trench is over-etched to expose the top surface of the buried power rail 120 .

In other embodiments, the top surface of the buried power rail is lower than the top surface of the isolation layer, and a cover dielectric layer is formed on the top of the buried power rail; correspondingly, the dielectric material at the bottom of the initial interconnect groove includes an interlayer dielectric layer and a cover dielectric layer, overetching the interlayer dielectric layer and capping dielectric layer at the bottom of the initial interconnect trench to expose the top surface of the buried power rail. Wherein, the dielectric material at the bottom of the initial interconnection groove also includes an isolation layer, and during the process of over-etching the interlayer dielectric layer and the covering dielectric layer at the bottom of the initial interconnection groove, the isolation layer at the bottom of the initial interconnection groove is also etched . Correspondingly, the subsequent source-drain interconnection layer is also located in the part-thick isolation layer.

It should be noted that, during the process of over-etching the bottom of the initial interconnection groove, part of the bottom of the initial interconnection groove is the source-drain doped region 140, and accordingly, the initial interconnection exposed to the source-drain doped region 140 The bottom of the trench is etched. Therefore, after the source-drain interconnection trench 160 is formed, the bottom of the source-drain interconnection trench 160 exposed by the source-drain doping region 140 is lower than the bottom of the source-drain interconnection trench 160 where the source-drain doping region 140 is located.

In an optional solution, a division layer 190 protruding from the bottom of the source-drain interconnection trench 160 is also formed in the source-drain interconnection trench 160, and the division layer 190 longitudinally divides the source-drain interconnection trench 160 located on both sides of the buried power rail 120 . By forming the split layer 190, the source-drain interconnect layer can be disconnected at the position that does not need to be connected based on design requirements, and the source-drain interconnect layer that does not need to be electrically connected to the buried power rail 120 can be connected to the buried power rail 120. The isolation between them improves the design freedom of the source-drain interconnection layer.

Specifically, in this embodiment, in the step of forming the source-drain interconnection trench 160 , a part of the width of the interlayer dielectric layer 150 located between adjacent device regions 100 a in the longitudinal direction is reserved as the partition layer 190 . Correspondingly, the material of the partition layer 190 is the same as that of the interlayer dielectric layer 150 . In some other embodiments, the material of the separation layer may also be different from that of the interlayer dielectric layer, and the material of the separation layer may also be other dielectric materials with an isolation function.

In other embodiments, based on actual process requirements, no separation layer may be formed in the source-drain interconnection trenches, and the source-drain interconnection trenches in adjacent device regions along the vertical direction are connected.

It should be noted that, as shown in FIG. 12 , in this embodiment, after the source-drain interconnection groove 160 is formed, the forming method further includes: forming Silicide layer 170 . The silicide layer 170 is used to reduce the contact resistance between the source-drain interconnection layer and the source-drain doped region 140 , and, when the device is in operation, current flows through the source-drain interconnection layer and through the surface of the silicide layer 170 . In this embodiment, the material of the silicide layer 170 may be nickel silicon compound, cobalt silicon compound or titanium silicon compound.

It should also be noted that, in this embodiment, after forming the source-drain interconnection groove 160 and before forming the silicide layer 170 , the forming method further includes: removing the hard mask layer 155 .

As shown in FIGS. 13 and 14 , the source-drain interconnection layer 180 is filled in the source-drain interconnection groove 160 .

Specifically, a conductive material (not shown) is filled in the source-drain interconnection groove 160, and the conductive material is also formed on the interlayer dielectric layer 150; the conductive material located on the interlayer dielectric layer 150 is removed by using a planarization process, and the remaining The conductive material located in the source-drain interconnection groove 160 is used as the source-drain interconnection layer 180 .

In this embodiment, the process of forming the conductive material may include one or more of a physical vapor deposition process, a chemical vapor deposition process, and an electrochemical plating process. In this embodiment, the planarization process may be a chemical mechanical planarization (CMP) process. The chemical mechanical planarization process is one of the global planarization processes, which is beneficial to improve the flatness and high consistency of the top surface of the source-drain interconnection layer 180 and the interlayer dielectric layer 150 while improving the removal efficiency of conductive materials. .

In an optional solution, when the separation layer 190 protruding from the bottom of the source-drain interconnection groove 160 is also formed in the source-drain interconnection groove 160, along the vertical direction, the source-drain interconnection layer 180 of the adjacent device region 100a is divided by the separation layer 190 quarantined.

It should be noted that the formation of the separation layer 190 during the process of forming the source-drain interconnection trench 160 is taken as an example for illustration. In other embodiments, after the source-drain interconnection layer is formed, a division layer that penetrates part of the source-drain interconnection layer located in the power rail region between adjacent device regions may be formed, and the division layer longitudinally divides the adjacent device region The source-drain interconnection layer of the region.

As an example, the source-drain interconnect layer 180 on either side of the partition layer 190 is in contact with the buried power rail 120 . It should also be noted that, for the convenience of illustration and description, only the dividing layer 190 is illustrated in the cross-sectional view.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. A semiconductor structure, comprising:

a substrate comprising a plurality of discrete device regions and a power rail region located between the device regions;

the convex part is separated on the substrate of the device area;

a channel structure on the boss;

the isolation layer is positioned on the substrate, surrounds the protruding part and exposes the channel structure;

the buried power rail penetrates through the isolation layer of the power rail area and the substrate with partial thickness, and the buried power rail and the bulge are arranged in parallel at intervals;

a gate structure located on the isolation layer and crossing the channel structure;

the source-drain doped region is positioned in the channel structures at two sides of the grid structure;

the interlayer dielectric layer is positioned on the isolation layer at the side part of the grid structure and covers the source drain doped region;

and the source-drain interconnection layer penetrates through the source-drain doped region and the interlayer dielectric layer on the top of the buried power rail, is in contact with the source-drain doped region, and is in contact with the top surface of the buried power rail at the bottom.

2. The semiconductor structure of claim 1, wherein a top surface of the buried power rail is flush with a top surface of the isolation layer; or,

a top surface of the buried power rail is higher than a top surface of the substrate and lower than a top surface of the isolation layer; the semiconductor structure further includes: a covering dielectric layer which is positioned in the isolation layer and positioned on the top surface of the buried power rail; the source-drain interconnection layer penetrates through the interlayer dielectric layer on the top of the source-drain doped region, the covering dielectric layer on the top of the buried power supply rail and the interlayer dielectric layer.

3. The semiconductor structure of claim 1 or 2, wherein a bottom of the source drain interconnect layer is flush with a top surface of the buried power rail; or the bottom of the source-drain interconnection layer is lower than the top surface of the buried power rail and higher than the top surface of the substrate.

4. The semiconductor structure of claim 1, wherein the buried power rail and the channel structure each extend in a lateral direction, a direction perpendicular to the lateral direction being a longitudinal direction; the source-drain interconnection layer extends along the longitudinal direction; the semiconductor structure further includes: and the dividing layer penetrates through part of the source-drain interconnection layer positioned in the power supply rail region, and the dividing layer divides the source-drain interconnection layer positioned in the adjacent device region along the longitudinal direction.

5. The semiconductor structure of claim 4, wherein a bottom surface of said source drain interconnect layer on either side of said spacer layer is in contact with a top surface of said buried power rail; or the bottom surfaces of the source-drain interconnection layers positioned on the two sides of the partition layer are both contacted with the top surface of the buried power rail.

6. The semiconductor structure of claim 1, wherein a top surface of the buried power rail is lower than or flush with a top surface of an isolation layer; the distance between the top surface of the buried power rail and the top surface of the isolation layer is 0nm to 15nm in a direction perpendicular to the surface of the substrate.

7. The semiconductor structure of claim 1, wherein the material of the substrate comprises: one or more of single crystal silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide; the materials of the boss and channel structure include: one or more of single crystal silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide; the material of the buried power rail comprises: one or more of Co, W, ni and Ru.

8. The semiconductor structure of claim 2, further comprising: the gate dielectric layers are positioned between the gate structure and the channel structure and between the gate structure and the isolation layer;

the top surface of the buried power rail is flush with the top surface of the isolation layer, and the gate dielectric layer is also positioned between the buried power rail and the gate structure; or the top surface of the buried power rail is higher than the top surface of the substrate and lower than the top surface of the isolation layer; the gate dielectric layer is also positioned between the cover dielectric layer and the gate structure.

9. The semiconductor structure of claim 8, wherein the gate dielectric layer comprises a material comprising: hfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、La ₂ O ₃ 、Al ₂ O ₃ Silicon oxide and nitrogen-doped silicon oxide.

10. The semiconductor structure of claim 1, wherein a material of the gate structure comprises: any one or more of TiAl, tiALC, taAlN, tiAlN, moN, taCN, alN, ta, tiN, taN, taSiN, tiSiN, W, co, al, cu, ag, au, pt and Ni; the source-drain interconnection layer is made of materials including: one or more of W, co, cu, ru and Ni.

11. The semiconductor structure of claim 1, wherein the channel structure is a fin; the grid electrode structure crosses the fin part and covers part of the top and part of the side wall of the fin part; or the channel structure is a channel structure layer, the channel structure layer and the bulge part are arranged at intervals, and the channel structure layer comprises one or more channel layers which are sequentially arranged at intervals; the gate structure crosses over the channel structure layer and surrounds the channel layer.

12. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a plurality of discrete device areas and power supply rail areas positioned between the device areas, discrete protruding parts are formed on the substrate of the device areas, channel structures are formed on the protruding parts, isolating layers surrounding the protruding parts are formed on the substrate, the isolating layers are exposed out of the channel structures, buried power supply rails are formed in the isolating layers of the power supply rail areas and the substrate with partial thickness, and the buried power supply rails and the protruding parts are arranged in parallel at intervals;

forming a grid structure which is positioned on the isolation layer and crosses the channel structure, source and drain doped regions which are positioned in the channel structure at two sides of the grid structure, and an interlayer dielectric layer which is positioned on the isolation layer at the side part of the grid structure and covers the source and drain doped regions;

and forming a source-drain interconnection layer which penetrates through the source-drain doped region and the interlayer dielectric layer on the top of the buried power rail, wherein the source-drain interconnection layer is contacted with the source-drain doped region, and the bottom of the source-drain interconnection layer is contacted with the top surface of the buried power rail.

13. The method of forming a semiconductor structure of claim 12, wherein in the step of providing a substrate, a top surface of the buried power rail is flush with a top surface of the isolation layer; or,

the top surface of the buried power rail is higher than the top surface of the substrate and lower than the top surface of the isolation layer, and a covering dielectric layer positioned on the top surface of the buried power rail is also formed in the isolation layer; in the step of forming the source-drain interconnection layer, the source-drain interconnection layer penetrates through the interlayer dielectric layer on the top of the source-drain doped region, and the cover dielectric layer and the interlayer dielectric layer on the top of the buried power rail.

14. The method for forming a semiconductor structure according to claim 12, wherein the step of forming the source-drain interconnection layer comprises: forming a source-drain interconnection groove penetrating through the source-drain doped region and the interlayer dielectric layer on the top of the buried power rail, wherein the source-drain interconnection groove exposes the top surface of the buried power rail and the source-drain doped region; and filling the source-drain interconnection layer in the source-drain interconnection groove.

15. The method for forming a semiconductor structure according to claim 14, wherein the step of forming the source-drain interconnection trenches comprises: performing main etching on the source-drain doped region and the interlayer dielectric layer on the top of the buried power rail to form an initial interconnection groove and expose the source-drain doped region; and over-etching the bottom of the initial interconnection groove to enable the initial interconnection groove to expose the top of the buried power rail, so as to form the source-drain interconnection groove.

16. The method of forming a semiconductor structure of claim 14, wherein the buried power rail and the channel structure each extend in a lateral direction, a direction perpendicular to the lateral direction being a longitudinal direction; in the step of forming the source-drain interconnection groove, the source-drain interconnection groove extends along the longitudinal direction, a partition layer protruding out of the bottom of the source-drain interconnection groove is formed in the source-drain interconnection groove, and the partition layer partitions the source-drain interconnection grooves on two sides of the buried power rail along the longitudinal direction;

and along the longitudinal direction, the source-drain interconnection layers adjacent to the device region are isolated by the partition layer.

17. The method of forming a semiconductor structure of claim 12, further comprising: after the source-drain interconnection layers are formed, a partition layer penetrating through a part of the source-drain interconnection layers between adjacent device regions is formed, and the partition layer vertically partitions the source-drain interconnection layers between the adjacent device regions.

18. The method for forming a semiconductor structure according to claim 16 or 17, wherein the source-drain interconnect layer on either side of the dividing layer is in contact with the buried power rail.

19. The method of forming a semiconductor structure of claim 12, wherein a bottom of the source drain interconnect layer is flush with a top surface of the buried power rail; or the bottom of the source-drain interconnection layer is lower than the top surface of the buried power rail and higher than the top surface of the substrate.

20. The method of forming a semiconductor structure of claim 12, wherein the step of providing a substrate comprises: providing a substrate, a raised part separated on the substrate in a device area and a channel structure positioned on the raised part;

forming a layer of isolation material on the substrate surrounding the raised portion and covering the channel structure;

forming a trench through the isolation material layer of the power rail region and a partial thickness substrate;

forming the buried power rail in the trench, a top surface of the buried power rail being higher than a top surface of the substrate and lower than or flush with a top surface of the raised portion;

forming a dielectric material layer filling the trench on the buried power rail;

when the top surface of the buried power rail is lower than the top surface of the protruding part, removing the dielectric material layer and the isolation material layer with partial thickness, wherein the rest isolation material layer is used as an isolation layer, and the rest dielectric material layer on the top surface of the buried power rail is used as a covering dielectric layer; and when the top surface of the buried power rail is flush with the top surface of the bulge part, removing the dielectric material layer and the isolation material layer which are higher than the top surface of the buried power rail, wherein the rest isolation material layer is used as an isolation layer.

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