CN221008951U - integrated circuit - Google Patents

Abstract

An integrated circuit includes: a first standard cell integrating a first pFET and a first nFET; a first gate, a second gate, and a third gate oriented longitudinally along a first direction and arranged in the first standard cell; a first gate contact located on the first gate adjacent to two S/D contacts on two opposite edges of the first gate; a second gate contact located on the second gate adjacent to an S/D contact on one edge of the second gate; and a third gate contact located on the third gate without any S/D contacts around it. The first, second, and third gate contacts extend along a second direction orthogonal to the first direction by a first dimension, a second dimension, and a third dimension, respectively; the first dimension is smaller than the second dimension, and the second dimension is smaller than the third dimension.

Description

integrated circuit

Technical Field

The present invention relates to an integrated circuit, and more particularly to an integrated circuit having a layout integrating multiple standard cells.

Background technique

In the design of integrated circuits (ICs), standard cells with specific functions are reused at a high frequency. Therefore, these standard cells are pre-designed and packaged in a cell library. The cell library is provided to IC designers for specific designs. During the design of the integrated circuit, the standard cells are taken from the cell library and placed at the required location, thereby reducing the design workload. Then, routing is performed to connect the standard cells and other circuit blocks to form the required integrated circuit. Predefined design rules are followed when making standard cells and placing the standard cells at the required locations. For example, a standard cell is placed near another standard cell, and the spacing between the two standard cells is determined according to predefined rules. The spacing reserved between the standard cell and the cell boundary causes the area of the standard cell to increase significantly. In addition, because the active region is separated from the cell boundary, when the standard cells are placed adjacent to each other, even if some active regions in nearby cells need to be electrically coupled, the active regions will not be connected. The separated active regions need to be electrically connected using metal wires. The performance of the resulting device will decrease. The layout pattern and configuration will affect the yield and design performance of the standard cell. In another example, the interconnect structure includes multiple contacts and vias formed on the gate electrode and the active area. However, if these conductive features are designed to be larger in size, short circuit problems will occur due to misalignment and process window. If these conductive features are designed to be smaller in size, the contact resistance will increase and misalignment will cause open circuit problems. Therefore, an integrated circuit layout structure and a method for manufacturing the integrated circuit layout structure are needed to solve the above problems.

Utility Model Content

In a broader embodiment, the present disclosure relates to an integrated circuit (IC). The integrated circuit includes: a first standard cell, the first standard cell integrating a first p-type field effect transistor (pFET) and a first n-type field effect transistor (nFET); a first gate, a second gate, and a third gate, the first gate, the second gate, and the third gate are longitudinally oriented along a first direction and arranged in the first standard cell; a first gate contact on the first gate, the first gate contact is adjacent to two source/drain (S/D) contacts on two opposite edges of the first gate; a second gate contact on the second gate, the second gate contact is adjacent to a single source/drain contact on one edge of the second gate; and a third gate contact on the third gate, the third gate contact is not surrounded by any source/drain contacts. The first gate contact extends a first dimension along a second direction orthogonal to the first direction; the second gate contact extends a second dimension along the second direction; the third gate contact extends a third dimension along the second direction; the first dimension is smaller than the second dimension, and the second dimension is smaller than the third dimension.

Preferably, a first ratio of the second size to the first size is equal to a second ratio of the third size to the second size, and both the first ratio and the second ratio are between 1.2 and 1.5.

Preferably, the integrated circuit further comprises: a second standard cell adjacent to the first standard cell, the second standard cell integrating a second p-type field effect transistor and a second n-type field effect transistor; a first dielectric gate located between the first standard cell and the second standard cell; a second dielectric gate located between the first standard cell and the second standard cell; and a first filling cell disposed between the first standard cell and the second standard cell and extending between the first dielectric gate and the second dielectric gate; wherein the first dielectric gate is located on a boundary of the first standard cell, and the second dielectric gate is located on a boundary of the second standard cell.

Preferably, the first filling unit further includes a third dielectric gate, and the third dielectric gate is sandwiched between the first dielectric gate and the second dielectric gate.

Preferably, the first p-type field effect transistor and the second p-type field effect transistor are formed on a first continuous active region; the first n-type field effect transistor and the second n-type field effect transistor are formed on a second continuous active region; the first continuous active region and the second continuous active region are longitudinally oriented along the second direction; and the first dielectric gate and the second dielectric gate are longitudinally oriented along the first direction and extend from the first continuous active region to the second continuous active region; wherein the first gate extends along the second direction by a fourth dimension; the second gate includes a first segment overlapping with the second gate contact, the first segment extends along the second direction by a first enlarged dimension; the first enlarged dimension is larger than the fourth dimension; the third gate includes a second segment overlapping with the third gate contact, the second segment extends along the second direction by a second enlarged dimension; the second enlarged dimension is larger than the first enlarged dimension;

The ratio of the first enlarged size to the fourth size is between 1.5 and 2; and the ratio of the second enlarged size to the fourth size is between 2 and 3.

In another broader embodiment, the present disclosure relates to an integrated circuit. The integrated circuit includes: a first standard cell, the first standard cell integrating a first p-type field effect transistor (pFET) and a first n-type field effect transistor (nFET), and having a first dielectric gate on the first standard cell boundary; a second standard cell adjacent to the first standard cell, the second standard cell integrating a second p-type field effect transistor and a second n-type field effect transistor, and having a second dielectric gate on the second standard cell boundary; and a first filling cell disposed between the first standard cell and the second standard cell, the first filling cell extending between the first dielectric gate and the second dielectric gate. The first standard cell further includes: a first gate and a second gate oriented longitudinally along a first direction and disposed in the first standard cell; a first gate contact on the first gate, the first gate contact being adjacent to two source/drain (S/D) contacts on two opposite edges of the first gate; and a second gate contact on the second gate, the second gate contact being adjacent to a source/drain contact on one edge of the second gate. The first gate contact extends a first dimension along a second direction orthogonal to the first direction; the second gate contact extends a second dimension along the second direction; and the first dimension is smaller than the second dimension.

Preferably, the first p-type field effect transistor and the second p-type field effect transistor are formed on a first continuous active region; and the first n-type field effect transistor and the second n-type field effect transistor are formed on a second continuous active region.

Preferably, the first continuous active region and the second continuous active region both include a plurality of vertically stacked channels; and the first gate and the second gate both surround the plurality of channels.

Preferably, the integrated circuit further includes: a third gate, oriented longitudinally along the first direction and configured in the first standard unit; and a third gate contact, located on the third gate and without any source/drain contacts around it, wherein the third gate contact extends a third dimension along the second direction, and the third dimension is greater than the second dimension; and a first ratio of the second dimension to the first dimension is equal to a second ratio of the third dimension to the second dimension, and the first ratio and the second ratio are both between 1.2 and 1.5.

Preferably, the first grid extends along the second direction by a fourth dimension; the second grid includes a first segment overlapping with the second grid contact, and the first segment extends along the second direction by a first enlarged dimension; the third grid includes a second segment overlapping with the third grid contact, and the second segment extends along the second direction by a second enlarged dimension; and the first enlarged dimension is greater than the fourth dimension, and the second enlarged dimension is greater than the first enlarged dimension;

The ratio of the first enlarged size to the fourth size is between 1.5 and 2; and the ratio of the second enlarged size to the fourth size is between 2 and 3.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel embodiments are best understood by reading the following embodiments in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, multiple features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of multiple features may be increased or decreased at will.

FIG. 1 is a top view of an integrated circuit (IC) structure manufactured according to an embodiment of the present invention.

FIG. 2A is a top view of an integrated circuit structure manufactured according to an embodiment of the present invention.

2B, 2C, and 2D are cross-sectional views of the integrated circuit structure in FIG. 2A manufactured according to an embodiment of the present invention.

FIG. 2E is a top view of the integrated circuit structure in FIG. 2A manufactured according to an embodiment of the present invention.

3A, 3B and 3C are cross-sectional views of a gate in an integrated circuit structure according to an embodiment of the present invention.

FIG. 4A is a top view of an integrated circuit structure manufactured according to an embodiment of the present invention.

FIG. 4B is a top view of the integrated circuit structure in FIG. 4A manufactured according to an embodiment of the present invention.

FIG. 4C is a top view of an integrated circuit structure manufactured according to an embodiment of the present invention.

FIG. 4D is a top view of the integrated circuit structure in FIG. 4C manufactured according to an embodiment of the present invention.

5A and 5B are top views of an integrated circuit structure manufactured according to an embodiment of the present invention.

6A, 6B, and 6C are cross-sectional views of the integrated circuit structure in FIG. 4A manufactured according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view of the integrated circuit structure in FIG. 4A manufactured according to an embodiment of the present invention.

8A and 8B are top views of an integrated circuit structure manufactured according to an embodiment of the present invention.

The reference numerals are described as follows:

10, 20: Integrated circuit structure (IC structure)

12: Semiconductor substrate (substrate)

12A, 22A: Upper surface

14: Standard cell/first standard cell

16: Standard cell/second standard cell

18: Filling unit

21: Standard cell/standard IC cell

22: Active area/Fin-type active area/First active area/Second active area

24: Isolation components

26: Negatively doped well (n well)

28: Positive doping well (p well)

30: Gate

30A, 30B: Segment

32: Gate stack

34: Gate spacer

36: Source/drain component (S/D component)

38: Channel

40: Dielectric Gate

42: Gate dielectric layer

42A: Interface layer

42B: High dielectric constant dielectric material layer

44: Gate electrode

44A: Work function metal layer

44B: Filler Metal

46: Interconnection structure

48: Interlayer dielectric layer (ILD layer)

48A: first interlayer dielectric layer (first ILD layer)

48B: second interlayer dielectric layer (second ILD layer)

50: Gate contact

50A: Gate contact/first type gate contact

50B: Gate contact/second type gate contact

50C: Gate contact/third type gate contact

52: First source/drain contact (first S/D contact)

54: Second source/drain contact (second S/D contact)

56: First Metal Wire

58: Common Edge

60A: First etch stop layer

60B: Second etch stop layer

62, 64: p-type FET (pFET)

66, 68: n-type FET (nFET)

D1: Size/First Size

D2: Dimension/Second Dimension

D3: Dimension/Third Dimension

D4, D5, Df, H: Dimensions

G1: Dimension/Fourth Dimension

G2: Size/first amplification size

G3: Size/Second Amplification Size

P: Gate pitch/pitch size

S1, S2: Interval

Detailed ways

A plurality of different embodiments or examples are provided below to realize the different features of the subject matter provided. Reference numbers and/or letters are repeated in a plurality of examples. Such repetition is for simplicity and clarity and is not used to determine the relationship between a plurality of embodiments and/or configurations. In addition, the following describes specific examples of components and arrangements to simplify the embodiments of the present invention. These examples are of course only examples and should not be limiting. For example, in the following embodiments, the formation of a first feature on a second feature may include an embodiment in which the first feature and the second feature are directly in contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, in which case the first feature and the second feature are not in direct contact. In addition, in the present disclosure, the formation of a feature on another feature, connected to another feature, and/or coupled to another feature may include an embodiment in which the feature is directly in contact, and may also include an embodiment in which an additional feature is formed between these features so that these features are not in direct contact.

In addition, the present disclosure will repeat reference numbers and/or letters in multiple examples. Such repetition is for simplicity and clarity, and is not used to describe the relationship between multiple embodiments and/or configurations. In addition, in the present disclosure, the formation of a feature on another feature, connected to another feature, and/or coupled to another feature may include an embodiment in which the features are directly contacted, and may also include an embodiment in which additional features are sandwiched between these features so that these features are not directly contacted. In addition, spatial relative relationship terms, such as "lower than", "higher than", "horizontally", "vertically", "above", "above", "below", "below", "up", "down", "top", "bottom", etc., and derived terms therein (such as "horizontally", "downwardly", "upwardly", etc.) are used here for convenience to describe the relationship between one element or feature and another element or feature. Spatial relative relationship terms are intended to include different directions of the device in use or operation other than the direction described in the figure. In addition, when "about", "approximately", or similar terms are used to describe a number or a range of numbers, the above terms include the numbers described based on the specific technology disclosed herein and according to the knowledge of those of ordinary skill in the art, within a specific variation (such as +/-10% or other variations). For example, the term "about 5 nm" includes a range from 4.5 nm to 5.5 nm.

The present disclosure provides various embodiments of an integrated circuit (IC) formed on a semiconductor substrate. The integrated circuit has a design layout that integrates multiple standard cells. A standard cell is an IC structure pre-designed for use in a separate IC design. An effective IC design layout includes multiple pre-designed standard cells and pre-defined rules for placing the standard cells to improve circuit performance and reduce circuit area.

FIG. 1 is a top view of an integrated circuit (IC) structure 10, which is manufactured according to various embodiments of the present invention. In some embodiments, the IC structure 10 is formed on a planar active region and includes a field-effect transistor (FET). In some embodiments, the IC structure 10 is formed on a fin active region and includes a fin field effect transistor (FinFET). In other embodiments, the IC structure 10 is formed on an active region having multiple channels, and the channels are vertically stacked on the active region, such as a gate-all-round field-effect transistor (GAA FET). The IC structure 10 is used as an example to describe an IC structure and a method for designing, integrating, and manufacturing a standard cell.

In various embodiments, the IC structure 10 includes one or more standard cells placed into the IC layout by predefined rules. These standard cells are repeatedly used in integrated circuit design and are therefore predefined and stored in a standard cell library according to manufacturing technology. IC designers can obtain these standard cells, integrate them into their IC designs, and place them into the IC layout according to predefined placement rules. Standard cells can include a number of basic circuit devices commonly used in digital circuit design applications, such as inverters, AND, NAND, OR, XOR, and NOR, such as central processing units (CPUs), graphic processing units (GPUs), and system on chip (SOC) chip designs. Standard cells can include other commonly used circuit blocks, such as flip-flop circuits and latches.

IC structure 10 includes semiconductor substrate 12 (substrate 12). Semiconductor substrate 12 includes silicon. Optionally, substrate 12 may include elemental semiconductors, such as silicon or germanium in a crystalline structure; compound semiconductors, such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; or combinations thereof. Substrate 12 may also include a silicon-on-insulator (SOI) substrate. SOI substrates are manufactured using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods.

The substrate 12 also includes a plurality of isolation features, such as isolation features formed on the substrate 12 and defining a plurality of active regions on the substrate 12. The isolation features use isolation techniques, such as shallow trench isolation (STI), to define and electrically isolate the plurality of active regions. Each active region is surrounded by a continuous isolation feature, such that the active region is separated from adjacent active regions. The isolation features include silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof.

The IC structure 10 only illustrates two standard cells 14 and 16 located next to each other. The standard cells 14 and 16 can be placed on a common boundary line, or optionally placed at a distance so that a filling cell 18 is sandwiched between the standard cells 14 and 16. The filling cell 18 is configured between the standard cells to provide appropriate separation and isolation. The filling cell 18 includes a plurality of components, such as an active region, a gate stack, etc. However, these components are not configured as components of the integrated circuit, but are placed to provide effective isolation for the standard cells and to enhance the performance of the integrated circuit. The standard cells 14 and 16 can have the same size, or optionally have different sizes. In the illustrated embodiment, the standard cell 14 extends along the X direction by a dimension D1, the standard cell 16 extends along the X direction by a dimension D2, and the standard cells 14 and 16 extend along the Y direction by the same dimension H. The filling cell 18 extends along the X direction by a dimension Df.

FIG. 2A is a top view of an integrated circuit (IC) structure 20, and FIG. 2B, FIG. 2C, and FIG. 2D are cross-sectional views of the IC structure 20 manufactured according to an embodiment of the present invention along dashed lines BB', CC', and DD', respectively. In some embodiments, the IC structure 20 is formed on a flat active region and includes a field effect transistor (FET). The IC structure 20 only illustrates one standard cell 21, which may be, for example, the standard cell 14 or the standard cell 16.

The substrate 12 also includes a plurality of isolation features 24 formed on the substrate 12 and defining a plurality of active regions 22 on the substrate 12. The isolation features 24 use isolation technology (e.g., shallow trench isolation (STI)) to define the plurality of active regions 22 and electrically isolate the plurality of active regions 22. Each active region 22 is surrounded by a continuous isolation feature 24, so that the active region 22 is separated from other adjacent active regions. The isolation features 24 include silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The isolation features 24 are formed by any suitable process. As an example, forming the STI features includes a lithography process to expose a portion of the substrate, etching a trench in the exposed portion of the substrate (for example, by using dry etching and/or wet etching), filling the trench by depositing one or more dielectric materials, and planarizing the substrate and removing excess portions of the dielectric material by a polishing process, such as a chemical mechanical polishing (CMP) process. In some examples, the isolation feature 24 may have a multi-layer structure, such as a thermal oxide liner layer of silicon nitride or silicon oxide and a filling layer.

The active region 22 is a region of a semiconductor surface in which a plurality of doped features are formed and used for one or more devices, such as diodes, transistors, and/or other suitable devices. The active region 22 may include a semiconductor material similar to the bulk semiconductor material (e.g., silicon) of the substrate 12, or a different semiconductor material, such as silicon germanium (SiGe), silicon carbide (SiC), or multiple semiconductor material layers (e.g., alternative silicon and silicon germanium layers) formed on the substrate 12 by epitaxial growth to enhance performance, such as strain effects to increase carrier mobility.

In the disclosed embodiment, the active region 22 is three-dimensional, such as a fin-type active region (active region 22 is also referred to as fin-type active region 22) extending vertically to the isolation component. The fin-type active region 22 protrudes from the substrate 12 and has a three-dimensional profile to more effectively couple between the channel and gate electrodes of the FET. In detail, the substrate 12 has an upper surface 12A, and the fin-type active region 22 has an upper surface 22A on the upper surface 12A of the substrate 12. The fin-type active region 22 can be formed by selectively etching to recess the isolation component 24, or by selective epitaxial growth to grow the active region using the same or different semiconductor material from the substrate 12, or a combination thereof. In the disclosed embodiment, the fin-type active region 22 is oriented longitudinally along the X direction.

The semiconductor substrate 12 further includes a plurality of doped components, such as an n-type doped well, a p-type doped well, source and drain components, other doped components, or combinations thereof, which are configured to form a plurality of devices or components of a device, such as source and drain components of a field effect transistor. In the example illustrated in FIG. 2A , the IC structure 20 includes a negatively doped well (also referred to as an n-well) 26 and a positively doped well (also referred to as a p-well) 28 as shown in FIG. 2A . The n-well 26 includes a negative dopant, such as phosphorus. The p-well 28 includes a positive dopant, such as boron. The n-well 26 and the p-well 28 are formed by suitable techniques, such as ion implantation, diffusion, or combinations thereof. In the present embodiment, two fin-type active regions 22 are formed in the n-well 26, and another two fin-type active regions 22 are formed in the p-well 28. In some embodiments, each doped well (n-well 26 or p-well 28 ) may include more or fewer fin-type active regions 22 , such as one, three, four, or any suitable number of fin-type active regions 22 .

A plurality of IC devices are formed on the semiconductor substrate 12. The IC devices include fin field-effect transistors (FinFETs), diodes, bipolar transistors, image sensors, resistors, capacitors, conductors, memory cells, or combinations thereof. In FIG. 2A , the exemplary FinFET is only schematically illustrated.

The IC structure 20 further includes a plurality of gates 30, which are long strips oriented longitudinally along the Y direction. In the present embodiment, the X and Y directions are orthogonal and define the upper surface of the semiconductor substrate 12. The gate 30 includes a gate stack 32, and the gate stack 32 further includes a dielectric layer and a gate electrode. The gate 30 may further include a gate spacer 34, which is located on the sidewall of the gate stack and has one or more functions, such as providing isolation between the gate electrode and the source/drain (S/D) components. The gate spacer 34 includes one or more dielectric materials, such as silicon oxide, silicon nitride, other suitable dielectric materials, or a combination thereof. The gate spacer 34 is formed by a suitable process, such as depositing a dielectric material and not anisotropic etching, such as plasma etching. The gate stack 32 is a component of the FET and operates in conjunction with other components, such as source/drain (S/D) components 36 and channel 38, wherein channel 38 is located in the portion of the active region directly below the gate stack 32; S/D components 36 are located in the active region and on both sides of the gate stack 30. As used herein, source/drain (S/D) components may refer to the source or drain of a device. Source/drain (S/D) components may also refer to regions that provide multiple device sources and/or drains. It should be noted that the gate 30 should not be confused with a logic gate (e.g., a NOR logic gate). The gate stack 32 is described in more detail below.

In some embodiments, the IC structure 20 also includes a dielectric gate 40 located on the semiconductor substrate. The dielectric gate 40 is not a gate and does not have the function of a gate. In contrast, the dielectric gate 40 is, for example, a dielectric component including one or more dielectric materials and has the function of a dielectric component. In some embodiments, the dielectric gate 40 is added to adjust the gate density to improve manufacturing. For example, when the gate density is uniform, a CMP process can be applied to the IC structure 20, and a better and improved planarization effect can be achieved. In the disclosed embodiment, as shown in FIG. 2E in a top view, the dielectric gate 40 is formed on the boundary of the standard cell 21.

Each dielectric gate 40 is also a long strip oriented longitudinally along the Y direction. The dielectric gate 40 is similar to the gate 30 in formation. In some embodiments, the gate 30 and the dielectric gate 40 are formed together by a process, such as a gate-last process. In a further embodiment, a dummy gate is first formed by deposition and patterning, wherein the patterning further includes a lithography process and etching. After forming the source/drain components, the dummy gate is removed by selective etching. Thereafter, a portion of the dummy gate is replaced to form the gate 30 by depositing a gate dielectric layer and a gate electrode, and the remaining dummy gate is replaced to form the dielectric gate 40 by depositing a single or multiple dielectric materials. A CMP process can then be used to remove excess material from the gate 30 and the dielectric gate 40. In addition, the arrangement and configuration of the dielectric gate 40 are different and therefore have different functions. In this embodiment, some dielectric gates 40 are placed on the boundaries of standard cells to perform an isolation function to separate one standard cell from an adjacent standard cell, and some dielectric gates 40 are placed in the standard cell for one or more considerations, such as isolation between adjacent FETs and adjusting pattern density. Therefore, the dielectric gates 40 provide isolation between adjacent IC devices and additionally provide a function of adjusting pattern density to improve manufacturing, such as etching, deposition, and CMP.

In the above-mentioned multiple embodiments, the gate stack 32 is further described according to multiple embodiments with reference to the cross-sectional views of Figures 3A to 3C. As shown in Figure 3A, the gate stack 32 includes a gate dielectric layer 42 (such as silicon oxide) and a gate electrode 44 (such as doped polysilicon) located on the gate dielectric layer 42.

In some embodiments, the gate stack 32 may alternatively or additionally include other materials suitable for circuit performance and manufacturing integration. For example, as shown in FIG. 3B , the gate dielectric layer 42 includes an interfacial layer 42A (e.g., silicon oxide) and a high-k dielectric material layer 42B. The high-k dielectric material may include metal oxides, metal nitrides, or metal oxynitrides. In many examples, the high-k dielectric material layer 42B includes metal oxides ZrO ₂ , Al ₂ O ₃ , and HfO ₂ , and the above metal oxides are formed by a suitable method, such as metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE). In some examples, the interfacial layer includes silicon oxide formed by ALD, thermal oxidation, or ultraviolet-ozone oxidation. The gate electrode 1204 includes a metal, such as aluminum, copper, tungsten, metal silicide, doped polysilicon, other suitable conductive materials, or a combination thereof. The gate electrode may include a plurality of conductive films, such as a capping layer, a work function metal layer, a blocking layer, and a filling metal layer (such as aluminum or tungsten). The plurality of conductive films are designed to have work functions that match n-type FETs (nFETs) and p-type FETs (pFETs), respectively. In some embodiments, the gate electrode of the nFET includes a work function metal whose composition is designed to have a work function less than or equal to 4.2 eV, and the gate electrode of the pFET includes a work function metal whose composition is designed to have a work function greater than or equal to 5.2 eV. For example, the work function metal layer of the nFET includes tantalum, titanium aluminum, titanium aluminum nitride, or a combination thereof. In other examples, the work function metal layer of the pFET includes titanium nitride, tantalum nitride, or a combination thereof.

In some embodiments illustrated in FIG. 3C , the gate stack 32 is formed by different methods and has different structures. The gate stack 32 can be formed by a plurality of deposition techniques and suitable processes, such as a gate-last process, in which a dummy gate is first formed, and after the source/drain components are formed, the dummy gate is replaced by a metal gate. Optionally, the gate stack 32 is formed by a high-k last process, in which the gate dielectric layer and the gate electrode are replaced by a high-k dielectric material and a metal, respectively, after the source/drain components are formed. In the high-k last process, a dummy gate is first formed by deposition and patterning; then source/drain components are formed on multiple sides of the gate stack, and an inter-layer dielectric layer is formed on the substrate; the dummy gate is removed by etching to form a gate trench; and then a gate material (including the material of the gate dielectric layer and the gate electrode) is deposited in the gate trench. In this example, the gate electrode 44 includes a work function metal layer 44A and a fill metal 44B, such as aluminum or copper. The gate stack 32 thus formed has multiple gate material layers in a U-shape. The composition of the gate electrode 44 and multiple conductive features in the interconnect structure (described below) is well designed for material integration, manufacturing, and device performance based on experimental data, simulations, and analysis. In the disclosed embodiment, the gate electrode 44 does not have tungsten (W), but includes titanium nitride (TiN) (such as the gate electrode of a p-type FET), or includes titanium aluminum nitride (TiNAl) (such as the gate electrode of an n-type FET).

The IC structure 20 includes a plurality of standard cells placed and configured on the semiconductor substrate 12 according to predefined rules. A standard cell is a group of logic transistors and interconnect structures that provide a Boolean function or a storage function (such as a trigger or a latch). The standard cells are pre-designed and collected in an IC standard cell library to be reused during IC design to achieve compatible, consistent, and efficient IC design and IC manufacturing. A filler cell is an IC design block inserted between two adjacent standard cells to be compatible with IC design and IC manufacturing rules. Appropriate design and configuration of standard cells and filler cells can increase packaging density and circuit performance. In the embodiment illustrated in FIG. 2E , each standard cell includes two dielectric gates configured on two boundary lines oriented along the Y direction. Each filler cell may include two dielectric gates located on two boundary lines oriented along the X direction. In addition, the standard cell and the adjacent filler cell share a dielectric gate located on a common boundary.

Referring back to FIGS. 2A-2D , the IC structure 20 further includes an interconnect structure 46 disposed on the substrate 12 and configured to couple a plurality of devices into the integrated circuit. The interconnect structure 46 includes metal lines distributed in a plurality of metal layers, the metal lines being used for horizontal routing, vias, and contacts to provide vertical connections between adjacent metal layers, or between the lowest metal layer and the substrate 12 or other device components (e.g., gate electrodes) formed on the substrate 12. A plurality of conductive components are embedded in an interlayer dielectric (ILD) layer 48, or additionally embedded in an etch-stop layer (ESL) disposed below the ILD layer 48. The ILD layer 48 includes one or more suitable dielectric materials, such as a low-k dielectric material, silicon oxide, other suitable dielectric materials, or combinations thereof. The ILD layer 48 is formed by a suitable process, such as deposition and chemical mechanical polishing (CMP).

In the disclosed embodiment, the interconnect structure 46 includes a gate contact 50, which is located on the gate 30 and electrically connected to the gate electrode of the gate 30. The gate contact 50 includes one or more conductive materials, such as titanium (Ti), titanium nitride (TiN), tungsten (W), or a combination thereof. In one embodiment, the gate contact 50 includes bulk tungsten (bulk W) and a conformal barrier layer of Ti and TiN surrounding the bulk tungsten. The formation of the gate contact 50 includes patterning the ILD layer 48, depositing the conductive material, and CMP. In particular, the gate contact 50 is formed differently and composed differently from the S/D features 36 to optimize manufacturing capabilities and process windows, which will be described in more detail below with respect to the S/D contacts.

The interconnect structure 46 includes S/D contacts formed separately in two layers, each of which is formed by a process including deposition, lithography, patterning, and etching. In detail, the interconnect structure 46 includes a first source/drain (S/D) contact 52 located on the S/D component 36, and a second source/drain (S/D) contact 54 located above the first S/D contact 52. The first S/D contact 52 and the second S/D contact 54 are different in composition and formation. In the disclosed embodiment, the first S/D contact 52 includes tungsten (W), and the second S/D contact 54 includes tungsten (W) or ruthenium. The first S/D contact 52 and the second S/D contact 54 are formed by separate processes, wherein each process includes lithography patterning, etching, deposition, and CMP according to some embodiments. In addition, the process for forming the gate contact 50 is separate from the process for forming the first S/D contact 52 and the process for forming the second S/D contact 54. As described below, the contact structure, manufacturing process, and composition are designed as such because of a number of considerations, manufacturing data, and simulation data. As IC technology advances to more advanced technology nodes with smaller feature sizes, the contact size and the spacing between the contact and the adjacent conductive features also decrease. Therefore, misalignment tolerance is reduced due to the reduced spacing, gap (trench or hole) filling capability during conductive material deposition is also reduced due to the reduction in the opening size of the trench, and contact conductivity is also reduced as the contact size is reduced to below the mean free path of the corresponding material. Therefore, the S/D contact structure is distributed in two layers with higher freedom, with higher freedom of different sizes and different compositions, so that the first S/D contact 52 is designed to have a smaller size and use a conductive material to have a high gap filling efficiency, and the second S/D contact 54 is designed to have a larger size and use a conductive material to have gap filling efficiency and conductivity. For example, the composition of the second S/D contact 54 is designed to be, for example, tungsten (W) or ruthenium (Ru). In a more detailed example, ruthenium has a relatively high conductivity when the contact size is reduced below a certain size, and ruthenium can be better integrated with the ILD layer. Therefore, the barrier layer can be removed without interdiffusion problems, and the size of the bulk ruthenium is relatively enlarged. For the gate contact 50, when formed separately, the misalignment problem can be improved by increasing the patterning resolution due to multi-patterning technology, such as a self-aligned process including selective deposition, self-aligned etching, or a combination thereof. In addition, the gate contact 50 can be designed more freely in terms of size and composition. For example, the gate contact 50 can use tungsten, or can further include Ti/TiN as a barrier layer and the gate electrode has no tungsten to achieve etching selectivity and reduce gate damage during the formation of the gate stack 50.

The gate contact 50, the first S/D contact 52, and the second S/D contact 54 can be formed in any suitable order to optimize manufacturing performance. In some embodiments, the first S/D contact 52 is first formed by a damascene process, which includes patterning the ILD layer 48 to form a contact hole (or contact trench); filling the corresponding conductive material by deposition; and CMP. Then, the second S/D contact 54 is formed by a process similar to the process of forming the first S/D contact 52. Then, the gate contact 50 is formed by a process similar to the process of forming the first S/D contact 52.

Additional design standard cells are further applied to the contacts, including location, size, shape, or a combination thereof, which will be further described below. The first S/D contact 52 and the second S/D contact 54 have different shapes and configurations, such as shown in FIG. 2A. In the disclosed embodiment, as shown in FIG. 2A, the first S/D contact 52 is a long strip oriented longitudinally along the Y direction, and extends to the adjacent active region 22 and is electrically connected to the adjacent active region 22, and the second S/D contact 54 is square and is located on the first S/D contact 52. In a further embodiment, the second S/D contact 54 extends in the same direction (X direction) with a smaller dimension than the first S/D contact 52, so that the second S/D contact 54 is completely located on the first S/D contact 52. In some embodiments, the first S/D contact 52 extends from the n-well 26 to the p-well 28 on multiple active regions, and the corresponding second S/D contact 54 is located on the first S/D contact 52 and can be configured in the n-well 26 or the p-well 28.

4A to 4D are top views of a standard IC cell 21 manufactured according to a plurality of embodiments. In the disclosed embodiment, the standard IC cell 21 includes a plurality of active regions, for example, 2 to 10 active regions. The elongated active region 22 of the standard IC cell 21 is longitudinally oriented along the X direction, and the gate 30 is longitudinally oriented along the Y direction. In the disclosed embodiment, the standard IC cell 21 includes a dielectric gate 40 located on the cell boundary line. In some embodiments, the dielectric gate 40 located on the cell boundary line may be replaced by a metal gate 30, depending on individual applications and design considerations. The active region 22 may be a planar active region or a fin-type active region, or an active region having a plurality of vertically stacked channels, such as a gate-all-around (GAA) structure.

For the gate contact 50, the configuration is divided into three categories/types, which are described in more detail with reference to Figures 4A to 4D. The three types of gate contacts 50 are configured in different environments. The first type of gate contact 50 is called gate contact 50A (first type gate contact 50A), as shown in Figure 4A, the gate contact 50A is configured at a position where both sides along the X direction are next to the S/D contact. The second type of gate contact 50 is called gate contact 50B (second type gate contact 50B), as shown in Figure 4A, the gate contact 50B is configured at a position where one side along the X direction is next to the S/D contact. The third type of gate contact 50 is called gate contact 50C (third type gate contact 50C), as shown in Figure 4A, the gate contact 50C is configured at a position where there is no S/D contact on both sides along the X direction or far away from the S/D contact. The S/D contact is located next to the gate contact is called adjacent. Typically, the gate 30 is uniformly configured to have a gate pitch P, as shown in FIG8A , where the gate pitch P is defined as the dimension from the edge of the gate to the same edge of the adjacent gate. Here, the S/D contact adjacent to the gate contact is defined as the distance between the S/D contact and the gate contact being less than or equal to the gate pitch P/2. If the gate contact is adjacent to no S/D contact, the gate contact is referred to as having no S/D contact.

The three types of gate contacts 50 are configured in different environments, and therefore have different freedoms and different levels of concern, and are therefore designed with different sizes and shapes. Design considerations include the trade-off between larger size (resulting in lower contact resistance) and smaller size (resulting in fewer short circuit issues and a larger process window).

The first type gate contact 50A is designed to be smaller in size D1 to avoid short circuit problems because it is subject to more stress (constrain) from the environment. The second type gate contact 50B is configured to be an intermediate size D2 to avoid less stringent short circuit problems because only one side is subject to stress. Size D2 is greater than size D1. In the disclosed embodiment, the ratio of size D2 to size D1 (size D2/size D1) is between 1.2 and 1.5. In some embodiments, the first type gate contact 50A is square and the second type gate contact 50B is rectangular (also called a slot contact). In addition, the second type gate contact 50B can be located in an asymmetric position so that the center is offset from the side with the S/D contact to the side without any S/D contact.

The third type gate contact 50C is designed to have a larger dimension D3 (third dimension) to increase the contact area and reduce the contact resistance because there is no open space for stress from both sides. In the disclosed embodiment, the ratio of dimension D3 to dimension D2 (dimension D3/dimension D2) and the ratio of dimension D2 to dimension D1 (dimension D2/dimension D1) are the same. In further embodiments, the ratio of dimension D3 to dimension D2 (dimension D3/dimension D2) is between 1.2 and 1.5. In some embodiments, the third type gate contact 50C is rectangular because the third type gate contact 50C has the freedom to extend to both sides. In addition, the third type gate contact 50C can be located in a symmetrical position so that the center is aligned with the center of the gate 30 along the X direction. In particular, the third type gate contact 50C extends beyond the edge of the gate 30 on each side with a margin greater than 20%.

The first S/D contact 52 and the second S/D contact 54 are also designed to have appropriate sizes to optimize the process window and the contact area. The first S/D contact 52 extends along the X direction by a dimension D4, and the second S/D contact 54 extends along the X direction by a dimension D5, wherein the dimension D4 is different from the dimension D5. In detail, according to various embodiments, the dimension D4 is greater than the dimension D5. In further embodiments, the ratio of the dimension D4 to the dimension D5 (dimension D4/dimension D5) is between 1.2 and 1.4. In some embodiments, the ratio of the dimension D4 to the dimension D1 (dimension D4/dimension D1) is between 0.8 and 1.2.

The interconnect structure 46 includes metal lines distributed in multiple metal layers and vias, and the metal lines are configured between adjacent metal layers for vertical connection. The first metal line 56 in the first metal layer (the lowest metal layer) (as shown in FIG. 4B ) is electrically connected to multiple device elements, such as the S/D components 36 and the gate electrode 44 through respective contacts, such as the first S/D contact 52, the second S/D contact 54, and the gate contact 50. In some embodiments, the first metal line 56 located on the IC structure 20 includes an odd number (2n+1) of first metal lines oriented longitudinally along the X direction. In this case, as shown in FIGS. 4A and 4B , the 2n first metal lines are symmetrically distributed on the n-well 26 and the p-well 28, and one first metal line 56 is located on the common edge 58 of the n-well 26 and the p-well 28.

In alternative embodiments, the first metal lines 56 are unevenly distributed to create more spacing for the gate contact 50. In some embodiments shown in FIG. 4B, the first metal line 56 located at the center is spaced S1 from the adjacent first metal line, and the other first metal lines 56 in the IC structure 20 are spaced S2 from the adjacent first metal lines, and the spacing S2 is smaller than the spacing S1. Therefore, the gate contact 50C and the first metal line 56 located at the center have an increased alignment margin and an improved process window. In some embodiments, the ratio of spacing S1 to spacing S2 (spacing S1/spacing S2) is between 1.2 and 1.4.

In some embodiments, the first metal lines 56 on the IC structure 20 include an even number (2n) of first metal lines oriented longitudinally along the X direction. In this case, as shown in FIGS. 4C and 4D , the 2n first metal lines are symmetrically distributed on the n-well 26 and the p-well 28, and the common edge 58 of the n-well 26 and the p-well 28 falls in the gap between adjacent first metal lines.

In some optional embodiments, the gate 30 also uses its own freedom to adjust the shape and size to increase the alignment window and contact area (and increase contact conductivity). As shown in FIG. 5A, the gate 30 associated with the gate contact 50C includes a segment 30A, the size of the segment 30A increases along the X direction, so that the gate contact 50C can be located on the segment 30A with an adjusted shape and size to have an increased contact area and improved alignment/manufacturing margin. The gate 30 extends along the X direction by a dimension G1 (a fourth dimension), and the shaped segment 30A extends along the X direction by a dimension G2 (a first enlarged dimension). In the disclosed embodiment, the ratio of the dimension G2 to the dimension G1 (dimension G2/dimension G1) is between 2 and 3. In other embodiments, the ratio of the dimension G2 to the dimension D3 (dimension G2/dimension D3) is between 1.5 and 2. In some embodiments, the ratio of the corresponding dimensions of the segment 30A and the gate contact 50C along the Y direction has a similar range, such as between 1.2 and 1.5.

In some optional embodiments, as shown in FIG. 5B , the gate 30 with respect to the gate contact 50B includes a segment 30B whose size increases along the X direction so that the gate contact 50B can be located on the segment 30B that has been shaped and sized to have an increased contact area and improved alignment/manufacturing margin. The shaped segment 30B extends along the X direction by a dimension G3 (a second enlarged dimension). In the disclosed embodiment, the ratio of the dimension G3 to the dimension G1 (dimension G3/dimension G1) is between 1.3 and 2. In other embodiments, the ratio of the dimension G3 to the dimension D2 (dimension G3/dimension D2) is between 1.2 and 1.5. In detail, as shown in FIG. 5B , the shaped segment 30B is offset toward the free side so that the segment 30B protrudes substantially toward the free side and the edge on the other side is substantially aligned with the other edge of the gate 30. In some embodiments, the ratio of the corresponding dimensions of the segment 30B and the gate contact 50B along the Y direction has a similar range, such as between 1.2 and 1.5.

The IC structure 20 is described in more detail in FIGS. 6A to 6C . FIGS. 6A to 6C are cross-sectional views of the IC structure 20 manufactured according to the present invention along the dotted line AA', the dotted line BB', and the dotted line CC' of FIG. 4A , respectively. As described above, a plurality of contacts are formed separately. The ILD structure includes multiple layers, each of which is patterned to form contacts respectively. In addition, an etch stop layer 60 is additionally disposed under the corresponding ILD layer 48 to achieve etching selectivity. In this case, the etch stop layer 60 and the ILD layer 48 have different components with different etching selectivities. In particular, the first S/D contact 52 and the second S/D contact 54 are formed in different ILD layers 48 and the corresponding etch stop layer 60.

The first S/D contact 52 is formed in the following manner. As shown in FIG. 6A , a first etch stop layer 60A is deposited conformably, and a first interlayer dielectric (ILD) layer 48A is deposited on the first etch stop layer 60A. In some embodiments, the first etch stop layer 60A includes silicon nitride or silicon oxynitride, and the first ILD layer 48A includes silicon oxide, a low-k dielectric material, or a combination thereof. A CMP process is applied to planarize the upper surface. Thereafter, the first ILD layer 48A and the first etch stop layer 60A are patterned to form a contact hole of the first S/D contact 52 using an etching process. The etching process includes a first etching process (e.g., wet etching or dry etching) and a second etching process after the first etching process, wherein the etchant used in the first etching process selectively etches the first ILD layer 48A and stops on the first etching stop layer 60A. The second etching process is, for example, wet etching, and the etchant used in the second etching process selectively etches the first etching stop layer 60A. Therefore, the etching process described above can avoid over-etching the first ILD layer 48A and damaging the substrate and device components, such as the S/D components 36. A conductive material is disposed in the contact hole, and another CMP process is applied to planarize the upper surface, thereby forming the first S/D contact 52.

The second S/D contact 54 is formed in a similar manner, but the second S/D contact 54 is formed in the second interlayer dielectric (ILD) layer 48B and the second etch stop layer 60B. As shown in FIG. 6A , the second etch stop layer 60B is deposited conformably, and the second ILD layer 48B is deposited on the second etch stop layer 60B. In some embodiments, the second etch stop layer 60B includes silicon nitride or silicon oxynitride, and the second ILD layer 48B includes silicon oxide, a low-k dielectric material, or a combination thereof. A CMP process is applied to planarize the upper surface. Thereafter, the second ILD layer 48B and the second etch stop layer 60B are patterned to form a contact hole for the second S/D contact 54 using an etching process. The etching process includes a first etching process (e.g., wet etching or dry etching) and a second etching process after the first etching process, and the etchant used in the first etching process selectively etches the second ILD layer 48B and stops on the second etch stop layer 60B. The second etching process is, for example, wet etching, and the etchant used in the second etching process selectively etches the second etching stop layer 60B. A conductive material is disposed in the contact hole, and another CMP process is applied to planarize the upper surface, thereby forming the second S/D contact 54.

The IC structure 20 is described in more detail in FIG. 7 , which is a cross-sectional view of the IC structure 20 manufactured according to the present novel embodiment along the dotted line CC' of FIG. 4A . FIG. 7 is similar to FIG. 6C , but the channel structure is different. Each active region 22 includes a plurality of channels 38 stacked vertically, and the gate 30 surrounds these channels. Such a structure is also referred to as a gate all-around (GAA) structure. In some embodiments, the number of stacked channels 38 can vary, for example, from 3 to 10. In some embodiments, the number of channels 38 in the n-well 26 is different from the number of channels 38 in the p-well 28.

FIG8A and FIG8B are top views of an IC structure 10 manufactured according to an embodiment of the present invention. FIG8A and FIG8B illustrate two adjacent standard cells 14 and 16 (the standard cell 14 is also referred to as the first standard cell 14 and the standard cell 16 is also referred to as the second standard cell 16), the standard cells 14 and 16 being similar to the standard IC cells described above, such as the standard IC cell 21 in FIGS. 2A to 7. The filling cell 18 is described in more detail herein. FIG8A illustrates only one active region 22 in the n-well 26 and only one active region 22 in the p-well 28. However, it should be understood that there may be any suitable number of active regions 22 (e.g., 2 to 10), depending on the individual standard IC cells and the functions corresponding to the standard IC cells. Similarly, only one gate 30 is illustrated in each standard IC cell. However, it should be understood that there may be any suitable number of gates 30 (e.g., 1 to 10), depending on the individual standard IC cells and the functions corresponding to the standard IC cells. The gates 30 are generally distributed with a gate pitch P. If the standard IC cell includes one gate, the size of the standard IC cell along the X direction is twice the gate pitch P (2P). If the standard IC cell includes N gates, the size of the standard IC cell along the X direction is N+1 times the gate pitch P ((N+1)P). The filling cell 18 includes two dielectric gates and extends a dimension Df, the dimension Df is the gate pitch P, the dimension D1 is N ₁ times the gate pitch P (N ₁ P), and the dimension D2 is N ₂ times the gate pitch P (N ₂ P), wherein the first standard cell 14 includes N ₁ gates 30, and the second standard cell 16 includes N ₂ gates 30. In addition, the active region 22 extends continuously from the first standard cell 14 to the second standard cell 16. A plurality of FETs (e.g., p-type FETs (pFETs) 62, 64, and n-type FETs (nFETs) 66, 68) are formed in the IC structure 10.

When the second standard cell 16 is located next to the first standard cell 14 , the filling cell 18 is configured to be sandwiched between the first standard cell 14 and the second standard cell 16 . The filling cell 18 extends by a dimension Df, which is equal to a pitch dimension P.

8A , each standard cell (e.g., the first standard cell 14 and the second standard cell 16) is bounded by a dielectric gate 40. For example, the first standard cell 14 extends a first dimension D1 along the X direction, and the second standard cell 16 extends a second dimension D2 along the X direction. In the presented design, dimension D1 is greater than dimension Df and dimension D2 is greater than dimension Df.

Each standard cell includes at least one gate 30 configured to form one or more field effect transistors. In the embodiment presented, each first standard cell 14 and each second standard cell 16 includes at least one gate 30. The distance between the gate 30 and the dielectric gate 40 is equal. In other words, all gates (including the gate 30 and the dielectric gate 40) are arranged in a periodic structure with a gate pitch P. Here, the pitch is the dimension between the same positions of adjacent components, such as center to center. Therefore, the filling cell 18 extends along the Y direction by a dimension Df of one pitch (equal to the gate pitch P). The first standard cell 14 extends along the X direction by a dimension of two pitches, or a dimension D1 equal to twice the gate pitch P. Similarly, the second standard cell 16 extends along the X direction by a dimension of two pitches, or a dimension D2 equal to twice the gate pitch P.

In particular, each active region 22 has a continuous structure extending through adjacent standard cells (e.g., the first standard cell 14 and the second standard cell 16), and the filling cell 18 is interposed therebetween. According to the present disclosure, when the second standard cell is located next to the first standard cell, the second standard cell is separated by a filling cell having a pitch size (gate pitch P); and all gates 30 and dielectric gates 40 are located on the same continuous active region 22.

In the embodiment shown, the IC structure 10 includes a first active region 22 in an n-well 26 and a second active region 22 in a p-well 28. The gate 30 in the first standard cell 14 extends continuously from the first active region 22 (in the n-well 26) to the second active region 22 (in the p-well 28) along the Y direction. Similarly, the gate 30 in the second standard cell 16 extends continuously from the first active region 22 (in the n-well 26) to the second active region 22 (in the p-well 28) along the Y direction. The dielectric gate 40 located on the boundary line of the standard cell also extends continuously from the first active region 22 (in the n-well 26) to the second active region 22 (in the p-well 28) along the X direction. Each gate 30 is located next to the dielectric gate 40. Because the active regions are continuous, isolation between transistors is achieved by the dielectric gate 40.

With the S/D components 36 and channels 38 of each transistor formed, the first standard cell 14 includes a p-type FET (pFET) 62 in the n-well 26 and an n-type FET (nFET) 66 in the p-well 28, each of which is associated with a respective active region and a respective standard cell; the second standard cell 16 includes a p-type FET (pFET) 64 in the n-well 26 and an n-type FET (nFET) 68 in the p-well 28. In the illustrated embodiment, the pFET 62 and the nFET 66 in the first standard cell 14 are integrated to form a functional circuit block, such as a complimentary FET; the pFET 64 and the nFET 68 in the second standard cell 16 are integrated to form a functional circuit block, such as another complimentary FET.

Thus, adjacent standard cells are spaced apart by a pitch dimension P, which ensures circuit packing density. The active region is continuous through multiple cells, and the transistors are isolated by dielectric gates 40. The continuity of the active region maintains a conventional layout for ease of manufacturing. In some embodiments, because the transistors are always next to the dielectric gate, design uncertainty is reduced. Because of the continuous active region and the use of dielectric gate isolation, there is no abutment constraint during cell placement. In addition, the uniform local density of gate 30 and dielectric gate 40 results in better device performance and process uniformity.

When placing standard cells next to other standard cells, the provisions defined above apply. In general, multiple standard cells can therefore be placed in a cascade mode. In this case, a filler cell sandwiched between two adjacent standard cells extends a pitch dimension between the two standard cells. A first standard cell is adjacent to a filler cell on one side of the dielectric gate, and a second standard cell is adjacent to another filler cell on the other side of the dielectric gate.

In FIG. 8B , the filling unit 18 includes three dielectric gates 40 evenly distributed, and the filling unit 18 extends along the X direction by a dimension Df, the dimension Df is equal to twice the gate pitch P (2P), the dimension D1 is equal to N ₁ times the gate pitch P (N ₁ P), and the dimension D2 is equal to N ₂ times the gate pitch P (N ₂ P).

The present disclosure provides an embodiment of an IC structure having a plurality of standard cells, wherein the standard cells are configured according to predefined regulations. In a plurality of the above-described embodiments, the standard cells include S/D contacts and gate contacts formed with different components, respectively. In detail, the gate contacts are classified into three categories, each category having a different environment, and the gate contacts in different environments are designed to have different shapes and different sizes to optimize the contact area and alignment margin. The gate further improves the contact area and process window according to the environment. The S/D contacts include two layers formed separately, and include different components to optimize manufacturing capabilities and circuit performance. Multiple benefits are presented in multiple embodiments. By using the disclosed layout having a plurality of standard cells, an IC structure (e.g., a logic circuit) can have a high packaging density, improved circuit performance, and improved power-performance-area-cost (PPAC).

In some embodiments, the present disclosure relates to an integrated circuit (IC) structure. The IC structure includes: a first standard cell, the first standard cell integrating a first p-type field effect transistor (pFET) and a first n-type field effect transistor (nFET); a first gate, a second gate, and a third gate, the first gate, the second gate, and the third gate are longitudinally oriented along a first direction and are arranged in the first standard cell; a first gate contact on the first gate, the first gate contact is adjacent to two source/drain (S/D) contacts on two opposite edges of the first gate; a second gate contact on the second gate, the second gate contact is adjacent to a single source/drain contact on one edge of the second gate; and a third gate contact on the third gate, the third gate contact is not surrounded by any source/drain contacts. The first gate contact extends a first dimension along a second direction orthogonal to the first direction; the second gate contact extends a second dimension along the second direction; the third gate contact extends a third dimension along the second direction; the first dimension is smaller than the second dimension, and the second dimension is smaller than the third dimension.

In some embodiments, the first ratio of the second dimension to the first dimension is equal to the second ratio of the third dimension to the second dimension. In some embodiments, the first ratio and the second ratio are both between 1.2 and 1.5.

In some embodiments, the IC structure further includes: a second standard cell adjacent to the first standard cell, the second standard cell integrating a second p-type field effect transistor and a second n-type field effect transistor; and a first dielectric gate located between the first standard cell and the second standard cell.

In some embodiments, the IC structure further includes: a second dielectric gate located between the first standard cell and the second standard cell; and a first filling cell configured between the first standard cell and the second standard cell, and the first filling cell extends between the first dielectric gate and the second dielectric gate; wherein the first dielectric gate is located on the boundary of the first standard cell, and the second dielectric gate is located on the boundary of the second standard cell.

In some embodiments, the first filling unit further includes a third dielectric gate, and the third dielectric gate is sandwiched between the first dielectric gate and the second dielectric gate.

In some embodiments, a first p-type field effect transistor and a second p-type field effect transistor are formed on a first continuous active region; a first n-type field effect transistor and a second n-type field effect transistor are formed on a second continuous active region; the first continuous active region and the second continuous active region are longitudinally oriented along a second direction; the first dielectric gate and the second dielectric gate are longitudinally oriented along the first direction and extend from the first continuous active region to the second continuous active region.

In some embodiments, the first gate extends along the second direction by a fourth dimension; the second gate includes a first segment overlapping with the second gate contact, the first segment extends along the second direction, and the first enlarged dimension is greater than the fourth dimension.

In some embodiments, the third gate includes a second segment overlapping the third gate contact, and the second segment extends along the second direction by a second enlarged dimension; the second enlarged dimension is larger than the first enlarged dimension.

In some embodiments, the ratio of the first expansion size to the fourth size is between 1.5 and 2; the ratio of the second expansion size to the fourth size is between 2 and 3.

In some other embodiments, the present disclosure is related to an IC structure. The IC structure includes: a first standard cell, the first standard cell integrating a first p-type field effect transistor (pFET) and a first n-type field effect transistor (nFET), and having a first dielectric gate on the first standard cell boundary; a second standard cell adjacent to the first standard cell, the second standard cell integrating a second p-type field effect transistor and a second n-type field effect transistor, and having a second dielectric gate on the second standard cell boundary; and a first filling cell disposed between the first standard cell and the second standard cell, the first filling cell extending between the first dielectric gate and the second dielectric gate. The first standard cell further includes: a first gate and a second gate oriented longitudinally along a first direction and disposed in the first standard cell; a first gate contact located on the first gate, the first gate contact being adjacent to two source/drain (S/D) contacts on two opposite edges of the first gate; and a second gate contact located on the second gate, the second gate contact being adjacent to a single source/drain contact on one edge of the second gate. The first gate contact extends a first dimension along a second direction orthogonal to the first direction; the second gate contact extends a second dimension along the second direction; and the first dimension is smaller than the second dimension.

In some embodiments, the first p-type field effect transistor and the second p-type field effect transistor are formed on the first continuous active region; the first n-type field effect transistor and the second n-type field effect transistor are formed on the second continuous active region.

In some embodiments, the first continuous active region and the second continuous active region include a plurality of channels stacked vertically; and the first gate and the second gate surround the plurality of channels.

In some embodiments, the IC structure further comprises: a third gate oriented longitudinally along the first direction and disposed in the first standard cell; and a third gate contact located on the third gate, wherein the third gate contact is free of any source/drain contacts. The third gate contact extends a third dimension along the second direction, and the third dimension is greater than the second dimension.

In some embodiments, a first ratio of the second size to the first size is equal to a second ratio of the third size to the second size, and both the first ratio and the second ratio are between 1.2 and 1.5.

In some embodiments, the first gate extends a fourth dimension along the second direction; the second gate includes a first segment overlapping with the second gate contact, and the first segment extends a first enlarged dimension along the second direction; the third gate includes a second segment overlapping with the third gate contact, and the second segment extends a second enlarged dimension along the second direction; the first enlarged dimension is greater than the fourth dimension, and the second enlarged dimension is greater than the first enlarged dimension.

In some embodiments, the ratio of the first enlarged size to the fourth size is between 1.5 and 2; the ratio of the second enlarged size to the fourth size is between 2 and 3.

Other embodiments of the present disclosure are related to a method for manufacturing an integrated circuit. The method includes: forming a first active region and a second active region oriented longitudinally along a first direction on a semiconductor substrate, wherein the first active region and the second active region are separated by an isolation component; forming a first gate electrode and a second gate electrode extending longitudinally on the first active region and the second active region along a second direction, wherein the second direction is perpendicular to the first direction; forming a first source/drain contact located on the first active region and the second active region; and forming a first gate contact and a second gate contact located on the first gate electrode and the second gate electrode, respectively; the first source/drain contact is a first distance away from the first gate contact, and the first source/drain contact is a second distance away from the second gate contact, wherein the first distance is greater than the second distance. The first gate contact extends from the first gate electrode to the isolation component and extends a first width along the first direction. The second gate contact extends a second width along the first direction, wherein the second width is less than the first width.

In some embodiments, the method further includes: forming a second source/drain contact on the first source/drain contact, wherein the second source/drain contact directly covers the isolation component; forming a first etch stop layer, wherein the first etch stop layer is directly located on the side wall of the first source/drain contact and the upper surface of the isolation component; and forming a second etch stop layer, wherein the second etch stop layer is directly located on the upper surface of the first source/drain contact, the first etch stop layer, and the side wall of the second source/drain contact.

In some embodiments, the formation of a first gate contact includes forming the first gate contact at a symmetrical position so that the center of the first gate contact is aligned with the center of the first gate electrode along the first direction; the formation of a second gate contact includes forming the second gate contact at an asymmetrical position so that the center of the second gate contact deviates from the center of the second gate electrode along the first direction; the first gate electrode and the second gate electrode are located under the second etching stop layer.

The above content summarizes the features of some embodiments. Those of ordinary skill in the art should understand that they can easily use the new embodiments as a basis to design or modify other processes and structures for performing the same purpose and/or achieving the same benefits of the above-mentioned embodiments. Those of ordinary skill in the art should also understand that such equivalent structures do not depart from the spirit and scope of the new embodiments, and those of ordinary skill in the art should understand that multiple changes, substitutions, and modifications can be made here without departing from the spirit and scope of the new embodiments.

Claims (10)

1. An integrated circuit, comprising: A first standard cell integrating a first p-type field effect transistor and a first n-type field effect transistor; A first gate, a second gate, and a third gate are longitudinally oriented along a first direction, and the first gate, the second gate, and the third gate are disposed in the first standard cell; a first gate contact located on the first gate and adjacent to the two source/drain contacts on two opposite edges of the first gate; a second gate contact located on the second gate and adjacent to the single source/drain contact on an edge of the second gate; and a third gate contact, located on the third gate and without any source/drain contacts around it; Wherein, the first gate contact extends a first dimension along a second direction orthogonal to the first direction; The second gate contact extends along the second direction by a second dimension; The third gate contact extends along the second direction by a third dimension; and The first size is smaller than the second size, and the second size is smaller than the third size. 2. The integrated circuit as claimed in claim 1, characterized in that a first ratio of the second size to the first size is equal to a second ratio of the third size to the second size, and the first ratio and the second ratio are both between 1.2 and 1.5. 3. The integrated circuit of claim 1, further comprising: a second standard cell adjacent to the first standard cell, wherein the second standard cell integrates a second p-type field effect transistor and a second n-type field effect transistor; a first dielectric gate located between the first standard cell and the second standard cell; a second dielectric gate located between the first standard cell and the second standard cell; and a first filling unit, disposed between the first standard unit and the second standard unit, and extending between the first dielectric gate and the second dielectric gate; The first dielectric gate is located on the boundary of the first standard cell, and the second dielectric gate is located on the boundary of the second standard cell. 4 . The integrated circuit as claimed in claim 3 , wherein the first filling unit further comprises a third dielectric gate, and the third dielectric gate is sandwiched between the first dielectric gate and the second dielectric gate. 5. The integrated circuit according to claim 3, wherein: The first p-type field effect transistor and the second p-type field effect transistor are formed on a first continuous active region; The first n-type field effect transistor and the second n-type field effect transistor are formed on a second continuous active region; The first continuous active region and the second continuous active region are longitudinally oriented along the second direction; and The first dielectric gate and the second dielectric gate are longitudinally oriented along the first direction and extend from the first continuous active region to the second continuous active region; in: The first gate extends along the second direction by a fourth dimension; The second grid includes a first segment overlapping the second grid contact, and the first segment extends along the second direction by a first enlarged dimension; The first enlarged size is larger than the fourth size; The third grid includes a second segment overlapping the third grid contact, and the second segment extends along the second direction by a second enlarged dimension; The second amplification size is larger than the first amplification size; The ratio of the first expansion size to the fourth size is between 1.5 and 2; and The ratio of the second enlarged size to the fourth size is between 2 and 3. 6. An integrated circuit, comprising: A first standard cell integrating a first p-type field effect transistor and a first n-type field effect transistor and having a first dielectric gate on a first standard cell boundary; a second standard cell adjacent to the first standard cell, the second standard cell integrating a second p-type field effect transistor and a second n-type field effect transistor, and having a second dielectric gate on a second standard cell boundary; and a first filling unit, disposed between the first standard unit and the second standard unit, and extending between the first dielectric gate and the second dielectric gate, wherein the first standard unit further comprises: A first gate and a second gate are longitudinally oriented along a first direction and are arranged in the first standard cell; a first gate contact located on the first gate and adjacent to the two source/drain contacts on two opposite edges of the first gate; and a second gate contact located on the second gate and adjacent to the single source/drain contact on an edge of the second gate; Wherein, the first gate contact extends a first dimension along a second direction orthogonal to the first direction; The second gate contact extends along the second direction by a second dimension; and The first size is smaller than the second size. 7. The integrated circuit of claim 6, wherein: The first p-type field effect transistor and the second p-type field effect transistor are formed on a first continuous active region; and The first n-type field effect transistor and the second n-type field effect transistor are formed on a second continuous active region. 8. The integrated circuit of claim 7, wherein: The first continuous active region and the second continuous active region both include a plurality of channels stacked vertically; and The first grid and the second grid both surround the plurality of channels. 9. The integrated circuit of claim 7, further comprising: a third gate oriented longitudinally along the first direction and disposed in the first standard cell; and A third gate contact is located on the third gate and is not surrounded by any source/drain contacts, wherein: The third gate contact extends along the second direction by a third dimension, and the third dimension is greater than the second dimension; and A first ratio of the second size to the first size is equal to a second ratio of the third size to the second size, and both the first ratio and the second ratio are between 1.2 and 1.5. 10. The integrated circuit of claim 9, wherein: The first gate extends along the second direction by a fourth dimension; The second grid includes a first segment overlapping the second grid contact, and the first segment extends along the second direction by a first enlarged dimension; The third gate includes a second segment overlapping the third gate contact, and the second segment extends along the second direction by a second enlarged dimension; and The first amplified size is larger than the fourth size, and the second amplified size is larger than the first amplified size; The ratio of the first expansion size to the fourth size is between 1.5 and 2; and The ratio of the second enlarged size to the fourth size is between 2 and 3.