CN115440573A - Single crystal SiC/Si wafer substrate, heterostructure and preparation method thereof - Google Patents

Abstract

The invention provides a single crystal SiC/Si wafer substrate, a heterostructure and a preparation method thereof. The single crystal SiC/Si wafer substrate includes: a Si substrate having a plurality of patterned cell regions formed thereon, the plurality of cell regions being spaced apart from each other by spacers, and each cell region including a single crystal SiC layer formed on the corresponding cell region. The heterostructure includes the single crystal SiC/Si and GaN layers described previously. The preparation method includes reacting the carbon-containing material layer with the Si substrate exposed in the groove by an annealing process to selectively grow a single crystal SiC layer. Similarly, the nitrogen-containing gas and gallium-containing vapor phase material are reacted on the patterned single crystal SiC/Si wafer substrate by a MOCVD epitaxial growth process to form a single crystal GaN layer. The resulting single crystal SiC and GaN structures within the cell region have high quality and low defect density.

Description

Single crystal SiC/Si wafer substrate, heterostructure and preparation method thereof

technical field

The invention relates to a heterogeneous structure and a preparation method thereof; in particular, it relates to a single-crystal SiC/Si wafer substrate, a single-crystal GaN/SiC heterostructure and a preparation method thereof.

Background technique

High power and high frequency circuits require devices based on semiconductor materials with both large breakdown voltages and high electron velocities. Unlike traditional semiconductor materials, materials with wide bandgap, such as GaN and SiC, have received special attention due to their ability to be used at higher power densities. GaN- and SiC-based devices grown on silicon (Si) substrates are expected to be among the best candidates for the next generation of systems seeking to integrate RF and digital circuits in close proximity to each other without gaps.

Due to the high thermal conductivity of SiC compared with GaN, SiC has also been widely concerned in the field of power applications. It can theoretically withstand higher power density than the existing polycrystalline SiC, and 3C-SiC can be directly grown on Si has attracted attention and also has extremely high electron mobility. Currently, numerous attempts have been made to directly grow and integrate high-quality SiC and GaN devices on Si substrates for high-quality power device applications.

The more commonly used integration technologies are hybrid integration and heteroepitaxy, where hybrid integration methods, such as wire bonding and rewind, provide short-term solutions. However, this approach has limitations in terms of interconnect loss and chip positioning/alignment issues and integration density. Furthermore, the cost of using SiC and GaN materials for power devices exhibiting excellent performance is greatly limited by the high defect density and small size of the substrate.

Heteroepitaxial integration of different semiconductors on Si substrates is a more promising approach, while the biggest problems in growing compound semiconductors (CS) directly on Si are lattice mismatch and coefficient of thermal expansion (CTE) mismatch. At present, the scheme of forming GaN and SiC on larger Si wafers seems to be reduced in cost, and the problem of lattice mismatch and high defect density on larger Si wafers becomes more serious. Alternatively, complex processes involving multiple layers such as buffer layers, superlattice layers, and barrier layers are required.

Therefore, there is a need in the art for a simplified method of growing high-quality single-crystal SiC and GaN on large-scale silicon wafers and their improved structures.

Contents of the invention

In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for preparing a single crystal SiC-Si wafer substrate, which is used to solve the problem of heterogeneous growth of SiC layers on larger Si substrates in the prior art. The problems of lattice mismatch and thermal expansion coefficient mismatch with the substrate.

In order to achieve the above purpose and other related purposes, the present invention provides a patterned single crystal SiC/Si wafer substrate, a patterned single crystal GaN/SiC/Si heterostructure wafer substrate and a preparation method thereof. The method for preparing a single crystal SiC/Si wafer substrate at least includes: providing a Si substrate; depositing an _SiO2 layer on the Si substrate, and patterning the _SiO2 layer to form in the _SiO2 layer a plurality of grooves, the grooves are defined by SiO ₂ sidewalls surrounding them, and the bottom of the grooves exposes the Si substrate; a carbonaceous material layer is formed in the grooves; the annealing process makes the reacting the carbon-containing material layer with the Si substrate exposed in the groove to selectively grow a single crystal SiC layer at the bottom of the groove; and removing the remaining carbon-containing material layer by a chemical mechanical polishing process, Multiple SiC cell regions separated by _SiO2 sidewalls are formed.

Preferably, the annealing process includes furnace annealing or rapid thermal annealing.

Preferably, the method for preparing a single crystal SiC/Si wafer substrate is characterized in that: the annealing process is a laser-based local annealing process.

Preferably, the size of the SiC unit area is less than or equal to 4 inches.

Preferably, the shape of the SiC unit area is a smooth polygon with rounded corners, an ellipse, a circle or a combination thereof.

Preferably, the thickness of the SiC unit region is from 0.1um to 10um.

Preferably, the carbonaceous material layer comprises a carbon layer formed by spin-coated polymethyl methacrylate or chemical vapor deposition.

The present invention also provides a single crystal SiC/Si wafer substrate, the wafer substrate at least includes: a Si substrate, a plurality of patterned unit regions are formed on the Si substrate, and a plurality of the unit regions are separated from each other by a spacer, and each unit region includes a single crystal SiC layer formed on the corresponding unit region.

Preferably, the spacers comprise silicon dioxide or voids.

Preferably, the single crystal SiC is 3C-SiC or 4H-SiC.

The present invention provides a SiC-based metal-oxide-semiconductor field-effect transistor, and the SiC-based metal-oxide-semiconductor field-effect transistor is formed based on the aforementioned patterned single-crystal SiC/Si wafer substrate.

The present invention provides a method for preparing a wafer substrate of a patterned single crystal GaN/SiC/Si heterostructure, the preparation method at least comprising: providing a Si substrate; depositing a _SiO2 layer on the Si substrate , and the SiO ₂ layer is patterned to form a plurality of grooves in the SiO ₂ layer, the grooves are defined by SiO ₂ sidewalls around them, and the grooves expose Si at the bottom substrate; forming a carbon-containing material layer in the groove; reacting the carbon-containing material layer with the Si substrate exposed in the groove through an annealing process to selectively grow a single layer at the bottom of the groove crystal SiC layer; the residual carbon-containing material layer is removed by a chemical mechanical polishing process to form SiC cell regions separated by _SiO2 sidewalls; GaN stacks are deposited on the patterned SiC/Si wafer substrate, and the GaN stacks include a GaN layer and an AlGaN barrier layer; and removing the GaN stack on the _SiO2 surface by a chemical mechanical polishing process.

Preferably, the GaN stack further includes a GaN buffer layer disposed between the single crystal SiC layer and the GaN layer.

Preferably, the GaN stack is deposited by performing an MOCVD epitaxial growth process, the MOCVD epitaxial growth process comprising: forming a GaN nucleation layer at a temperature of 500-800° C.; and forming a GaN epitaxial layer at a temperature of 900-1100° C. Floor. .

Preferably, the precursor for depositing the GaN stack includes NH ₃ as a nitrogen source and an organic gas phase material containing aluminum and gallium.

Preferably, the aluminum-containing organic gas-phase material is trimethylaluminum (TMAl), and the gallium-containing organic gas-phase material is trimethylgallium (TMGa).

The present invention also provides a wafer substrate of a patterned single crystal GaN/SiC/Si heterostructure, the wafer substrate at least includes: a Si substrate on which a plurality of patterned a cell region, the plurality of cell regions are separated from each other by a spacer, and each cell region includes: a single crystal SiC layer formed on the corresponding cell region; and a GaN stack including a GaN layer and an AlGaN potential Layers.

Preferably, the GaN stack further includes a GaN buffer layer disposed between the single crystal SiC layer and the GaN layer.

The present invention also provides a GaN-based high electron mobility transistor (HEMT), which is formed based on the aforementioned patterned single-crystal GaN/SiC/Si heterostructure wafer substrate.

As mentioned above, the preparation method of the single crystal SiC/Si wafer substrate of the present invention has the following beneficial effects: the single crystal SiC layer can be selectively grown on the Si substrate, and the compound semiconductor based compound semiconductor can be purposely positioned on the substrate. CMOS devices, thereby optimizing the performance of the circuit, while selective area growth can reduce the defect density at the interface, so devices based on this wafer substrate have low leakage current and optimized performance; using high-energy lasers can provide The localized heating scheme can improve the resolution of the irradiation area by controlling the spatial distribution of the laser; the localized annealing based on the laser enables the Si material to undergo melting and recrystallization in a very short period of time, rapidly Homogeneity of the material allows modification of the surface properties without changing the properties of the bulk region, reducing damage to the substrate and adjacent circuitry by confining the energy absorption region to the illuminated surface area. Through the preparation method of the patterned single-crystal SiC/Si wafer substrate, high-quality single-crystal SiC and GaN can be grown on large-scale substrates, and the obtained wafer substrate structure has high quality and low defects density, especially for the fabrication of SiC and GaN power devices.

Description of drawings

Fig. 1 is a flowchart showing the method for preparing a single crystal SiC/Si wafer substrate of the present invention.

FIG. 2 is a schematic diagram showing the structure of a patterned single crystal SiC/Si wafer substrate according to the present invention.

FIG. 3 to FIG. 6 are schematic structural diagrams showing various stages of the method for preparing a single crystal SiC/Si wafer substrate according to the present invention.

FIG. 7 is a flowchart showing a method for preparing a patterned single-crystal GaN/SiC/Si heterostructure wafer substrate of the present invention.

FIG. 8 shows a schematic structural view of a wafer substrate with a patterned single crystal GaN/SiC/Si heterostructure of the present invention.

9 shows a schematic plan view of a HEMT device prepared for a wafer substrate with a patterned single crystal GaN/SiC/Si heterostructure according to the present invention.

Component designation description

110 Si substrate

120 SiO ₂ layers

122 SiO ₂ sidewall

124 Spacers

130 grooves

140 SiC layers

142 SiC cell area

250 GaN layers

252 GaN/SiC cell area

350 GaN stack

352 GaN buffer layer

354 GaN hetero layer

356 AlGaN barrier layer

360 Grid Metal

370 Source metal

380 Drain Metal

S1～S8 steps

detailed description

Hereinafter, specific examples are used to illustrate the implementation of the present invention, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention. For the purpose of clarity, components and steps that are well known to those skilled in the art are omitted to avoid unnecessarily obscuring elements of the invention.

It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

In order to solve the problem of lattice mismatch and thermal expansion coefficient mismatch between the compound semiconductor grown on a larger Si substrate and the substrate, and the degradation of device performance caused by high defect density, the present invention provides a novel method to selectively or locally grow SiC on Si substrates. Such an approach allows the performance of circuits to be optimized by purposefully positioning compound semiconductor-based CMOS devices on commonly used Si substrates. Selective region growth helps reduce the density of misfit dislocations in lattice-mismatched systems by reducing dislocation interactions and propagation. Due to the limitation of the area of the growth region to a few mm ² , the quality of the heterogeneously grown compound semiconductor can be better optimized.

Herein, the term "large-sized substrate" means a wafer whose size exceeds 4 inches in terms of wafer diameter; thus, the method for preparing a single crystal SiC/Si wafer substrate according to the present invention can be applied to Inch larger wafers, such as greater than or equal to 6-inch wafers, for example, 8-inch wafers.

Conventionally, the step of carbonizing and growing SiC on the Si substrate is performed, and the carbon source pre-deposited on the Si may be pre-deposited by a conventional annealing process in the art, and the annealing process will cause carbon to diffuse into the Si. Examples of conventional annealing processes in the art include furnace annealing, rapid thermal annealing (RTA), where in the RTA process only the SiC layer needs to be performed at a relatively lower temperature due to enhanced SiC crystallization at high heating rates. The growth is, for example, performed at a temperature of 1000-1400°C. Preferably, a high power laser beam can be used to locally anneal the pre-deposited carbon source on the Si. Laser irradiation has very high energy, which can decompose the carbon source and melt the silicon at the same time, thereby initiating the growth of SiC. Laser-based processes can provide localized heating; specifically, the laser beam is focused by optical elements to control the spatial distribution of the laser light, which can localize the irradiation energy and improve the spatial resolution of the laser light. Furthermore, laser-based localized annealing can achieve SiC growth on larger substrates under ambient conditions (atmospheric pressure and room temperature conditions), compared with conventional furnace annealing and RTA processes, making Si substrates The irradiated area is able to undergo melting and recrystallization in an extremely short period of time.

On the other hand, the present invention also provides a method for growing a crack-free AlGaN/GaN heterostructure on a single crystal SiC/Si wafer substrate, by metal-organic chemical vapor deposition (MOCVD) technology on the single crystal SiC layer Epitaxial growth of the AlGaN/GaN heterostructure, as opposed to SiC growth on the entire substrate, grows SiC layers on selective regions of the Si substrate, by tuning the accumulation of lattice mismatch and thermal expansion mismatch, which can The performance of the device is effectively improved; accordingly, a high-quality GaN/SiC heterostructure can be formed on a patterned single-crystal SiC/Si wafer substrate. This AlGaN/GaN heterostructure can be used to fabricate high-performance power devices, such as high electron mobility transistors (HEMTs).

As shown in Figure 1 and Figures 3-6, the present invention provides a method for selectively forming a single crystal SiC layer on a Si substrate, the method for selectively forming a single crystal SiC layer includes the following steps:

S1: A Si substrate is provided.

S2: Deposit a _SiO2 layer on the Si substrate.

S3: patterning the SiO ₂ layer to form a plurality of grooves in the SiO ₂ layer.

S4: Forming a carbonaceous material layer in the groove.

S5: forming a SiC layer in the groove through an annealing process.

S6: planarization and cleaning.

The preparation method of the single crystal SiC/Si wafer substrate of the present invention uses photolithography to pattern the _SiO2 layer to form a plurality of grooves separated by _SiO2 sidewalls, and the bottom of the grooves exposes the Si substrate material , the Si substrate has a surface with a (111) crystal orientation, and a single crystal SiC layer is grown on a Si substrate with a crystal orientation of (111), and a single crystal SiC layer is selectively grown on this Si substrate, which can reduce the crystal lattice The density of misfit dislocations in the mismatched system makes it possible to reduce the defect density of single-crystal SiC/Si heterostructures. Furthermore, by adjusting the process parameters of the annealing operation, the geometry and thickness of the SiC cell region can be determined, thus enabling the optimization of the circuit performance according to the positioning of the device. In one embodiment, localized annealing can be used, such as laser thermal annealing with very high energy to decompose the solid carbon source, and the irradiated area of the Si substrate will undergo melting and recrystallization in a very short period of time, Relative to conventional annealing processes, material homogeneity can be achieved faster in selective regions, and localized annealing at ambient conditions can alleviate the accumulation of thermal mismatch at junctions.

The method for preparing the patterned single-crystal SiC/Si wafer substrate will be described in detail below in conjunction with the method flow chart of FIG. 1 and the structural diagrams of each stage.

Specifically, at step S1 , as shown in FIG. 3 , a Si substrate 110 is provided, and the Si substrate 110 has a (111) crystal plane orientation.

As shown in FIG. 4, at step S2, a SiO2 layer 120 is deposited on the surface of the Si substrate 110, and the deposited _SiO2 layer ₁₂₀ may have a thickness greater than 0.1 μm, for example, a thickness from 0.1 μm to 5 μm . Examples of processes used to prepare _SiO2 layers may include chemical vapor deposition (LPCVD), ultra-high vacuum chemical vapor deposition (UHCVD), plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDPCVD).

Next, referring to FIG. 5, a patterning step is performed at step S3, a photomask is applied on the SiO layer ₁₂₀ and it is etched to form a plurality of grooves 130, the bottom of which exposes Si substrate material, thus obtaining a patterned Si substrate.

Subsequently, at step S4 , a carbon source is introduced into the patterned Si substrate 110 to form a carbon-containing material layer in the groove 130 . In an example, examples of carbon sources according to this embodiment may include polymethyl methacrylate (PMMA), C60, CVD carbon layers, or similar carbonaceous materials, wherein PMMA may be applied to the on the patterned Si substrate 110 .

Next, referring to FIG. 5, an annealing process is performed, and the carbon-containing material layer can be annealed, so that the carbon-containing material layer contacts the Si substrate material at the bottom of the groove 130 and grows a SiC layer 140, without SiC growing on the SiO ₂ surface (ie, the upper surface of the spacer 124). By selectively growing a single crystal SiC layer at the bottom of the groove by surrounding the groove with SiO ₂ sidewalls, the defect expansion caused by lattice mismatch and thermal expansion coefficient mismatch can be reduced, which helps to reduce misfit dislocations, Thereby reducing the defects at the interface between single crystal SiC and Si. Examples of the annealing process employed according to this embodiment may include furnace annealing and rapid thermal annealing. In one embodiment, the recess 130 may be localized annealed, for example using a laser-based technique to apply a shaped high-energy laser beam to the recess 130 region of the Si substrate 110 to locally anneal the Si substrate 110 a pre-deposited layer of carbonaceous material. Due to the localized annealing of semiconductors with high-energy lasers, the absorbed laser energy is directly converted into heat. Through this pyrolysis, high-energy lasers with a threshold value higher than the melting of materials can cause higher thermal energy in the solid phase. Solubility, which can bring the material to homogeneity faster. The laser source may be a KrF excimer laser (λ=248nm). The shorter wavelength laser locally irradiates the carbon-containing material layer, which can realize local modification of the surface properties without changing the properties of the bulk region. Laser scan the entire substrate at a certain rate to form a single crystal SiC layer 140 in the groove 130 of the Si substrate 110, depending on the application of the SiC/Si wafer substrate, the SiC cell region 142 can have a thickness from 0.1 μm to 10 μm . In this embodiment, the thickness of the SiC unit area can be determined by controlling the laser energy and scanning rate; that is, a thicker SiC layer can be obtained by appropriately increasing the annealing time.

Subsequently, the residual carbon-containing material layer on the upper surface of the spacer region 124 can be removed, for example, the annealed substrate surface can be treated by chemical mechanical polishing (CMP) to remove the residual carbon layer, and a planarized SiC surface, as shown in Figure 6.

As a second embodiment, the present invention provides a method for preparing a patterned GaN/SiC heterostructure wafer substrate, the method for preparing a patterned GaN/SiC heterostructure includes the following steps:

S1: A Si substrate is provided.

S2: Deposit a _SiO2 layer on the Si substrate.

S3: patterning the SiO ₂ layer to form a plurality of grooves in the SiO ₂ layer.

S4: Forming a carbonaceous material layer in the groove.

S5: forming a SiC layer in the groove through an annealing process.

S6: planarization and cleaning.

S7: Depositing a GaN layer on the patterned SiC/Si wafer substrate.

S8: planarization and cleaning.

Referring to steps S1 to S6 in the first embodiment, a patterned SiC/Si wafer substrate may be formed. In step S7 after step S6, a GaN layer may be formed on the entire patterned Si substrate 110 by metal organic chemical vapor deposition (MOCVD). The patterned SiC/Si wafer substrate includes a plurality of SiC cell regions 142 and SiO ₂ sidewalls 122 for separating the SiC cell regions. In this embodiment, the MOCVD epitaxial growth process may be a two-step process, including; firstly, forming a GaN nucleation layer at a low temperature of 500-800°C to effectively improve the crystal quality of the GaN thin film grown at a subsequent high temperature, and then Raise the temperature to 900-1100° C. to form a high-quality GaN layer on the GaN nucleation layer. The GaN layer 250 may include a GaN stack including a thick GaN layer and an AlGaN barrier layer. In one embodiment, the precursor for depositing the GaN layer may include a nitrogen source and an organic gas-phase material containing aluminum and gallium, for example, the nitrogen source is NH ₃ , and the organic gas-phase material containing aluminum is Trimethylaluminum (TMAl), and the organic gas-phase material containing gallium is trimethylgallium (TMGa). In an embodiment, the GaN layer may further include a GaN buffer layer disposed between the single crystal SiC layer 140 and the GaN layer 250 to adjust the stress balance in the epitaxial film.

Referring to FIG. 7, at step S8, a step of selectively removing the GaN layer deposited on the surface of the polycrystalline SiO ₂ is performed, leaving the GaN layer 250 covering the single crystal SiC layer 140, thereby forming a polycrystalline SiC layer 250 on the Si substrate. a GaN/SiC cell region 252 . For example, the GaN layer 250 deposited on the polycrystalline SiO ₂ may be removed using a chemical mechanical polishing (CMP) process.

The invention also provides a patterned single crystal SiC/Si wafer substrate. Please refer to FIG. 2, which is a schematic structural view of a patterned single-crystal SiC/Si wafer substrate according to the present invention, and FIG. 6 can be a patterned single-crystal SiC/Si wafer substrate along the Partial view of section A-A'. The wafer substrate of the single crystal SiC/Si has a Si substrate 110 with a crystal orientation of (111), and a plurality of patterned unit regions 142 are formed on the Si substrate 110, and the plurality of unit regions are formed by each other. The spacer regions 124 are spaced apart, and each cell region 142 includes a single crystal SiC layer formed on the corresponding cell region. The SiC cell region may have a smooth rounded polygon, ellipse, circle or similar shape for reducing defect growth at region edges. Depending on the application of the device, the size of the cell area may be the same and not exceed the size of currently available SiC substrates, for example, not exceeding 4 inches. The smaller the size of the SiC cell region, the less stress and fewer defects exist in the grown SiC layer. In some embodiments, the single crystal SiC may be any one of 3C-SiC or 4H-SiC.

On the other hand, the present invention also provides a wafer substrate of a patterned GaN/SiC/Si heterostructure, the wafer substrate of the patterned GaN/SiC/Si heterostructure can include the aforementioned A patterned single-crystal SiC/Si wafer substrate, and each cell region may include a GaN stack, and the GaN stack may include a GaN layer and an AlGaN barrier layer. In one embodiment, the GaN stack further includes a GaN buffer layer disposed between the SiC layer and the GaN layer.

In addition, the single crystal SiC/Si wafer substrate can be used to manufacture improved SiC-based metal oxide semiconductor field effect transistor (MOSFET) devices, and the preparation of the patterned single crystal SiC/Si wafer substrate of the present invention The method provides a plurality of SiC unit regions selectively grown on a large-size substrate, and the SiC unit regions are heterogeneously grown on a large-size Si substrate, based on such a high-quality SiC/Si wafer substrate The prepared SiC type power devices, such as MOSFET devices, can realize device performance optimization and high yield.

The wafer substrate of the single crystal GaN/SiC/Si heterostructure can be used to manufacture an improved GaN high electron mobility transistor (HEMT) device, and the patterned single crystal GaN/SiC/Si heterostructure of the present invention The fabrication method of the wafer substrate provides a high-quality, crack-free AlGaN/GaN heterostructure epitaxially grown on the SiC cell region 142 with lattice mismatch and thermal expansion mismatch GaN-type power devices, especially HEMT devices, prepared based on this high-quality AlGaN/GaN heterostructure can achieve device performance optimization, high yield and cost-effectiveness. As shown in Figure 9, a side cross-sectional view of the HEMT structure based on the single crystal GaN/SiC heterostructure, the HEMT device based on the AlGaN/GaN heterostructure may include: a substrate, a SiC layer, a GaN stack 350, gate metal 360, source metal 370, and drain metal 380, wherein the GaN stack 350 includes a GaN buffer layer 352, a GaN heterogeneous layer 354 and an AlGaN barrier layer 356, and the gate metal 360 is located in the Between the source metal 370 and the drain metal 380, the source metal 370 and the drain metal 380 are in ohmic contact with the AlGaN barrier layer 356, and the gate metal 360 is in ohmic contact with the AlGaN barrier layer 356. Schottky contact, the gate metal 360 is used to control the density of the two-dimensional electron gas formed by the GaN heterogeneous layer 354 and the AlGaN barrier layer 356 .

In summary, the method for preparing a single crystal SiC/Si wafer substrate of the present invention at least includes: providing a Si substrate; depositing an _SiO2 layer on the Si substrate, and patterning the _SiO2 layer to A plurality of grooves are formed in the _SiO2 layer, the grooves are defined by _SiO2 sidewalls surrounding them, and the bottoms of the grooves expose the Si substrate; material layer; reacting the carbon-containing material layer with the Si substrate exposed in the groove through an annealing process to selectively grow a single crystal SiC layer at the bottom of the groove; and through a chemical mechanical polishing process The residual carbonaceous material layer is removed to form multiple SiC cell regions separated by _SiO2 sidewalls. The preparation method provided by the present invention can grow high-quality single crystal SiC and GaN on a large-size substrate, and the obtained wafer base structure has high quality and low defect density, so that a large-size Si wafer base can be used respectively Manufacture power devices based on SiC or GaN and improve yield. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (19)

1. A preparation method for a single crystal SiC/Si wafer substrate, characterized in that the preparation method at least comprises: Provide Si substrate; Depositing a _SiO2 layer on the Si substrate, and patterning the _SiO2 layer to form a plurality of grooves in the _SiO2 layer, the grooves being defined by _SiO2 sidewalls around their perimeter , and the bottom of the groove exposes the Si substrate; forming a layer of carbonaceous material in the groove; reacting the carbon-containing material layer with the Si substrate exposed in the groove through an annealing process to selectively grow a single crystal SiC layer at the bottom of the groove; and The residual carbonaceous material layer is removed by a chemical mechanical polishing process, forming multiple SiC cell regions separated by _SiO2 sidewalls. 2. The method for preparing a single crystal SiC/Si wafer substrate according to claim 1, wherein the annealing process comprises furnace annealing or rapid thermal annealing. 3 . The method for preparing a single crystal SiC/Si wafer substrate according to claim 1 , wherein the annealing process is a laser-based local annealing process. 4 . 4. The method for preparing a single crystal SiC/Si wafer substrate according to claim 1, characterized in that: the size of the SiC unit area is less than or equal to 4 inches. 5 . The method for preparing a single crystal SiC/Si wafer substrate according to claim 1 , wherein the shape of the SiC unit region is a smooth rounded polygon, ellipse, circle or a combination thereof. 6 . 6 . The method for preparing a single crystal SiC/Si wafer substrate according to claim 1 , wherein the thickness of the SiC unit area is from 0.1 um to 10 um. 7. The method for preparing a single crystal SiC/Si wafer substrate according to claim 1, characterized in that: said carbonaceous material layer comprises polymethyl methacrylate by spin coating or formed by chemical vapor deposition carbon layer. 8. A patterned single crystal SiC/Si wafer substrate, characterized in that the wafer substrate at least includes: Si substrate on which a plurality of unit regions are patterned, the plurality of unit regions are separated from each other by spacers, and each unit region includes a single crystal SiC formed on the corresponding unit region Floor. 9 . The patterned single-crystal SiC/Si wafer substrate according to claim 8 , wherein the spacer comprises silicon dioxide or voids. 10. The patterned single crystal SiC/Si wafer substrate according to claim 8, characterized in that: the single crystal SiC is 3C-SiC or 4H-SiC. 11. A SiC-based metal-oxide-semiconductor field-effect transistor, characterized in that the SiC-based transistor formed based on the patterned single-crystal SiC/Si wafer substrate according to any one of claims 8-10 metal oxide semiconductor field effect transistor. 12. A method for preparing a wafer substrate of a patterned single crystal GaN/SiC/Si heterostructure, characterized in that the method at least comprises: Provide Si substrate; Depositing a _SiO2 layer on the Si substrate, and patterning the _SiO2 layer to form a plurality of grooves in the _SiO2 layer, the grooves being defined by _SiO2 sidewalls around their perimeter , and the groove exposes the Si substrate at the bottom; Forming a carbon-containing material layer in the groove; reacting the carbon-containing material layer with the Si substrate exposed in the groove through an annealing process to selectively grow a single crystal SiC layer at the bottom of the groove ; Removing the residual carbonaceous material layer by a chemical mechanical polishing process to form SiC cell regions separated by _SiO2 sidewalls; continuing to deposit a GaN stack comprising a GaN layer and an AlGaN barrier layer on the patterned SiC/Si wafer substrate; and The GaN stack on the _SiO2 surface was removed by a chemical mechanical polishing process. 13. The method for preparing a wafer substrate with a patterned single crystal GaN/SiC/Si heterostructure according to claim 12, characterized in that: the GaN stack further comprises a layer disposed between the single crystal SiC layer and GaN GaN buffer layer between layers. 14. The method for preparing a patterned single-crystal GaN/SiC/Si heterostructure wafer substrate according to claim 12, characterized in that: the GaN stack is deposited by performing an MOCVD epitaxial growth process, and the MOCVD epitaxy The growth process includes: forming a GaN nucleation layer at a temperature of 500-800°C; and forming a GaN epitaxial layer at a temperature of 900-1100°C. 15. The method for preparing a patterned single-crystal GaN/SiC/Si heterostructure wafer substrate according to claim 12, characterized in that: the precursor for depositing the GaN stack includes NH as a nitrogen source ₃ and organic gas phase materials containing aluminum and gallium. 16. The method for preparing a patterned single-crystal GaN/SiC/Si heterostructure wafer substrate according to claim 15, characterized in that: the aluminum-containing organic gas phase material is trimethylaluminum (TMAl), The gallium-containing organic gas-phase material is trimethylgallium (TMGa). 17. A wafer substrate of a patterned single crystal GaN/SiC/Si heterostructure, characterized in that the wafer substrate at least includes: A Si substrate on which a plurality of patterned unit regions are formed, the plurality of unit regions are separated from each other by a spacer, and each unit region includes: a single crystal SiC layer formed on the corresponding cell area; and GaN stack, the GaN stack includes a GaN layer and an AlGaN barrier layer. 18. The wafer substrate of the patterned single crystal GaN/SiC/Si heterostructure according to claim 17, characterized in that: the GaN stack further comprises a layer disposed between the single crystal SiC layer and the GaN layer GaN buffer layer. 19. A GaN-based high electron mobility transistor, characterized in that, the wafer substrate formed based on the patterned single crystal GaN/SiC/Si heterostructure as claimed in any one of claims 17-18 GaN-based high electron mobility transistors.

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