CN115440295B - Device and method for testing data loading capacity of eMMC chip - Google Patents
Device and method for testing data loading capacity of eMMC chip Download PDFInfo
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- CN115440295B CN115440295B CN202211395635.7A CN202211395635A CN115440295B CN 115440295 B CN115440295 B CN 115440295B CN 202211395635 A CN202211395635 A CN 202211395635A CN 115440295 B CN115440295 B CN 115440295B
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Abstract
The invention provides a device and a method for testing data loading capacity of an eMMC chip, and belongs to the field of eMMC chip testing. The device comprises: the input current setting module is used for setting the input currents of the data IO interfaces of the eMMC chip to be rated currents; the judging module is used for judging whether the data loading capacity of the data IO interface exceeds a nominal value or not on the basis of the rated current and outputting a corresponding judging signal; and the gear adjusting module is used for controlling the eMMC chip to down-regulate the data loading gear when the judgment signal indicates that the data loading capacity exceeds a nominal value. By adopting the invention, the test and adjustment of the data loading capacity of the eMMC chip can be quickly realized during the packaging test, and the overall expected effect is improved.
Description
Technical Field
The invention relates to the field of eMMC chip testing, in particular to a device and a method for testing data loading capacity of an eMMC chip.
Background
The data loading capability of the eMMC chip directly affects the input signal identification accuracy.
The current general testing method is that a batch of sample wafers are selected, a window of a data loading gear is determined by measuring the data loading gear of the batch of sample wafers, and a window intermediate value is selected. When packaging the eMMC chip, the data loading is set to the above-described window intermediate value, and it is considered that with such setting, the data loading capability of most eMMC chips may fall within an expected range.
However, the expected effect of the method depends on the quality of the selected sample wafer, the sample wafer cannot represent all the eMMC chips, and the uniformity of the data loading capacity of the eMMC chips cannot be well guaranteed and is expected. Therefore, a new testing apparatus and a corresponding testing method are needed to improve the expected effect of data loading capability.
Disclosure of Invention
In order to solve the problems in the prior art, embodiments of the present invention provide a device and a method for testing a data loading capability of an eMMC chip, which can quickly implement testing and adjusting the data loading capability during a package test, thereby improving an overall expected effect. The technical scheme is as follows:
according to an aspect of the present invention, there is provided an apparatus for testing data loading capability of an eMMC chip, the apparatus including:
the input current setting module is used for setting the input currents of a plurality of data IO interfaces of the eMMC chip to be rated currents;
the judging module is used for judging whether the data loading capacity of the data IO interface exceeds a nominal value or not on the basis of the rated current and outputting a corresponding judging signal;
and the gear adjusting module is used for controlling the eMMC chip to lower the data loading gear when the judgment signal indicates that the data loading capacity exceeds a nominal value.
Optionally, the output current setting module includes a multi-stage current mirror circuit, and an output end of each stage current mirror circuit is connected to each data IO interface of the eMMC chip;
the current mirror circuit is used for setting the current of each stage of output end of the current mirror circuit as the rated current of the eMMC chip based on preset current and preset voltage.
Optionally, an input end of the judgment module is configured to receive an output voltage of the data IO interface;
the judging module is used for:
when the output voltage is smaller than the reference voltage, outputting a first judgment signal, wherein the first judgment signal is used for indicating that the data loading capacity exceeds a nominal value;
and when the output voltage is not less than the reference voltage, outputting a second judgment signal, wherein the second judgment signal is used for indicating that the data loading capacity reaches a nominal value.
Optionally, the gear adjustment module is configured to output a gear adjustment signal when the determination module outputs the first determination signal, where the gear adjustment signal is used to down-regulate the data loading gear of the eMMC chip.
Optionally, the apparatus further comprises a switching module;
the switching module is configured to:
when the judging module outputs the first judging signal, the data IO interface is switched to a communication channel from a test circuit, so that the eMMC chip receives the gear adjusting signal;
and after the data loading gear of the eMMC chip is adjusted downwards, the data IO interface is switched back to the test circuit.
According to another aspect of the present invention, there is provided a method of testing data loading capability of an eMMC chip, the method including:
setting the input currents of a plurality of data IO interfaces of the eMMC chip as rated currents;
on the basis of the rated current, judging whether the data loading capacity of the data IO interface exceeds a nominal value;
and when the data loading capacity of the data IO interface exceeds a nominal value, controlling the eMMC chip to down-regulate the data loading gear until the data loading capacity of the data IO interface reaches the nominal value or the data loading gear reaches the lowest gear.
Optionally, the determining whether the data loading capability of the data IO interface exceeds a nominal value includes:
judging whether the output voltage of the data IO interface is smaller than a reference voltage or not;
when the output voltage is smaller than the reference voltage, outputting a first judgment signal, wherein the first judgment signal is used for indicating that the data loading capacity exceeds a nominal value;
and when the output voltage is not less than the reference voltage, outputting a second judgment signal, wherein the second judgment signal is used for indicating that the data loading capacity reaches a nominal value.
Optionally, the method further includes:
when the data loading capacity of the data IO interface exceeds a nominal value, switching the data IO interface from a test circuit to a communication channel so that the eMMC chip receives a gear adjusting signal;
and switching the data IO interface back to the test circuit after the data loading gear of the eMMC chip is adjusted downwards.
According to another aspect of the present invention, there is provided an electronic apparatus including:
a device for testing the data loading capability of the eMMC chip;
a processor; and
a memory for storing the program, wherein the program is stored in the memory,
the program comprises instructions, and when the instructions are executed by the processor, the processor is enabled to execute the method for testing the data loading capacity of the eMMC chip.
According to another aspect of the present invention, there is provided a non-transitory computer readable storage medium storing computer instructions for causing a computer to execute the method for testing the data load capability of the eMMC chip described above.
In the invention, the data loading capacity of the data IO interface is measured through the input current setting module and the judgment module, and whether the data loading capacity of the data IO interface exceeds a nominal value is judged; and if the data loading capacity exceeds the nominal value, the data loading gear is adjusted downwards through the gear adjusting module. In the testing device of the eMMC chip, a measuring circuit and a feedback adjusting mechanism are adopted, so that the shipment yield of the eMMC chip is improved.
Drawings
Further details, features and advantages of the invention are disclosed in the following description of exemplary embodiments with reference to the accompanying drawings, in which:
fig. 1 is a schematic diagram illustrating a device for testing data loading capability of an eMMC chip according to an exemplary embodiment of the invention;
FIG. 2 illustrates a schematic diagram of a current mirror circuit provided in accordance with an exemplary embodiment of the present invention;
fig. 3 illustrates a flow diagram of a method for testing data loading capabilities of an eMMC chip provided in accordance with an exemplary embodiment of the invention;
FIG. 4 illustrates a block diagram of an exemplary electronic device that can be used to implement an embodiment of the invention.
Detailed Description
Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present invention. It should be understood that the drawings and the embodiments of the invention are for illustration purposes only and are not intended to limit the scope of the invention.
It should be understood that the various steps recited in method embodiments of the present invention may be performed in a different order, and/or performed in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the invention is not limited in this respect.
The term "including" and variations thereof as used herein is intended to be open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description. It should be noted that the terms "first", "second", and the like in the present invention are only used for distinguishing different devices, modules or units, and are not used for limiting the order or interdependence relationship of the functions performed by the devices, modules or units.
It is noted that references to "a", "an", and "the" modifications in the present invention are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that reference to "one or more" unless the context clearly dictates otherwise.
The names of messages or information exchanged between devices in the embodiments of the present invention are for illustrative purposes only, and are not intended to limit the scope of the messages or information.
The embodiment of the invention provides a device for testing the data loading capacity of an eMMC chip, which can be arranged on a test board card (load board) of the eMMC chip.
Referring to fig. 1, the testing device includes an input current setting module, a determination module, and a gear adjustment module.
The input current setting module is used for setting the input currents of a plurality of data IO interfaces of the eMMC chip as rated currents;
the judging module is used for judging whether the data loading capacity of the data IO interface exceeds a nominal value or not on the basis of the rated current and outputting a corresponding judging signal;
and the gear adjusting module is used for controlling the eMMC chip to lower the data loading gear when the judgment signal indicates that the data loading capacity exceeds a nominal value.
In one possible embodiment, since the input power of the eMMC data IO interface is constant, when the data loading capability of the data IO interface reaches a nominal value, if the input rated current is fixed, the output voltage may be stabilized at the rated voltage (e.g., 1.8V). Therefore, the input current of the data IO interface of the eMMC chip may be set to be a rated current by the input current setting module, and the output voltage of the data IO interface is measured by the determining module, so as to determine whether the data loading capability of the data IO interface exceeds a nominal value.
The data loading gear of the eMMC chip is adjustable, the higher the data loading gear is, the stronger the data loading capacity of the eMMC chip is, and the preset value is usually located in the middle gear. When the data loading capacity of the data IO interface exceeds a nominal value, the situation that the output voltage is reduced occurs, at this time, the gear adjusting module can be adopted to control the eMMC chip to lower the data loading gear, and the data loading capacity of the eMMC chip is reduced.
Optionally, the output current setting module includes a multi-stage current mirror circuit, and an output end of each stage current mirror circuit is connected to each data IO interface of the eMMC chip.
And the current mirror circuit is used for setting the current of each stage of output end of the current mirror circuit as the rated current of the eMMC chip based on the preset current and the preset voltage.
In one possible embodiment, as shown in the current mirror circuit in fig. 2, VDD is a constant voltage source (i.e., a preset voltage), iref is a preset reference current (i.e., a preset current) on the test board, and the reference current is a fixed standard current and may be preset as a rated current of the eMMC chip. I0 is used for adjusting the grid voltage of M2M 4M 7, so that each MOS tube works in a proper state. Wherein, I1, I2, \8230: \ I (n-2)/2 are currents at the output terminals of the respective stages of the current mirror circuit, and are respectively input to each data IO interface, and not shown in the figure. As can be derived from the current mirror circuit philosophy, the current at the output of each stage can be equal to Iref.
Optionally, the input end of the determining module may be configured to receive an output voltage of the data IO interface. The determination module may be configured to:
when the output voltage is smaller than the reference voltage, outputting a first judgment signal, wherein the first judgment signal is used for indicating that the data loading capacity exceeds a nominal value;
and when the output voltage is not less than the reference voltage, outputting a second judgment signal, wherein the second judgment signal is used for indicating that the data loading capacity reaches a nominal value.
In a possible implementation manner, the determining module may employ a comparator circuit, and two input terminals of the comparator circuit may respectively receive the output voltage of the data IO interface and a reference voltage (e.g., 1.6V). When the output voltage (e.g., 1V) is smaller than the reference voltage, it is determined that the deviation range is exceeded, and the comparator circuit may output a low level as the first determination signal. When the output voltage (e.g., 1.8V) is not less than the reference voltage, the deviation is deemed to be within the range, and the comparator circuit may output a high level as a second determination signal to determine that the eMMC chip passes the test.
Optionally, the gear adjustment module may be configured to: when the judging module outputs the first judging signal, a gear adjusting signal is output, and the gear adjusting signal is used for adjusting the data loading gear of the eMMC chip.
In a possible implementation manner, an MCU (micro controller Unit) may be used to detect an output result of the comparator, and transmit the result to a control chip of the test board through an I2C to generate a gear adjustment signal, where the MCU, the control chip of the test board, and related circuits form the gear adjustment module. Or, the gear position adjusting signal can be transmitted to the computer end through the control chip, and the computer end generates the corresponding gear position adjusting signal.
Optionally, the testing apparatus may further include a switching module. The switching module may be to: when the judging module outputs a first judging signal, switching the data IO interface from the testing circuit to a communication channel so that the eMMC chip receives a gear adjusting signal; and after the data loading gear of the eMMC chip is adjusted downwards, the data IO interface is switched back to the test circuit.
In a possible embodiment, the switching module may include a multiplexer circuit (MUX) for connecting the data IO interface and the communication channel, or connecting the data IO interface and the test circuit.
Under initial state, the switching module can be connected data IO interface and test circuit, after above-mentioned test process, if the first judgement signal of judgement module output, the data loading ability of eMMC chip promptly surpasss the nominal value this moment, and the switching module can be switched data IO interface to communication channel from test circuit.
Furthermore, the eMMC chip can receive the gear adjusting signal through the communication channel, the data loading gear is adjusted down by one level through the register, and the adjusted data loading gear is stored in the eMMC chip so that the adjustment can be continuously effective.
After the adjustment is completed, the switching module can switch the data IO interface back to the test circuit, repeatedly execute the test process, judge whether the data loading capacity of the data IO interface exceeds a nominal value or not, judge that the eMMC chip passes the test until the data loading capacity of the data IO interface reaches the nominal value, or judge that the data loading gear reaches the lowest gear and the data loading capacity of the data IO interface still exceeds the nominal value, and judge that the eMMC chip is abnormal.
In the invention, the data loading capacity of the data IO interface is measured through the input current setting module and the judging module, and whether the data loading capacity of the data IO interface exceeds a nominal value is judged; and if the data loading capacity exceeds the nominal value, the data loading gear is adjusted downwards through the gear adjusting module. In the testing device of the eMMC chip, a measuring circuit and a feedback adjusting mechanism are adopted, so that the shipment yield of the eMMC chip is improved.
Based on the same inventive concept, the embodiment of the invention provides a method for testing the data loading capacity of an eMMC chip.
Referring to the test method illustrated in fig. 3, the method includes the following steps 301-303.
Step 301, setting input currents of a plurality of data IO interfaces of the eMMC chip to be rated currents;
step 302, on the basis of rated current, judging whether the data loading capacity of the data IO interface exceeds a nominal value;
and step 303, when the data loading capacity of the data IO interface exceeds a nominal value, controlling the eMMC chip to lower the data loading gear.
And then, repeating the steps 301 to 303 until the data loading capacity of the data IO interface reaches a nominal value or the data loading gear reaches the lowest gear. When the data loading capacity of the data IO interface reaches a nominal value, judging that the eMMC chip passes the test; when the data loading gear reaches the lowest gear and the data loading capacity of the data IO interface still exceeds a nominal value, the eMMC chip is judged to be abnormal.
Optionally, the determining whether the data loading capability of the data IO interface exceeds a nominal value includes:
judging whether the output voltage of the data IO interface is smaller than a reference voltage or not;
when the output voltage is smaller than the reference voltage, outputting a first judgment signal, wherein the first judgment signal is used for indicating that the data loading capacity exceeds a nominal value;
and when the output voltage is not less than the reference voltage, outputting a second judgment signal, wherein the second judgment signal is used for indicating that the data loading capacity reaches a nominal value.
Optionally, the method further includes:
when the data loading capacity of the data IO interface exceeds a nominal value, switching the data IO interface from a test circuit to a communication channel so that the eMMC chip receives a gear adjusting signal;
and after the data loading gear of the eMMC chip is adjusted downwards, the data IO interface is switched back to the test circuit.
In the embodiment of the invention, on the basis of inputting the rated current to the data IO interface, whether the data loading capacity of the data IO interface reaches the nominal value is measured, and if the data loading capacity exceeds the nominal value, the data loading capacity is fed back to the eMMC chip to carry out data loading gear down regulation, so that the shipment yield of the eMMC chip is improved.
An exemplary embodiment of the present invention also provides an electronic device including: at least one processor; and a memory communicatively coupled to the at least one processor. The memory stores a computer program executable by the at least one processor, the computer program, when executed by the at least one processor, is operative to cause the electronic device to perform a method according to an embodiment of the present invention.
Exemplary embodiments of the present invention also provide a non-transitory computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor of a computer, is operable to cause the computer to perform a method according to an embodiment of the present invention.
The exemplary embodiments of the invention also provide a computer program product comprising a computer program, wherein the computer program, when being executed by a processor of a computer, is adapted to cause the computer to carry out the method according to the embodiments of the invention.
Referring to fig. 4, a block diagram of an electronic device 400 that may be a server or a client of the present invention, which is an example of a hardware device that may be applied to aspects of the present invention, will now be described. Electronic device is intended to represent various forms of digital electronic computer devices, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.
As shown in fig. 4, the electronic device 400 includes a computing unit 401 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 402 or a computer program loaded from a storage unit 408 into a Random Access Memory (RAM) 403. In the RAM 403, various programs and data required for the operation of the device 400 can also be stored. The calculation unit 401, the ROM 402, and the RAM 403 are connected to each other via a bus 404. An input/output (I/O) interface 405 is also connected to bus 404.
A number of components in the electronic device 400 are connected to the I/O interface 405, including: an input unit 406, an output unit 407, a storage unit 408, and a communication unit 409. The input unit 406 may be any type of device capable of inputting information to the electronic device 400, and the input unit 406 may receive input numeric or character information and generate key signal inputs related to user settings and/or function control of the electronic device. Output unit 407 may be any type of device capable of presenting information and may include, but is not limited to, a display, speakers, a video/audio output terminal, a vibrator, and/or a printer. Storage unit 408 may include, but is not limited to, magnetic or optical disks. The communication unit 409 allows the electronic device 400 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers, and/or chipsets, such as bluetooth devices, wiFi devices, wiMax devices, cellular communication devices, and/or the like.
Program code for implementing the methods of the present invention may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of the present invention, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, apparatus, and/or device (e.g., magnetic discs, optical disks, memory, programmable Logic Devices (PLDs)) used to provide machine instructions and/or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal used to provide machine instructions and/or data to a programmable processor.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the Internet.
The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.
Claims (10)
1. An apparatus for testing data loading capabilities of an eMMC chip, the apparatus comprising:
the input current setting module is used for setting the input currents of a plurality of data IO interfaces of the eMMC chip to be rated currents;
the judging module is used for judging whether the data loading capacity of the data IO interface exceeds a nominal value or not on the basis of the rated current and outputting a corresponding judging signal;
and the gear adjusting module is used for controlling the eMMC chip to down-regulate the data loading gear when the judgment signal indicates that the data loading capacity exceeds a nominal value.
2. The apparatus of claim 1, wherein the input current setting module comprises a multi-stage current mirror circuit, an output of each stage of current mirror circuit being connected to each data IO interface of the eMMC chip;
the current mirror circuit is used for setting the current of each stage of output end of the current mirror circuit as the rated current of the eMMC chip based on preset current and preset voltage.
3. The apparatus according to claim 1, wherein an input terminal of the determining module is configured to receive an output voltage of the data IO interface;
the judging module is used for:
when the output voltage is smaller than the reference voltage, outputting a first judgment signal, wherein the first judgment signal is used for indicating that the data loading capacity exceeds a nominal value;
and when the output voltage is not less than the reference voltage, outputting a second judgment signal, wherein the second judgment signal is used for indicating that the data loading capacity reaches a nominal value.
4. The apparatus of claim 3, wherein the gear adjustment module is configured to output a gear adjustment signal when the determination module outputs the first determination signal, the gear adjustment signal being configured to down-adjust a data-loading gear of the eMMC chip.
5. The apparatus of claim 4, further comprising a switching module;
the switching module is configured to:
when the judging module outputs the first judging signal, the data IO interface is switched to a communication channel from a test circuit, so that the eMMC chip receives the gear adjusting signal;
and switching the data IO interface back to the test circuit after the data loading gear of the eMMC chip is adjusted downwards.
6. A method for testing data loading capability of an eMMC chip is characterized by comprising the following steps:
setting the input currents of a plurality of data IO interfaces of the eMMC chip as rated currents;
on the basis of the rated current, judging whether the data loading capacity of the data IO interface exceeds a nominal value;
and when the data loading capacity of the data IO interface exceeds a nominal value, controlling the eMMC chip to lower the data loading gear until the data loading capacity of the data IO interface reaches the nominal value or the data loading gear reaches the lowest gear.
7. The method according to claim 6, wherein the determining whether the data loading capacity of the data IO interface exceeds a nominal value includes:
judging whether the output voltage of the data IO interface is smaller than a reference voltage or not;
when the output voltage is smaller than the reference voltage, outputting a first judgment signal, wherein the first judgment signal is used for indicating that the data loading capacity exceeds a nominal value;
and when the output voltage is not less than the reference voltage, outputting a second judgment signal, wherein the second judgment signal is used for indicating that the data loading capacity reaches a nominal value.
8. The method of claim 6, further comprising:
when the data loading capacity of the data IO interface exceeds a nominal value, switching the data IO interface from a test circuit to a communication channel so that the eMMC chip receives a gear adjusting signal;
and switching the data IO interface back to the test circuit after the data loading gear of the eMMC chip is adjusted downwards.
9. An electronic device, comprising:
the device of any one of claims 1-5;
a processor; and
a memory for storing the program, wherein the program is stored in the memory,
wherein the program comprises instructions which, when executed by the processor, cause the processor to carry out the method according to any one of claims 6-8.
10. A non-transitory computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method of any one of claims 6-8.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103970117A (en) * | 2013-01-30 | 2014-08-06 | 上海海尔集成电路有限公司 | MCU (microprogrammed control unit) chip detecting method and circuit |
| CN107677951A (en) * | 2017-08-29 | 2018-02-09 | 深圳市江波龙电子有限公司 | Die test devices and method |
| CN107886997A (en) * | 2017-12-15 | 2018-04-06 | 北京京存技术有限公司 | A kind of EMMC test devices and method |
| CN208477894U (en) * | 2018-06-21 | 2019-02-05 | 广州视源电子科技股份有限公司 | Current reference control circuit, backlight adjusting circuit and electronic equipment |
| CN209418157U (en) * | 2018-12-26 | 2019-09-20 | 深圳市江波龙电子股份有限公司 | It is a kind of for testing the test board and test equipment of storage card |
| CN110489362A (en) * | 2019-08-22 | 2019-11-22 | 江苏华存电子科技有限公司 | EMMC corrects import and export valid window automatic adjusting method, device, storage medium |
-
2022
- 2022-11-09 CN CN202211395635.7A patent/CN115440295B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103970117A (en) * | 2013-01-30 | 2014-08-06 | 上海海尔集成电路有限公司 | MCU (microprogrammed control unit) chip detecting method and circuit |
| CN107677951A (en) * | 2017-08-29 | 2018-02-09 | 深圳市江波龙电子有限公司 | Die test devices and method |
| CN107886997A (en) * | 2017-12-15 | 2018-04-06 | 北京京存技术有限公司 | A kind of EMMC test devices and method |
| CN208477894U (en) * | 2018-06-21 | 2019-02-05 | 广州视源电子科技股份有限公司 | Current reference control circuit, backlight adjusting circuit and electronic equipment |
| CN209418157U (en) * | 2018-12-26 | 2019-09-20 | 深圳市江波龙电子股份有限公司 | It is a kind of for testing the test board and test equipment of storage card |
| CN110489362A (en) * | 2019-08-22 | 2019-11-22 | 江苏华存电子科技有限公司 | EMMC corrects import and export valid window automatic adjusting method, device, storage medium |
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