CN115424970B - Semiconductor package alignment method and semiconductor package structure - Google Patents
Semiconductor package alignment method and semiconductor package structure Download PDFInfo
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- CN115424970B CN115424970B CN202211382296.9A CN202211382296A CN115424970B CN 115424970 B CN115424970 B CN 115424970B CN 202211382296 A CN202211382296 A CN 202211382296A CN 115424970 B CN115424970 B CN 115424970B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
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- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
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Abstract
The invention provides a semiconductor packaging alignment method and a semiconductor packaging structure, wherein the alignment method comprises the steps of providing a bearing substrate which is provided with a plurality of first packaging areas and a plurality of first chips attached in the plurality of first packaging areas, wherein each first chip is provided with a first mark, the plurality of first packaging areas comprise a first number of alignment packaging areas, each alignment packaging area is attached with a plurality of first chips and at least one second chip, the second chip is provided with a second mark, and the first mark is different from the second mark; performing first alignment according to the second marks on the second chips in each alignment packaging region to confirm the overall layout of the first chips on the bearing substrate; and carrying out second alignment according to the first marks on the first chips in the first packaging areas in sequence so as to confirm the position of each first packaging area. The invention has convenient operation and improves the alignment precision.
Description
Technical Field
The present invention relates to a semiconductor package, and more particularly, to a method for aligning a semiconductor package and a semiconductor package structure.
Background
Fan-in packaging and fan-out packaging generally involve reconfiguration of the chip. At present, most of reconstructed chips adopt a stepping exposure mode, and alignment is carried out on each packaging area, and the mode can ensure that the chip offset in each packaging area is minimum to the greatest extent. Specifically, in this exposure method, the alignment process generally includes coarse alignment and fine alignment, and the captured alignment marks are the same in both the two alignments, so that the method of capturing the alignment marks is more prone to cause problems. The reason is that, referring to fig. 1A, fig. 1A is a schematic diagram of a chip mounting effect under an ideal situation in the prior art, as shown in fig. 1A, each chip 10 is precisely mounted on a predetermined position on a carrier substrate 20. In the actual chip mounting process, the problem of overall deviation of the chip 10 mounted on the carrier substrate 20 is often caused by the problem of abrasion of the mark (mark) on the carrier substrate 20 or the accuracy of the equipment machine, and please refer to fig. 1B, where fig. 1B is a schematic diagram of the overall deviation of the chip in the prior art. Further, as shown in fig. 1A and 1B, the alignment marks 11 on each chip 10 are the same, so that the alignment marks captured during the alignment process have no specificity, which causes a problem of wrong columns and rows when the exposure equipment performs coarse alignment during the exposure process, resulting in a problem of rework or yield loss due to exposure deviation and whole row alignment.
In the prior art, in order to solve the problem, the processing method is to not attach chips to specific identification positions on the wafer bearing substrate. However, when the first layer of lithography is performed subsequently, the position where the chip is not attached does not have a special alignment point, and the alignment point needs to be manually debugged, which causes inconvenience in operation.
Disclosure of Invention
In order to overcome the defects of the prior art, a semiconductor package alignment method and a semiconductor package structure are provided.
In order to achieve the above object, the present invention provides a method for aligning a semiconductor package, comprising:
step A, providing a bearing substrate, wherein the bearing substrate is provided with a plurality of first packaging areas and a plurality of first chips attached in the plurality of first packaging areas, each first chip is provided with a first mark, the plurality of first packaging areas comprise a first number of contraposition packaging areas, each contraposition packaging area is attached with a plurality of first chips and at least one second chip, the second chip is provided with a second mark, and the first marks are different from the second marks; and
b, carrying out first alignment according to the second marks on the second chips in each alignment packaging area so as to confirm the overall layout of the first chips on the bearing substrate; and carrying out second alignment according to the first marks on the first chips in the first packaging areas in sequence so as to confirm the position of each first packaging area.
As a further improvement of an embodiment of the present invention, step a further includes attaching the first chips and the second chips to the carrier substrate according to a predetermined attachment map.
As a further improvement of the embodiment of the present invention, in step a, the first number of alignment packaging regions are respectively adjacent to different sides of the carrier substrate, the different sides are opposite sides or adjacent sides of the carrier substrate, and the first number is between 3 and 10.
As a further improvement of one embodiment of the present invention, each pair of packaging regions includes at least 2*2 chips, and the arrangement positions of the second chips in each pair of packaging regions are the same or different.
As a further improvement of an embodiment of the present invention, the first mark is one of a cross mark, a cross arrow mark, and a square mark; the second mark is another one of a cross mark, a cross arrow mark, and a square mark.
As a further improvement of an embodiment of the present invention, the second chip is a waste chip or a blank chip.
As a further improvement of an embodiment of the present invention, in each pair of package regions, the arrangement step size of the second chip is the same as that of each first chip.
As a further improvement of an embodiment of the present invention, before the step B, a molding compound layer is formed on the carrier substrate, the molding compound layer covers each of the first chips and each of the second chips, and the carrier substrate is removed; and step B, forming metal patterns on the first chips by utilizing a photoetching process to form a rewiring layer.
In addition, the present invention further provides a semiconductor package structure, which includes a carrier substrate, wherein the carrier substrate has a plurality of first package areas and a plurality of first chips attached to the plurality of first package areas, each first chip has a first mark thereon, the plurality of first package areas includes a first number of alignment package areas, each alignment package area is attached with a plurality of first chips and at least one second chip, the second chip has a second mark thereon, the first mark is different from the second mark, and the second mark on each second chip in each alignment package area is used for performing a first alignment to confirm an overall layout of the plurality of first chips on the carrier substrate; the first marks on the first chips in the first packaging areas are used for carrying out second alignment so as to confirm the position of each first packaging area.
As a further improvement of the embodiment of the invention, the first number of alignment packaging regions are respectively adjacent to different sides of the carrier substrate, the different sides are opposite sides or adjacent sides of the carrier substrate, and the first number is between 3 and 10.
As a further improvement of one embodiment of the present invention, each pair of packaging regions includes at least 2*2 chips, and the arrangement positions of the second chips in each pair of packaging regions are the same or different.
As a further improvement of an embodiment of the present invention, the first mark is one of a cross mark, a cross arrow mark, and a square mark; the second mark is another one of a cross mark, a cross arrow mark, and a square mark.
As a further improvement of an embodiment of the present invention, the second chip is a waste chip or a blank chip.
As a further improvement of an embodiment of the present invention, in each pair of package regions, the arrangement step size of the second chip is the same as that of each first chip.
Compared with the prior art, the alignment method of the semiconductor package and the semiconductor package structure are characterized in that the second chip with the special mark is pasted at the specific position on the bearing substrate, and the special mark is different from the general mark on the actual chip, so that the problem that fan-in (fan-in) package products and fan-out (fan-out) package products have whole-row and whole-column deviation in the exposure process can be effectively solved, and the alignment precision is improved. Furthermore, the second chip with the special mark is only mounted at the specific position on the bearing substrate, the overall yield of the actual chip (real die) is not influenced, and manual intervention operation in the first layer of photoetching is avoided, so that the method is simple and strong in operability, and can be effectively applied to production operation.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1A is a schematic diagram of the effect of a patch in an ideal situation in the prior art;
FIG. 1B is a diagram illustrating the overall chip offset in the prior art;
FIG. 2 is a flowchart of a method for aligning a semiconductor package according to the present invention;
FIG. 3 is a schematic diagram of a semiconductor package structure according to the present invention;
FIGS. 4A and 4B are schematic views illustrating mounting of chips on a carrier substrate according to the alignment method of the semiconductor package of the present invention;
FIG. 5 is an enlarged schematic view of one embodiment of an alignment packaging area of FIG. 3;
FIG. 6 is an enlarged view of another embodiment of the in-place package region of FIG. 3.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to embodiments and accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 2, 3 and 5, fig. 2 is a flow diagram illustrating the alignment method, fig. 3 is a schematic diagram illustrating a semiconductor package structure according to the present invention, and fig. 5 is an enlarged schematic diagram illustrating an embodiment of an alignment packaging region in fig. 3; the alignment method comprises the following steps:
step a (S100), providing a carrier substrate 100, where the carrier substrate 100 has a plurality of first package areas and a plurality of first chips 110 mounted in the plurality of first package areas, each first chip 110 has a first mark 111 thereon, the plurality of first package areas include a first number of alignment package areas B, each alignment package area B is mounted with a plurality of first chips 110 and at least one second chip 120, the second chip 120 has a second mark 121 thereon, and the first mark 111 is different from the second mark 121;
step B (S200), performing a first alignment according to the second mark 121 on each second chip 120 in each alignment packaging region B to confirm the overall layout of the first chips 110 on the carrier substrate 100; and sequentially performing second alignment according to the first marks 111 on the first chips 110 in the first packaging areas to confirm the position of each first packaging area.
In this embodiment, the carrier substrate 100 is a substrate for subsequent chip packaging, and may be one of a package carrier, a glass carrier, a blank semiconductor wafer, and the like.
Referring to fig. 3, 4A and 4B, fig. 4A and 4B are schematic views illustrating mounting of each chip on a carrier substrate in the alignment method of the semiconductor package according to the present invention. In practical operation, the step a further includes attaching the first chips 110 and the second chips 120 to the carrier substrate 100 according to a predetermined attachment map. The predetermined mounting map includes a mounting position of each first chip 110 and a mounting position of each second chip 120. As shown in fig. 4A and 4B, in the present embodiment, each first chip 110 is mounted to a predetermined position on the carrier substrate 100, and each second chip 120 is mounted to a predetermined position on the carrier substrate 100 according to the predetermined mounting map. In actual operation, each second chip 120 may be mounted first, and then each first chip 110 may be mounted; or other sequences, according to actual requirements.
In the invention, in the process of mounting the chip, the mark specialization of the individual chip in the alignment packaging area B is realized by sticking the second chip 120 with the special mark in the alignment packaging area B for the first alignment, so that the photoetching machine can grab the chip in the subsequent first alignment, the alignment precision is improved, the existing photoetching machine can be used for carrying out subsequent photoetching, the manual intervention in the first photoetching is avoided, the operation is convenient, and the cost is lower.
In practical operation, before the step B (S200), a chip plastic package is performed on the surface of the carrier substrate 100 and the surfaces of the first chips 110 and the second chips 120 to form a plastic package layer (not shown), where the plastic package layer covers the first chips 110 and the second chips 120 to form a chip package structure; then, the carrier substrate 100 is peeled off from the chip package structure to remove the carrier substrate 100. Step B (S200) further includes forming a redistribution layer (RDL) on the first chips 110 (e.g., on the lift-off surface corresponding to the chip package structure), where a metal pattern needs to be formed by using a photolithography process when forming the RDL, and the foregoing alignment method needs to be used in this process. In practice, the alignment method of the present invention can be applied to fan-in (fan-in) packages and fan-out (fan-out) packages.
Generally, the alignment process of the exposure apparatus includes coarse alignment and fine alignment, in the step B, the first alignment is coarse alignment, and the second alignment is fine alignment. The rough alignment (i.e. the first alignment) generally selects marks at several positions on the carrier substrate 100 to determine an overall layout (global map) of the first chips 110 on the carrier substrate 100; the fine alignment (i.e., the second alignment) is performed for each first package region on the carrier substrate 100 (by the first mark in each first package region), so as to more precisely position each first package region.
In the present invention, the carrier substrate 100 is divided into a plurality of first packaging regions (fields) to cover all chips, a first number of alignment packaging regions B for performing rough alignment are disposed in all the first packaging regions (fields) on the carrier substrate 100, and at least one second chip 120 having a special mark is disposed in each alignment packaging region B, since the special mark on the second chip 120 is obviously different from the general mark on the first chip 110, the pick-up of a photolithography tool is facilitated during the first alignment. During the second alignment, each first package region is aligned according to the mark on the first chip 110, so that the alignment accuracy is ensured to the maximum extent.
In the alignment method of the semiconductor package of the present invention, the second chip 120 having the special mark (i.e. the second mark 121) is mounted at the specific position on the carrier substrate 100, and the special mark is different from the general mark (i.e. the first mark 111) on the actual chip (i.e. the first chip 110), so that the problem of the whole row and column offset of fan-in (fan-in) package and fan-out (fan-out) package products during the exposure process can be effectively solved, and the alignment precision is improved. Furthermore, the present invention only mounts the second chip 120 with the special mark at the specific position on the carrier substrate 100 (generally, the second chip 120 is only mounted in the alignment packaging area B for rough alignment), which does not affect the overall yield of the actual chip (real die), and avoids the need of manual intervention operation during the first layer photolithography, so the method is simple and has strong operability, and can be effectively applied to the production operation.
In practical operation, the first number of alignment packaging regions are respectively adjacent to different sides of the carrier substrate 100, where the different sides are opposite sides or adjacent sides of the carrier substrate 100. As shown in fig. 3, the carrier substrate 100 includes a first side and a second side opposite to each other, in this embodiment, the first side is an upper side in the figure, and the second side is a lower side in the figure. In this embodiment, the first number is 4, that is, the plurality of first encapsulation areas includes 4 alignment encapsulation areas B, where two alignment encapsulation areas B are adjacent to the first side; the other two alignment packaging areas B are adjacent to the second side. In practical applications, the distribution of each alignment packaging region B is not limited thereto, for example, the first side and the second side are adjacent sides, and each alignment packaging region B is distributed on the adjacent first side and the adjacent second side, etc., depending on practical requirements.
Since the present embodiment has 4 alignment package regions B in total, each alignment package region B includes a second chip 120, and thus there are 4 second chips 120 in total. In this way, during the exposure process, the exposure apparatus selects the second marks 121 at 4 positions (i.e., the second marks 121 of the 4 second chips 120 on the 4 alignment packaging regions B) during the first alignment (i.e., rough alignment) to determine the overall layout (global map) of the first chips 110 on the carrier substrate 100.
In the alignment method for semiconductor package of the present invention, by specializing the relative marks, for example, the wafer should grab the second marks 121 in the 4 alignment package regions B during the exposure process to perform rough alignment, since the 4 second marks 121 are designed to be completely different from the first marks 111 on the plurality of first chips 110, only 4 second marks 121 are left on the entire wafer. During rough alignment in the exposure process, only the 4 second marks need to be found, so that the risk of deviation of the exposure alignment in rows and columns is avoided, the alignment precision is improved, and the inconvenience caused by manual alignment of the subsequent first-layer photoetching is avoided.
In practical applications, the first number is not limited to the above 4, and may further include 3 alignment package regions B,6 alignment package regions B, and the like, and generally, the number of the alignment package regions B may be between 3 and 10, that is, the first number is between 3 and 10. When each pair of package regions B includes a second chip 120, the number of the second chips 120 is the first number, and the mounting of the second chips 120 has a small influence on the entire carrier substrate 100 because the first number is small.
Referring to fig. 3 and 5, fig. 5 is an enlarged schematic view of an embodiment of an alignment packaging area in fig. 3. In practical applications, each pair of package regions may include 2*2 chips, as shown in fig. 5, each pair of package regions B includes 3*3 chips in the present embodiment, and specifically, each pair of package regions B includes 8 first chips 110 and 1 second chip 120. In practice, the method is not limited to this.
Referring to fig. 3 and 5, the arrangement positions of the second chips 120 in each pair of package regions B are the same. In this embodiment, each of the second chips 120 is the first chip at the upper left corner of the corresponding alignment packaging region B (i.e. located in the first row and the first column of the corresponding alignment packaging region B), and in actual operation, the arrangement position of the second chip 120 in each alignment packaging region B may be selected as well, please refer to fig. 6, which is a schematic diagram of another embodiment of the alignment packaging region B of the present invention, as shown in fig. 6, the second chip 120 is located in the first row and the second column of the corresponding alignment packaging region B. Further, the arrangement positions of the second chips 120 in each alignment packaging region B may also be different, for example, the second chip 120 in one alignment packaging region B is located in the first row and the first column of the alignment packaging region B, and the second chip 120 in the other alignment packaging region B is located in the first row and the second column of the alignment packaging region B, and the like, which is not limited thereto.
In this embodiment, as shown in fig. 5, the first mark 111 is a cross mark, and the second mark 121 is a square mark. In practice, the method is not limited to this. The first mark 111 may be one of a cross mark, a cross arrow mark, and a square mark; the second mark 121 is another one of a cross mark, a cross arrow mark, and a square mark. In the embodiment shown in fig. 6, the second indicia 121 is a cross-arrow indicia. Further, the second mark 121 may have other options, which is convenient for the exposure apparatus to grasp.
In this embodiment, the second chip 120 is a dummy chip (dummy die), such as a waste chip or a blank chip. In this case, the second chip 120 may be used for the first alignment (i.e. coarse alignment) without any other special purpose. Further, in the present embodiment, the size of the second chip 120 may be smaller than that of the first chip 110, and in practical operation, the size is not limited thereto. As shown in fig. 3, in each alignment packaging region B, the arrangement step size (spreading size) of the second chip 120 is the same as that of each first chip 110.
In the aligning method of the semiconductor package of the present invention, the dummy chip (dummy die) with a specific mark is mounted at a specific recognition position on the carrier substrate 100, and the mounting position of the dummy chip (dummy die) is identical to the step size of the real die (i.e., the first chip 110), so that the position does not need to be redesigned. And because the special mark is only made in the alignment packaging area for rough alignment and is only arranged on the virtual chip, the overall yield of the actual chip (real die) is not influenced.
In addition, as shown in fig. 3, the present invention further provides a semiconductor package structure, where the semiconductor package structure 200 includes a carrier substrate 100, the carrier substrate 100 has a plurality of first package areas and a plurality of first chips 110 mounted in the plurality of first package areas, each first chip 110 has a first mark 111 thereon, the plurality of first package areas includes a first number of alignment package areas B, each alignment package area B is mounted with a plurality of first chips 110 and at least one second chip 120, the second chip 120 has a second mark 121 thereon, the first mark 111 is different from the second mark 121, and the second mark 121 on each second chip 120 in each alignment package area B is used for performing a first alignment to confirm an overall layout of the plurality of first chips 110 on the carrier substrate 100; the first marks 111 on the first chips 110 in the first package regions B are used for performing a second alignment to confirm the position of each first package region.
As shown in fig. 3, the carrier substrate 100 has a first side and a second side opposite to each other, and the first number of alignment packaging regions B is respectively adjacent to the first side and the second side, wherein the first number is between 3 and 10. In another embodiment, each alignment packaging region B may also be distributed adjacent to the adjacent first side and second side.
Generally, each pair of package regions includes at least 2*2 chips, and in this embodiment, each pair of package regions B includes 3*3 chips, and specifically, each pair of package regions B includes 8 first chips 110 and 1 second chip 120. In practice, the method is not limited to this. And the arrangement position of the second chips 120 in each pair of package regions B may be the same or different.
As shown in fig. 5, in the present embodiment, the first mark 111 is a cross mark, and the second mark 121 is a square mark. In practical operation, the second mark 121 may also be a cross arrow mark or the like, which is convenient for grabbing the exposure apparatus.
As shown in fig. 5, in the present embodiment, the second chip 120 is a dummy chip (dummy die), such as a waste chip or a blank chip. In this case, the second chip 120 may be used for the first alignment (i.e., coarse alignment) without any other special purpose. Further, in the present embodiment, the size of the second chip 120 may be smaller than that of the first chip 110, and in practical operation, the size is not limited thereto. As shown in fig. 3, in each alignment packaging region B, the arrangement step size (spreading size) of the second chip 120 is the same as that of each first chip 110.
The alignment method of the semiconductor package and the semiconductor package structure of the invention are characterized in that the second chip with the special mark is pasted at the specific position on the bearing substrate, and the special mark is different from the general mark on the actual chip, thus effectively solving the problem that the fan-in (fan-in) package and fan-out (fan-out) package products have whole row and whole column offset in the exposure process and improving the alignment precision. Furthermore, the second chip with the special mark is only mounted at the specific position on the bearing substrate, the overall yield of the actual chip (real die) is not influenced, and manual intervention operation in the first layer exposure is avoided, so that the method is simple and strong in operability, and can be effectively applied to production operation.
The present invention has been described in relation to the above embodiments, which are only exemplary of the implementation of the present invention. Furthermore, the technical features mentioned in the different embodiments of the present invention described above may be combined with each other as long as they do not conflict with each other. It is to be noted that the present invention may be embodied in other specific forms, and that various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (12)
1. A method for aligning a semiconductor package, comprising:
step A, providing a carrier substrate, wherein the carrier substrate is provided with a plurality of first packaging areas and a plurality of first chips attached in the plurality of first packaging areas, each first chip is provided with a first mark, the plurality of first packaging areas comprise a first number of contraposition packaging areas, each contraposition packaging area is attached with a plurality of first chips and at least one second chip, each contraposition packaging area comprises at least 2*2 chips, the second chip is provided with a second mark, and the first mark is different from the second mark; and
b, carrying out first alignment according to the second marks on the second chips in each alignment packaging area so as to confirm the overall layout of the first chips on the bearing substrate; and sequentially carrying out second alignment according to the first marks on the first chips in the first packaging areas so as to confirm the position of each first packaging area, wherein the second chip is a waste chip or a blank chip, and the size of the second chip is smaller than that of the first chip.
2. The method of claim 1, wherein step a further comprises attaching the first chips and the second chips to the carrier substrate according to a predetermined attachment map.
3. The method of claim 1, wherein in the step a, the first number of the alignment packaging regions are respectively adjacent to different sides of the carrier substrate, the different sides are opposite sides or adjacent sides of the carrier substrate, and the first number is between 3 and 10.
4. The method of claim 1, wherein the arrangement position of the second chips in each alignment packaging region is the same or different.
5. The method of claim 1, wherein the first mark is one of a cross mark, a cross arrow mark, and a square mark; the second mark is another one of a cross mark, a cross arrow mark, and a square mark.
6. The method of claim 1, wherein the second chip is arranged in a step size same as the first chips in each alignment packaging region.
7. The method of claim 1, further comprising forming a molding compound layer on the carrier substrate before the step B, the molding compound layer covering the first chips and the second chips, and removing the carrier substrate; and step B, forming metal patterns on the first chips by utilizing a photoetching process to form a rewiring layer.
8. A semiconductor package structure, comprising,
the chip packaging structure comprises a bearing substrate, a plurality of first packaging areas and a plurality of first chips, wherein the first chips are attached in the first packaging areas, each first chip is provided with a first mark, the first packaging areas comprise a first number of contraposition packaging areas, each contraposition packaging area is attached with a plurality of first chips and at least one second chip, each contraposition packaging area comprises at least 2*2 chips, the second chips are provided with second marks, and the first marks are different from the second marks, wherein the second marks on the second chips in each contraposition packaging area are used for carrying out first contraposition so as to confirm the overall layout of the first chips on the bearing substrate; the first marks on the first chips in the first packaging areas are used for carrying out second alignment so as to confirm the position of each first packaging area, the second chip is a waste chip or a blank chip, and the size of the second chip is smaller than that of the first chip.
9. The semiconductor package structure of claim 8, wherein the first number of the plurality of alignment-packaging regions are respectively adjacent to different sides of the carrier substrate, the different sides being opposite or adjacent to the carrier substrate, wherein the first number is between 3 and 10.
10. The semiconductor package structure of claim 8, wherein the arrangement positions of the second chips in each pair of the package regions are the same or different.
11. The semiconductor package structure of claim 8, wherein the first mark is one of a cross mark, a cross arrow mark, a square mark; the second mark is another one of a cross mark, a cross arrow mark, and a square mark.
12. The semiconductor package structure of claim 8, wherein the second chip is arranged in a step size same as the first chips in each pair of package regions.
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| CN113219800B (en) * | 2021-03-25 | 2024-03-19 | 北海惠科半导体科技有限公司 | Wafer semiconductor product, manufacturing method thereof and photoetching machine |
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