CN115036251B - Alignment method of fan-out packaging wafer and fan-out packaging wafer - Google Patents
Alignment method of fan-out packaging wafer and fan-out packaging wafer Download PDFInfo
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- CN115036251B CN115036251B CN202210636457.6A CN202210636457A CN115036251B CN 115036251 B CN115036251 B CN 115036251B CN 202210636457 A CN202210636457 A CN 202210636457A CN 115036251 B CN115036251 B CN 115036251B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 99
- 238000000034 method Methods 0.000 title claims abstract description 63
- 239000000758 substrate Substances 0.000 claims description 34
- 238000000206 photolithography Methods 0.000 claims description 26
- 235000012431 wafers Nutrition 0.000 claims 18
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 9
- 238000001259 photo etching Methods 0.000 description 8
- 238000012858 packaging process Methods 0.000 description 5
- 244000045947 parasite Species 0.000 description 4
- 238000001459 lithography Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
- H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
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- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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Abstract
The invention relates to the technical field of chip packaging, in particular to a fan-out packaging wafer alignment method and a fan-out packaging wafer. According to the invention, the counterpoint chips in a plurality of counterpoint areas are sacrificed, the counterpoint chips are utilized to move to the middle positions of four adjacent first chips according to a preset movement rule, the counterpoint point positions are determined, and additional counterpoint pattern manufacturing is not needed.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a fan-out packaging wafer alignment method and a fan-out packaging wafer.
Background
With the increasing wide application of wafer fan-out package, different types of product applications and package requirements are derived, but the chip pitch in the packaging process may also vary, for example:
1. The distance change is more after the chip is rearranged: the chip spacing after the redistribution is determined by different packaging positions and sizes;
2. The range of fan-out ratios (chip area/package area) varies widely: a large fan-out ratio means an increased chip pitch;
3. compared with the original chip spacing which is the size of the wafer scribing channel, the chip spacing can be obviously amplified after the chips are rearranged.
Meanwhile, in the current advanced packaging process, the wafer fan-out package after chip redistribution also needs to be optimally routed through a redistribution layer, and a metal conductive layer needs to be formed by utilizing a photoetching process when the redistribution layer is formed.
When performing a photolithography process of a redistribution layer based on a conventional wafer level packaging process, as shown in fig. 1, the intersection points of scribe lanes 3 between four adjacent chips 1 are often used as exposure counterpoint sites 4, and the counterpoint window 2 of the exposure device is used to obtain the corresponding exposure counterpoint sites 4 for counterpoint and exposure.
When the photolithography process is performed based on the wafer fan-out package, the chip pitch is significantly enlarged after the chip is rearranged, but the alignment view field of the exposure device is fixed, the range of the search alignment mark is fixed, and an alignment window image as shown in fig. 2 or fig. 3 may appear. As shown in fig. 2, four chips 1 of four package structures are respectively located at four corners of the alignment window 2, the package structures with four chip intervals are very wide, the chip distribution after the chip mounting cannot be accurately and rapidly determined, and the alignment of the fan-out package wafer is difficult; furthermore, as shown in fig. 3, a plurality of even four chips 1 of the four package structures are located outside the range of the alignment window 2, the alignment window of the exposure device cannot see any chip, and the specific positions of the package scribe lanes 3 of the four package structures cannot be determined, that is, the chip distribution after the chip mounting cannot be determined, so that the fan-out package wafer is difficult to align.
Disclosure of Invention
The invention provides a fan-out packaging wafer and a counterpoint method thereof in order to overcome the defects of the prior art.
In order to achieve the above objective, an embodiment of the present invention further provides a method for aligning a fan-out package wafer, including:
Providing a fan-out packaging wafer substrate, wherein the fan-out packaging wafer substrate is provided with a plurality of first fan-out packaging areas and first chips attached to the first fan-out packaging areas, at least three alignment areas are selected in the fan-out packaging wafer substrate, and each alignment area at least comprises 2x2 four adjacent first chips and four adjacent first fan-out packaging areas corresponding to each first chip;
Each alignment area selects at least one first chip as an alignment point chip, a first fan-out packaging area corresponding to the alignment point chip is used as an alignment fan-out packaging area, and in a chip mounting process, the alignment point chip is moved and mounted from a preset mounting position of the alignment fan-out packaging area to the middle positions of four adjacent first chips according to a preset movement rule, so that the actual mounting position of the alignment point chip is positioned in an exposure equipment alignment window corresponding to a subsequent process;
And determining the chip patch position of the whole fan-out packaging wafer substrate according to the position of the counterpoint chip in the counterpoint window of the exposure equipment and a preset movement rule.
Optionally, each alignment area selects two diagonal first chips as alignment point chips, and the two alignment point chips are moved to the actual patch positions from the preset patch positions of the corresponding alignment fan-out packaging areas according to a preset movement rule and are patched.
Optionally, each alignment area selects a first chip as an alignment point chip, and the alignment point chip moves from a preset patch position of the corresponding alignment fan-out packaging area to an actual patch position according to a preset movement rule and patches.
Optionally, when the predetermined position of the alignment chip is located in the alignment window of the exposure device corresponding to the subsequent photolithography process, and the alignment chip moves to the middle position, the actual position of the alignment chip is still located in the alignment fan-out package area corresponding to the alignment chip.
Optionally, when the predetermined positions of the alignment point chip are all located outside the alignment window of the exposure device corresponding to the subsequent photolithography process, after the alignment point chip moves to the middle position during the alignment, the maximum moving position corresponding to the alignment point chip does not exceed the minimum width area required by the package dicing streets between four adjacent first fan-out package areas.
Optionally, the first fan-out package area has a plurality of other chips besides the first chip, and the other chips are attached to predetermined attachment positions corresponding to the other chips.
The embodiment of the invention provides a fan-out packaging wafer, which comprises the following components:
The fan-out packaging wafer substrate is provided with a plurality of first fan-out packaging areas and first chips which are adhered to the first fan-out packaging areas;
the fan-out packaging wafer substrate is internally provided with at least three alignment areas, and the alignment areas at least comprise four adjacent first chips with the size of 2x2 and four adjacent first fan-out packaging areas corresponding to each first chip;
At least one first chip of each alignment area is used as an alignment point chip, a first fan-out packaging area corresponding to the alignment point chip is used as an alignment fan-out packaging area, in a chip mounting process, the alignment point chip is moved from a preset mounting position of the alignment fan-out packaging area to the middle positions of four adjacent first chips according to a preset movement rule and mounted, so that the actual mounting position of the alignment point chip is located in an alignment window of exposure equipment corresponding to a subsequent process, and other first chip mounting positions correspond to the preset mounting positions of the first fan-out packaging area.
Optionally, each alignment area selects two diagonal first chips as alignment point chips, and the two alignment point chips are respectively moved to the middle positions of four adjacent first chips from the preset patch positions of the corresponding alignment fan-out packaging area according to a preset movement rule and then are patched.
Optionally, each alignment area selects one first chip as an alignment point chip, and the alignment point chip moves from a preset patch position of the corresponding alignment fan-out packaging area to a middle position of four adjacent first chips according to a preset movement rule and patches.
Optionally, when the predetermined patch position corresponding to the alignment point chip is located in the alignment window of the exposure device corresponding to the subsequent photolithography process, the actual patch position of the alignment point chip is located in the alignment fan-out packaging area corresponding to the alignment point chip.
Optionally, when the predetermined patch positions of the alignment point chips corresponding to the first fan-out packaging areas are all located outside the exposure equipment alignment window corresponding to the subsequent photolithography process, the actual patch positions of the alignment point chips do not exceed the minimum width area required by the packaging dicing channels between four adjacent first fan-out packaging areas.
Optionally, the first fan-out package area has a plurality of other chips besides the first chip, and the other chips are attached to predetermined attachment positions corresponding to the other chips.
In summary, the beneficial effects of the invention are as follows:
According to the invention, at least three alignment areas are selected in the fan-out packaging wafer substrate, each alignment area at least comprises four adjacent first chips with the size of 2x2, at least one first chip is selected as an alignment point chip in each alignment area, in a chip mounting process, the alignment point chip is moved from a preset mounting position to the middle position of the four adjacent first chips according to a preset movement rule, so that the actual mounting position of the alignment point chip is positioned in an exposure equipment alignment window corresponding to a subsequent process, and the chip mounting position of the whole fan-out packaging wafer substrate is determined according to the position of the alignment point chip in the exposure equipment alignment window and the preset movement rule. According to the invention, the alignment point chips in a plurality of alignment areas are sacrificed, the alignment point chips are moved to the middle positions of four adjacent first chips according to the preset movement rule, and the alignment point positions are determined, so that the chip patch positions of the whole fan-out packaging wafer substrate can be determined, the rows and columns of the chips cannot be misplaced when the exposure equipment performs coarse alignment, the method is suitable for photoetching on the existing photoetching machine, additional alignment point pattern manufacturing is not needed, and the cost is low.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings.
Drawings
FIG. 1 is a schematic diagram of a photolithography alignment structure in a photolithography process based on a conventional wafer level packaging process in the prior art;
FIGS. 2 and 3 are schematic diagrams of photolithography alignment structures in the prior art for performing photolithography based on wafer fan-out package;
FIG. 4 is a schematic flow chart of a photolithography alignment method of a fan-out package wafer according to an embodiment of the present invention;
Fig. 5 to 10 are schematic structural diagrams of a fan-out package wafer according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples for the purpose of facilitating understanding to those skilled in the art.
The embodiment of the invention firstly provides a lithography alignment method of a fan-out package wafer, please refer to fig. 4, which is a flow chart diagram of the lithography alignment method, comprising:
Step S100, a fan-out packaging wafer substrate is provided, the fan-out packaging wafer substrate is provided with a plurality of first fan-out packaging areas and first chips which are adhered to the first fan-out packaging areas, at least three alignment areas are selected in the fan-out packaging wafer substrate, and each alignment area at least comprises four adjacent first chips with the size of 2x2 and four adjacent first fan-out packaging areas corresponding to each first chip;
step S200, each alignment area selects at least one first chip as an alignment point chip, a first fan-out packaging area corresponding to the alignment point chip is used as an alignment fan-out packaging area, and in a chip mounting process, the alignment point chip is moved and mounted from a preset mounting position of the alignment fan-out packaging area to the middle positions of four adjacent first chips according to a preset movement rule, so that the actual mounting position of the alignment point chip is positioned in an exposure equipment alignment window corresponding to a subsequent process;
and step S300, determining the position of the counterpoint point and the chip patch position of the whole fan-out packaging wafer substrate according to the position of the counterpoint point chip in the counterpoint window of the exposure equipment and a preset movement rule.
Specifically, step S100 is performed, please refer to fig. 5 and 8, fig. 5 is a schematic diagram of an overall structure of the fan-out package wafer, and fig. 8 is a schematic diagram of structures of four adjacent first chips and four corresponding adjacent first fan-out package regions in a alignment region.
In this embodiment, the fan-out package wafer substrate is a substrate for fan-out package of a subsequent chip, and the fan-out package wafer substrate may be one of a package carrier, a glass carrier, a blank semiconductor wafer, and the like.
In a wafer fan-out packaging process, chip mounting is carried out at a preset position on the surface of a fan-out packaging wafer substrate, and chip plastic packaging is carried out on the surface of the fan-out packaging wafer substrate and the surface of the chip to form a chip packaging structure; and then stripping the fan-out packaging wafer substrate and the chip packaging structure, and forming a rewiring layer on the stripping surface corresponding to the chip packaging structure, wherein a metal pattern is required to be formed by utilizing a photoetching process when the rewiring layer is formed.
The photolithography process needs to perform coarse alignment on the alignment sites first, and if the photolithography process is performed without wafer fan-out package formation to form a redistribution layer, as shown in fig. 1, scribe line intersections between four adjacent chips are often used as the alignment sites for coarse alignment. However, with the diversity of the layout of the fan-out packaging wafer, the chips are located at different positions of the packaging structure and have different fan-out ratios, so that the distance is changed more and the distance is increased after the chips are rearranged, and even the distance is larger than the size of an alignment window (as shown in fig. 3) of exposure equipment corresponding to a photolithography process, that is, any chip cannot be found in an existing alignment window of the exposure equipment, alignment cannot be performed accordingly, and alignment row and column errors are easily caused by the method, so that alignment failure is caused.
For this reason, in the present embodiment, the fan-out package wafer substrate 10 is divided into a plurality of first fan-out package regions 20, one of the first fan-out package regions 20 is used to form one fan-out package structure, and the size of the first fan-out package region 20 is larger than the size of the first chip of the pre-patch.
When coarse alignment is performed, at least three alignment points are needed for the fan-out packaging wafer to perform alignment so as to determine chip distribution after chip mounting. At least three alignment areas 15 are thus selected within the fan-out package wafer substrate, one alignment point for each alignment area 15.
As shown in fig. 5 and 6, the dashed box illustrates one alignment area 15, and six adjacent first fan-out package areas 20 and six predetermined patch locations 31 of adjacent first chips are included in the alignment area 15.
In other embodiments, each alignment region includes at least 2x2 four adjacent first fan-out package regions 20 and 2x2 four adjacent first chips.
In the following description, four adjacent first chips 30 are b, c, d, e, and one first chip 30 corresponds to one first fan-out package region 20. The four first chips 30 have corresponding predetermined patch locations 31 within the corresponding first fan-out package regions 20.
In the present embodiment, as shown in fig. 6 to 10, one first fan-out package region 20 is used for packaging only one first chip 30.
In other embodiments, one first fan-out package region encapsulates one first chip in addition to other chips at the same time. The first chip and the other chips may be the same or different in chip type and size. The first chip differs from the other chips only in that: at least one first chip is used as an alignment point chip to move to the middle positions of four adjacent first chips in the alignment area of the fan-out packaging wafer substrate, so that the actual patch position of the alignment point chip is positioned in an exposure equipment alignment window corresponding to the subsequent photoetching process.
Step S200 is executed, as shown in fig. 6 to 8, each alignment area has at least four adjacent first chips, at least one first chip is selected as an alignment point chip 30', a first fan-out package area corresponding to the alignment point chip 30' is selected as an alignment fan-out package area 20', in the chip mounting process, the alignment point chip 30' is moved from a predetermined mounting position 31 of the alignment fan-out package area 20 'to an intermediate position of the four adjacent first chips according to a predetermined movement rule and mounted, so that an actual mounting position 32' of the alignment point chip is located in an alignment window of exposure equipment corresponding to a subsequent process, and the rest of the first chips 30 are still mounted at the predetermined mounting positions 31 corresponding to the first fan-out package area 20.
Fig. 6 is a schematic structural diagram of a predetermined chip mounting position of a first chip including the alignment point chips b and e in the alignment area, fig. 7 is a schematic structural diagram of an actual chip mounting position of the first chip including the alignment point chips b and e in the alignment area, and fig. 8 is a schematic structural diagram of a moving position in the chip mounting process of the first chip.
The predetermined patch position of the alignment point chip corresponding to the first fan-out packaging region may be located in the field of view of the alignment window of the exposure device corresponding to the subsequent photolithography process, or may be located outside the field of view of the alignment window of the exposure device corresponding to the subsequent photolithography process.
In this embodiment, as shown in fig. 8, the pair of bit point chips are two first chips, and the pair of bit point chips b and e are diagonally arranged. When the predetermined patch positions 31 of the alignment point chips b and e corresponding to the first fan-out package region are all or partially located in the exposure device alignment window 40 corresponding to the subsequent photolithography process, the actual patch positions 32 of the alignment point chips b and e are still located in the alignment fan-out package region 20' corresponding to the alignment point chips after moving to the intermediate position according to the predetermined movement rule.
The predetermined movement rule may be a determined fixed value, or may be a movement rule determined according to the position and the size of the first chip in the first fan-out package area 20.
In the embodiment shown in fig. 9, since the predetermined patch positions 31 and the actual patch positions 32 of the pair-site chips are all located within the exposure apparatus alignment window 40, only a specific position needs to be moved to determine the pair-site using the pair-site chips b and e. As shown in table 1, there are four adjacent first fan-out package regions and four adjacent first die dimensional implications.
TABLE 1
Wherein the maximum moving distance of the opposite site chip b in the X-axis direction is (L-X)/2- (O '-O), the minimum moving distance is 2um, the maximum moving distance of the opposite site chip b in the Y-axis direction is (W-Y)/2+ (P' -P), and the minimum moving distance is 2um.
Wherein the maximum moving distance of the opposite site chip e in the X-axis direction is (L-X)/2+ (O '-O), the minimum moving distance is 2um, the maximum moving distance of the opposite site chip b in the Y-axis direction is (W-Y)/2- (P' -P), and the minimum moving distance is 2um.
The minimum moving distance can be adjusted according to different processes.
In other embodiments, as shown in fig. 10, when the predetermined patch positions 31 corresponding to the counterpoint chip 30 'are all located outside the exposure device counterpoint window 40 corresponding to the subsequent photolithography process, after the counterpoint chip 30' moves to the intermediate position, the maximum moving position of the predetermined patch positions corresponding to the counterpoint chip 30 'does not exceed the minimum width area required by the package scribe line between the four adjacent first fan-out package areas, and the actual patch positions corresponding to the counterpoint chip 30' do not exceed the minimum width area required by the package scribe line between the four adjacent first fan-out package areas.
Wherein the maximum moving distance of the para-site chip b in the X-axis direction is (L-X+K-K ')/2- (O' -O), the minimum moving distance is (L-X+K-M)/2- (O '-O), the maximum moving distance of the para-site chip b in the Y-axis direction is (W-Y+K-K')/2+ (P '-P), and the minimum moving distance is (W-Y+K-N)/2+ (P' -P).
Wherein the maximum moving distance of the opposite site chip e in the X-axis direction is (L-X+K-K ')/2+ (O' -O), the minimum moving distance is (L-X+K-M)/2+ (O '-O), the maximum moving distance of the opposite site chip b in the Y-axis direction is (W-Y+K-K')/2- (P '-P), and the minimum moving distance is (W-Y+K-N)/2- (P' -P).
Since the predetermined patch positions corresponding to the alignment point chips are all located outside the alignment window 40 of the exposure device corresponding to the subsequent photolithography process, it is necessary to increase the predetermined moving distance of the alignment point chips, even if the actual patch positions of the alignment point chips are located in the preset scribe line region (i.e., the region with the width of K), the minimum width region (i.e., the region with the width of K') required for packaging the finished scribe line is not covered, and the subsequent scribe and dicing is not affected.
In this embodiment, in the chip mounting process, the alignment point chip is moved to the middle positions of four adjacent first chips according to a predetermined movement rule, so that the actual mounting position of the alignment point chip is located in the alignment window of the exposure device corresponding to the subsequent photolithography process, but other first chips that are not used as the alignment point chip still normally mount at the predetermined mounting position, and the fan-out package structure corresponding to the first chip still can normally work.
The invention performs counterpoint for the whole fan-out packaging wafer by sacrificing a plurality of fan-out packaging structures corresponding to the plurality of counterpoint chips, does not need to additionally perform counterpoint manufacture, is applicable to the photoetching of the existing photoetching machine, and has lower cost.
In other embodiments, when the first chip and the other chips are simultaneously mounted in the first fan-out package area, the positioning point chip and the other chips are simultaneously mounted in the positioning fan-out package area, and only the positioning point chip is moved, the position of the mounting is adjusted, and the other chips in the positioning fan-out package area are not moved, but are mounted at the corresponding predetermined mounting positions.
In other embodiments, when the first fan-out package region has the first chip and other chips simultaneously, only the alignment point chip is attached to the alignment fan-out package region, and other chips are not attached to the alignment point chip, so that the positions of the moved alignment point chip and other chips are prevented from overlapping.
In this embodiment, the alignment point chip 30' of the alignment fan-out package region is mounted by using a normal first chip, and in other embodiments, the alignment point chip of the alignment fan-out package region may also be mounted by selecting a waste chip or a blank chip.
And step S300, determining the position of the counterpoint point and the chip patch position of the whole fan-out packaging wafer substrate according to the position of the counterpoint point chip in the counterpoint window of the exposure equipment and a preset movement rule.
In this embodiment, the distances that the two alignment point chips 30' move to the middle positions of the four adjacent first chips are different, and the two alignment point chips b and e move according to the predetermined movement rule, so that the middle positions of the two alignment point chips b and e are the center positions of the alignment points, and the chip patch positions of the whole fan-out packaging wafer substrate are determined by using the alignment point positions.
In other embodiments, one corner of two alignment point chips may be used as an alignment point.
In this embodiment, the alignment sites are determined by using the alignment site chips, and the chip layout positions of the fan-out package wafer are coarsely positioned by using the alignment sites, so that the actual positions of the alignment sites can be set within the range of the alignment window of the exposure device according to the needs, and the method is not particularly limited.
In other embodiments, the distances that the two counterpoint chips move to the middle positions of the four adjacent first chips may be the same, and the positions of the counterpoint chips may also be determined by acquiring the sizes of the counterpoint chips, the sizes of the first fan-out packaging regions, the sizes of the dicing streets, the positions of the predetermined patch positions of the counterpoint chips in the first fan-out packaging regions, and the distances that the counterpoint chips move to the middle positions.
In other embodiments, only one counterpoint chip corresponding to one counterpoint area may be provided, and only one counterpoint chip in the four first chips may be moved to the middle positions of four adjacent first chips, where the position of the counterpoint point may also be determined by obtaining the size of the counterpoint chip, the size of the first fan-out package area, the size of the scribe line, the position of the counterpoint chip in the first fan-out package area, the distance that the counterpoint chip moves to the middle position, and the accurate position of the counterpoint chip in the counterpoint window of the exposure device.
In other embodiments, more than 2 counterpoint chips corresponding to one counterpoint region may be used to position the plurality of counterpoint chips by adjusting the positions of the plurality of counterpoint chips.
The embodiment of the invention also provides a fan-out packaging wafer, as shown in fig. 5-8, comprising:
a fan-out package wafer substrate 10, wherein the fan-out package wafer substrate 10 has a plurality of first fan-out package regions 20 and first chips 30 attached to the first fan-out package regions;
The fan-out package wafer substrate 10 has at least three alignment areas 15 therein, and the alignment areas 15 include at least 2x2 four adjacent first chips 30 and four adjacent first fan-out package areas 20 corresponding to each first chip;
At least one first chip in each alignment area is used as an alignment point chip 30', a first fan-out packaging area corresponding to the alignment point chip is used as an alignment fan-out packaging area 20', in a chip mounting process, the alignment point chip 30' is moved and mounted from a preset mounting position 31' of the alignment fan-out packaging area to the middle position of four adjacent first chips according to a preset movement rule, so that the actual mounting position of the alignment point chip 30' is located in an exposure equipment alignment window 40 corresponding to a subsequent process, and the rest of first chips 30 are mounted at the preset mounting positions 31 corresponding to the first fan-out packaging area.
In this embodiment, as shown in fig. 8 and 9, the pair of the bit point chips 30' are two first chips, and the pair of the bit point chips b and e are diagonally arranged. When the predetermined patch positions 31 of the alignment fan-out package regions 20' corresponding to the alignment point chips b and e are all or partially located in the alignment window 40 of the exposure device corresponding to the subsequent photolithography process, the actual patch positions of the alignment point chips b and e are still located in the alignment fan-out package regions 20' corresponding to the alignment point chips 30' after moving to the intermediate positions according to the predetermined movement rule.
In one embodiment, the predetermined movement rule is specifically:
Wherein the maximum moving distance of the opposite site chip b in the X-axis direction is (L-X)/2- (O '-O), the minimum moving distance is 2um, the maximum moving distance of the opposite site chip b in the Y-axis direction is (W-Y)/2+ (P' -P), and the minimum moving distance is 2um.
Wherein the maximum moving distance of the opposite site chip e in the X-axis direction is (L-X)/2+ (O '-O), the minimum moving distance is 2um, the maximum moving distance of the opposite site chip b in the Y-axis direction is (W-Y)/2- (P' -P), and the minimum moving distance is 2um.
In other embodiments, as shown in fig. 10, when the predetermined patch positions 31 'of the alignment point chip 30' corresponding to the first fan-out package regions are all located outside the exposure device alignment window 40 corresponding to the subsequent photolithography process, the maximum moving position of the predetermined patch positions of the alignment point chip 30 'after moving to the intermediate position does not exceed the minimum width region (i.e., the region with the width K') required by the package dicing streets between four adjacent first fan-out package regions.
Wherein the maximum moving distance of the para-site chip b in the X-axis direction is (L-X+K-K ')/2- (O' -O), the minimum moving distance is (L-X+K-M)/2- (O '-O), the maximum moving distance of the para-site chip b in the Y-axis direction is (W-Y+K-K')/2+ (P '-P), and the minimum moving distance is (W-Y+K-N)/2+ (P' -P).
Wherein the maximum moving distance of the opposite site chip e in the X-axis direction is (L-X+K-K ')/2+ (O' -O), the minimum moving distance is (L-X+K-M)/2+ (O '-O), the maximum moving distance of the opposite site chip b in the Y-axis direction is (W-Y+K-K')/2- (P '-P), and the minimum moving distance is (W-Y+K-N)/2- (P' -P).
In other embodiments, the first fan-out package region has a plurality of other chips in addition to the first chip, and the chip types and the chip sizes of the first chip and the other chips may be the same or different. The first chip differs from the other chips only in that: at least one first chip is used as an alignment point chip to move to the middle positions of four adjacent first chips in the alignment area of the fan-out packaging wafer substrate, so that the actual patch position of the alignment point chip is positioned in an exposure equipment alignment window corresponding to the subsequent photoetching process.
In other embodiments, when the first fan-out package region has the first chip and other chips simultaneously, only the alignment point chip is attached to the alignment fan-out package region, and other chips are not attached to the alignment point chip, so that the positions of the moved alignment point chip and other chips are prevented from overlapping.
In this embodiment, the normal first chip is used for bonding the position point chip, and in other embodiments, a waste chip or a blank chip may be selected for bonding.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the present invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the present invention.
Claims (12)
1. The alignment method of the fan-out packaging wafer is characterized by comprising the following steps of:
Providing a fan-out packaging wafer substrate, wherein the fan-out packaging wafer substrate is provided with a plurality of first fan-out packaging areas and first chips attached to the first fan-out packaging areas, at least three alignment areas are selected in the fan-out packaging wafer substrate, and each alignment area at least comprises 2x2 four adjacent first chips and four adjacent first fan-out packaging areas corresponding to each first chip;
Each alignment area selects at least one first chip as an alignment point chip, a first fan-out packaging area corresponding to the alignment point chip is used as an alignment fan-out packaging area, and in a chip mounting process, the alignment point chip is moved and mounted from a preset mounting position of the alignment fan-out packaging area to the middle positions of four adjacent first chips according to a preset movement rule, so that the actual mounting position of the alignment point chip is positioned in an exposure equipment alignment window corresponding to a subsequent process;
and determining the opposite site position and the chip patch position of the whole fan-out packaging wafer substrate according to the position of the opposite site chip in the exposing device and a preset movement rule.
2. The alignment method of fan-out package wafer according to claim 1, wherein each alignment area selects two diagonally opposite first chips as alignment point chips, and the two alignment point chips are respectively moved from the predetermined patch positions of the corresponding alignment fan-out package area to the intermediate positions of four adjacent first chips according to a predetermined movement rule and are patched.
3. The method of aligning fan-out package wafers of claim 1 wherein each alignment area selects one first chip as an alignment point chip, and the alignment point chip moves from a predetermined patch position of the corresponding alignment fan-out package area to an intermediate position of four adjacent first chips according to a predetermined movement rule and patches.
4. The method for aligning a fan-out package wafer according to claim 1, wherein when the predetermined patch position corresponding to the alignment point chip is located in the alignment window of the exposure device corresponding to the subsequent photolithography process, the actual patch position of the alignment point chip is still located in the alignment fan-out package area corresponding to the alignment point chip after the alignment point chip moves to the middle position during the patch.
5. The alignment method of fan-out package wafers according to claim 1, wherein when the predetermined positions of the alignment point chips are all located outside the alignment window of the exposure device corresponding to the subsequent photolithography process, the maximum moving position of the alignment point chips after the alignment point chips move to the middle position does not exceed the minimum width area required by the package dicing streets between four adjacent first fan-out package areas.
6. The photolithographic alignment method of a fan-out package wafer of claim 1, wherein the first fan-out package region has a plurality of other chips in addition to the first chip, and the other chips are attached to predetermined attachment locations corresponding to the other chips.
7. A fan-out package wafer, comprising:
The fan-out packaging wafer substrate is provided with a plurality of first fan-out packaging areas and first chips which are adhered to the first fan-out packaging areas;
the fan-out packaging wafer substrate is internally provided with at least three alignment areas, and the alignment areas at least comprise four adjacent first chips with the size of 2x2 and four adjacent first fan-out packaging areas corresponding to each first chip;
At least one first chip of each alignment area is used as an alignment point chip, a first fan-out packaging area corresponding to the alignment point chip is used as an alignment fan-out packaging area, in a chip mounting process, the alignment point chip is moved from a preset mounting position of the alignment fan-out packaging area to the middle positions of four adjacent first chips according to a preset movement rule and mounted, so that the actual mounting position of the alignment point chip is located in an alignment window of exposure equipment corresponding to a subsequent process, and other first chip mounting positions correspond to the preset mounting positions of the first fan-out packaging area.
8. The fan-out package wafer of claim 7, wherein each alignment area selects two diagonally opposite first chips as alignment point chips, and the two alignment point chips are moved from the predetermined patch positions of the corresponding alignment fan-out package areas to the actual patch positions and patches according to a predetermined movement rule.
9. The fan-out package wafer of claim 7, wherein each alignment area selects a first chip as an alignment point chip, and the alignment point chip is moved from a predetermined patch position of the corresponding alignment fan-out package area to an actual patch position and is patched according to a predetermined movement rule.
10. The fan-out package wafer of claim 7, wherein when the predetermined patch positions corresponding to the pair of site chips are located in the alignment window of the exposure device corresponding to the subsequent photolithography process, the actual patch positions of the pair of site chips are located in the alignment fan-out package region corresponding to the pair of site chips.
11. The fan-out package wafer of claim 7, wherein when the predetermined patch positions of the alignment point chips corresponding to the first fan-out package regions are all located outside the exposure equipment alignment window corresponding to the subsequent photolithography process, the actual patch positions of the alignment point chips do not exceed the minimum width region required by the package dicing streets between four adjacent first fan-out package regions.
12. The fan-out package wafer of claim 7, wherein the first fan-out package region has a plurality of other chips in addition to the first chip, the other chips being mounted at predetermined mounting locations corresponding to the other chips.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104733440A (en) * | 2013-12-23 | 2015-06-24 | 英飞凌科技股份有限公司 | Alignment Mark Arrangement, Semiconductor Workpiece, And Method For Aligning Wafer |
| CN106601634A (en) * | 2016-08-25 | 2017-04-26 | 合肥祖安投资合伙企业(有限合伙) | Chip package technology and chip package structure |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999050893A1 (en) * | 1998-03-30 | 1999-10-07 | Nikon Corporation | Exposure method and exposure system |
| US6954272B2 (en) * | 2002-01-16 | 2005-10-11 | Intel Corporation | Apparatus and method for die placement using transparent plate with fiducials |
| JP4040668B2 (en) * | 2007-04-05 | 2008-01-30 | キヤノン株式会社 | Position detection apparatus and method, exposure apparatus, and device manufacturing method |
| JP2012222003A (en) * | 2011-04-04 | 2012-11-12 | Renesas Electronics Corp | Method for manufacturing semiconductor device and shot layout method using serial exposure |
| TWI629729B (en) * | 2016-12-19 | 2018-07-11 | 技鼎股份有限公司 | Chip positioning method and manufacturing equipment for use in fan-out process |
| JP7369529B2 (en) * | 2019-02-28 | 2023-10-26 | 株式会社オーク製作所 | Exposure equipment and alignment method |
| US11183482B2 (en) * | 2019-09-17 | 2021-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Shift control method in manufacture of semiconductor device |
| US11380649B2 (en) * | 2020-09-08 | 2022-07-05 | Sj Semiconductor (Jiangyin) Corporation | Fan-out wafer-level packaging structure and method packaging the same |
| CN113161227B (en) * | 2021-02-05 | 2021-12-24 | 广东工业大学 | Fan-out packaging system, method and rewiring method based on maskless lithography |
-
2022
- 2022-06-07 CN CN202210636457.6A patent/CN115036251B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104733440A (en) * | 2013-12-23 | 2015-06-24 | 英飞凌科技股份有限公司 | Alignment Mark Arrangement, Semiconductor Workpiece, And Method For Aligning Wafer |
| CN106601634A (en) * | 2016-08-25 | 2017-04-26 | 合肥祖安投资合伙企业(有限合伙) | Chip package technology and chip package structure |
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