CN115424372B - Intelligent lock circuit, unlocking method and device and intelligent lock - Google Patents

Abstract

This application discloses a smart lock circuit, unlocking method, device and smart lock. This application detects the feedback AD value of the card through a signal transmission processing circuit and a detection circuit to update the reference value for judging whether there is a card, and whether the card meets the card swiping proximity and The characteristic of slow approach is used to determine when a card is approaching, so that the environment without a card can be updated at all times, and the wrong baseline value can be avoided when the card does not leave the panel. When a card is approaching, it responds quickly, allowing the low-power card detection function to be stable. reliable.

Description

Smart lock circuit, unlocking method, device and smart lock

Technical field

This application relates to the field of smart locks, especially smart lock circuits, unlocking methods, devices and smart locks.

Background technique

Proximity card (ic card) is a verification method for smart locks to open the door. When the smart lock system is dormant, it can only determine whether a card is close to the card swipe panel of the smart lock and needs to be verified, resulting in long response times and slow response speed, which reduces the user experience.

Therefore, the above technical problems existing in related technologies need to be solved urgently.

Contents of the invention

This application aims to solve one of the technical problems in the related art. To this end, embodiments of the present application provide smart lock circuits, unlocking methods, devices and smart locks, which can improve the unlocking efficiency of smart locks.

According to one aspect of the embodiment of the present application, a smart lock circuit is provided, and the circuit includes a signal transmission processing circuit and a detection circuit,

The detection circuit includes a first capacitor, a first resistor, and a second resistor. The first capacitor and the first resistor are connected in parallel. The first end of the first capacitor is connected to the main control pin. The first The second end of the capacitor is connected to ground, the first end of the second resistor is connected to the first end of the first capacitor, and the second end of the second resistor is connected to the signal transmission and processing circuit.

Wherein, the signal transmission and processing circuit includes a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a third resistor, four resistors, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a diode;

The third capacitor, the fourth capacitor, and the fifth capacitor are connected in parallel with each other, the first end of the sixth capacitor is connected to the first end of the second capacitor, and the second end of the sixth capacitor is connected to the first end of the sixth capacitor. The first ends of the three capacitors are connected, the first end of the second capacitor is connected to the main control pin, and the second ends of the second capacitor and the third capacitor are connected to the first end of the third resistor. , the second end of the third resistor is connected to ground; the fourth resistor and the seventh capacitor are connected in parallel, the first end of the fourth resistor is connected to the first end of the fifth resistor, and the fifth resistor The second end is connected to the first end of the eighth capacitor and the first end of the ninth capacitor. The second end of the ninth capacitor is connected to the first end of the sixth resistor and the first end of the seventh resistor. connection, the second end of the seventh resistor is connected to the first end of the eighth resistor and the second end of the tenth capacitor, and the first end of the tenth capacitor is connected to the second end of the sixth resistor. Connection, the second end of the fourth resistor, the eighth capacitor and the sixth resistor are all grounded, and the second end of the eighth resistor is connected to the power supply;

The first end of the seventh resistor is connected to the first radio frequency antenna connection line, and the second end of the seventh resistor is connected to the second radio frequency antenna connection line;

The second end of the sixth capacitor is connected to the anode of the diode, and the cathode of the diode is connected to the first end of the fifth resistor. , the second end of the second resistor is connected to the first end of the eighth capacitor.

Wherein, the circuit also includes a main control module, which transmits radio frequency signals through the signal transmission processing circuit and the radio frequency antenna;

The main control module detects feedback analog signals through the detection circuit and the radio frequency antenna;

The main control module converts the feedback analog signal into a digital signal.

According to one aspect of the embodiment of the present application, a smart lock unlocking method is provided, which is applied to the smart lock circuit described in the previous embodiment. The method includes:

Get feedback AD value;

If the absolute difference between the feedback AD value and the reference value is less than the first preset difference, update the reference value according to the feedback AD value;

Wherein, the reference value is the feedback AD value tested when no card is close to the card.

Wherein, the obtaining the feedback AD value also includes:

Detect feedback analog signals;

The feedback analog signal is converted into a feedback AD value.

Wherein, the method also includes:

Obtain the feedback AD value twice;

If the difference between the feedback AD value obtained for the first time and the reference value is greater than or equal to the second preset difference, and the difference between the feedback AD value obtained for the first time and the feedback AD value obtained for the second time is If the difference is greater than or equal to the third preset difference, and the duration is less than or equal to the first preset time, it is determined that a card is currently approaching slowly.

Wherein, the method includes:

If the difference between the feedback AD value and the reference value is greater than or equal to the fourth preset difference, and the duration is less than or equal to the second preset time, it is determined that a card is approaching quickly and the system is awakened to read the card.

According to one aspect of the embodiment of the present application, a smart lock unlocking device is provided, and the device includes:

at least one processor;

At least one memory for storing at least one program;

The smart lock unlocking method as described in the previous embodiment is implemented when at least one of the programs is executed by at least one of the processors.

According to one aspect of the embodiment of the present application, a smart lock is provided, and the smart lock includes the smart lock circuit as described in the previous embodiment.

The beneficial effects of the smart lock circuit, unlocking method, device and smart lock provided by the embodiments of this application are: this application uses a radio frequency circuit, a detection circuit and a transmitting circuit to detect the feedback AD value of the card to update the reference value for judging whether there is a card. , whether the card meets the characteristics of card swiping and slow approaching to determine whether a card is approaching. This can update the environment without a card at all times, and avoid updating the wrong baseline value when the card does not leave the panel. When a card is approaching, it can respond quickly, allowing low-cost users to The power consumption detection card function is stable and reliable.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Description of the drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.

Figure 1 is a circuit diagram of a smart lock circuit provided by an embodiment of the present application;

Figure 2 is a schematic diagram of a smart lock device provided by an embodiment of the present application;

Figure 3 is a schematic diagram of another smart lock device provided by an embodiment of the present application.

Detailed ways

In order to enable those in the technical field to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only These are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall within the scope of protection of this application.

The terms “first”, “second”, “third” and “fourth” in the description, claims and drawings of this application are used to distinguish different objects, rather than describing a specific sequence. Furthermore, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes Other steps or units inherent to such processes, methods, products or devices.

Reference herein to "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.

Proximity card (ic card) is a verification method for smart locks to open the door. When the smart lock system is dormant, it can only determine whether a card is close to the card swipe panel of the smart lock and needs to be verified, resulting in long response times and slow response speed, which reduces the user experience.

In order to solve the above problems, this application proposes a smart lock circuit, unlocking method, device and smart lock.

In this embodiment, when the smart lock system is sleeping, it can only be judged whether a card is close to the card swiping panel of the smart lock by detecting whether there is a card that needs to be verified. This can achieve the low-power card detection function; low power consumption The card detection function is to detect the AD value of the feedback voltage of the antenna by sending a radio frequency (RFID enable) to the card swiping circuit and the antenna to determine whether a card is approaching. The detected feedback voltage of the antenna has a fluctuating value. According to the absence of a card approaching , the card approach algorithm is based on the characteristics of the card approaching quickly and the card approaching slowly, so as to achieve the purpose of waking up the system when the card is approaching and preventing the card from being accidentally triggered to wake up by swiping the card.

Figure 1 Legend: R47-first resistor, R48-second resistor, R55-third resistor, R51-fourth resistor, R49-fifth resistor, R52-sixth resistor, R53-seventh resistor, R56-eighth Resistor, C11-first capacitor, C17-second capacitor, C18-third capacitor, C19-fourth capacitor, C20-fifth capacitor, C13-sixth capacitor, C21-seventh capacitor, C22-eighth capacitor, C14-the ninth capacitor, C23-the tenth capacitor.

Specifically, Figure 1 is a circuit diagram of a smart lock circuit provided by an embodiment of the present application. As shown in Figure 1, the smart lock circuit proposed by this application includes a radio frequency circuit, a detection circuit and a transmitting circuit. The circuit includes a signal transmission processing circuit, Detection circuit, the detection circuit includes a first capacitor, a first resistor, and a second resistor. The first capacitor and the first resistor are connected in parallel. The first end of the first capacitor is connected to the main control pin, so The second end of the first capacitor is connected to ground, the first end of the second resistor is connected to the first end of the first capacitor, and the second end of the second resistor is connected to the signal transmission and processing circuit.

Wherein, the signal transmission and processing circuit includes a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a third resistor, Four resistors, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a diode; the third capacitor, the fourth capacitor and the fifth capacitor are connected in parallel with each other, and the first end of the sixth capacitor and the first The first ends of the two capacitors are connected, the second end of the sixth capacitor is connected to the first end of the third capacitor, the first end of the second capacitor is connected to the main control pin, and the third capacitor is connected to the first end of the third capacitor. The second ends of the second capacitor and the third capacitor are connected to the first end of the third resistor, and the second end of the third resistor is connected to ground; the fourth resistor and the seventh capacitor are connected in parallel, and the fourth The first end of the resistor is connected to the first end of the fifth resistor, and the second end of the fifth resistor is connected to the first end of the eighth capacitor and the first end of the ninth capacitor. The second end is connected to the first end of the sixth resistor and the first end of the seventh resistor. The second end of the seventh resistor is connected to the first end of the eighth resistor and the second end of the tenth capacitor. connection, the first end of the tenth capacitor is connected to the second end of the sixth resistor, the second ends of the fourth resistor, the eighth capacitor and the sixth resistor are all grounded, and the eighth end of the eighth resistor is connected to the ground. Two ends are connected to the power supply; the first end of the seventh resistor is connected to the first radio frequency antenna connection line, the second end of the seventh resistor is connected to the second radio frequency antenna connection line; the second end of the sixth capacitor is connected to the power supply. The terminal is connected to the anode of the diode, and the cathode of the diode is connected to the first terminal of the fifth resistor. , the second end of the second resistor is connected to the first end of the eighth capacitor.

Wherein, the circuit also includes a main control module, which transmits radio frequency signals through the signal transmission processing circuit and the radio frequency antenna; the main control module detects feedback analog signals through the detection circuit and the radio frequency antenna; The main control module converts the feedback analog signal into a digital signal.

It should be noted that to detect the card circuit diagram and feedback voltage AD value: send a 13.6M radio frequency signal to the circuit through RF_TXP, send it out through the antenna connected to CMP_INP and CMP_INN, and then detect the feedback AD value of the antenna through RF_ADC; usually when there is no card nearby When , the AD value of the voltage detected by RF_ADC is M units. If the card approaches quickly (approach time is less than 300ms), the AD value is N units. If the card approaches slowly (approach time is greater than twice 300ms), the AD value approaches is It is divided into two detections, namely P and Q units.

Based on the smart lock unlocking circuit proposed in the above embodiment, this embodiment provides three unlocking situations, including:

(1) No card proximity detection algorithm:

The detection method when no card is approaching includes: obtaining the feedback AD value detected by the detection circuit; if the absolute difference between the feedback AD value and the reference value is less than the first preset difference, updating the feedback AD value according to the feedback AD value Reference value; wherein, the reference value is the feedback AD value obtained by testing without a card approaching. Specifically, when no card is detected after powering on for the first time, the M value of no card is used as the reference value D. At this time, M is equal to D. The next time no card is detected, the M value of no card is detected. The absolute value difference between the value and the reference value D is less than 60 units, then use M to update the reference value D that is close to the card without a card; on the contrary, if the absolute value difference between the currently detected value of M and the reference value D is greater than 60 units, keep The base value D remains unchanged (does not need to be updated). If the card never leaves the panel and the detected values are all greater than plus or minus 60 units, the base value will not be updated. The expression of the feedback AD value in this embodiment is:

if(M>D-60&&M<D+60)，D＝M

Among them, M is the voltage AD value detected by RF_ADC, and D is the reference value when no card is close.

(2) Fast card approach detection algorithm

The detection method of fast card approach includes: if the difference between the feedback AD value and the reference value is greater than or equal to the fourth preset difference value, and the duration is less than or equal to the preset time, then it is determined that a card is currently approaching quickly and wakes up the system Read the card. Specifically, if the card approaches the card swiping panel for no more than 300ms, the feedback AD value N is more than 800 units smaller than the reference value, and it is immediately determined that a card is approaching and the card is read after waking up the system. The expression of the feedback AD value in this embodiment is:

if(N<D-800)

(3) Detection algorithm for slow card approach

The detection method of slow card approach includes: obtaining the feedback AD value twice; if the difference between the feedback AD value obtained for the first time and the reference value is greater than or equal to the second preset difference, and the feedback AD value obtained for the first time is If the difference between the feedback AD value and the feedback AD value obtained for the second time is greater than or equal to the third preset difference, it is determined that a card is currently approaching slowly. Specifically, if the card is close to the card swiping panel for no more than 600ms, the AD values P and Q units will be detected twice. The first time P is less than the reference value D by more than 100 units, and the second time Q is less than the reference value D. P is less than 100 units. The expression of the feedback AD value in this embodiment is:

if(P<D-100&&Q<P-100)

Among them, P is the voltage AD value detected for the first time, and Q is the voltage AD value detected for the second time.

According to one aspect of the embodiment of the present application, a smart lock unlocking method is provided, which is applied to the smart lock circuit described in the previous embodiment. The method includes: obtaining a feedback AD value; if the absolute difference between the feedback AD value and the reference value is If the difference is less than the first preset difference, the reference value is updated according to the feedback AD value; wherein the reference value is the feedback AD value tested when no card is close to the card. Wherein, obtaining the feedback AD value further includes: detecting a feedback analog signal; and converting the feedback analog signal into a feedback AD value. Wherein, the method further includes: obtaining the feedback AD value twice; if the difference between the feedback AD value obtained for the first time and the reference value is greater than or equal to the second preset difference, and the difference between the feedback AD value obtained for the first time and the reference value is If the difference between the feedback AD value and the feedback AD value obtained for the second time is greater than or equal to the third preset difference value, and the duration is less than or equal to the first preset time, it is determined that a card is currently approaching slowly. Wherein, the method includes: if the difference between the feedback AD value and the reference value is greater than or equal to the fourth preset difference, and the duration is less than or equal to the second preset time, then it is determined that a card is currently approaching quickly, and wakes up The system reads the card.

This application uses a low-power timer to wake up once every 300ms to detect the feedback AD value of the card to update the reference value for judging whether there is a card. Whether the card meets the characteristics of swiping the card close and slow approaching to judge whether the card is close, so that it can be updated at all times. In a card-less environment, the erroneous baseline value can be avoided without leaving the panel, and the card will respond quickly when the card is close, making the low-power detection card function stable and reliable.

Figure 2 is a schematic diagram of a smart lock device provided by an embodiment of this application. As shown in Figure 2, this application also provides a smart lock unlocking device. The device includes:

Detection module, used to obtain feedback AD value;

A judgment module configured to update the reference value according to the feedback AD value if the difference between the feedback AD value and the reference value is less than a first preset difference;

Wherein, the reference value is the feedback AD value tested when no card is close to the card.

Figure 2 is a schematic diagram of a smart lock device provided by an embodiment of this application. As shown in Figure 3, this application also provides a smart lock unlocking device. The device includes:

at least one processor;

At least one memory for storing at least one program;

The smart lock unlocking method as described in the previous embodiment is implemented when at least one of the programs is executed by at least one of the processors.

In addition, this application also provides a smart lock, which includes the smart lock circuit described in the previous embodiment.

Similarly, the contents in the above method embodiments are applicable to this device embodiment. The specific functions implemented by this device embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are the same as those achieved by the above method embodiments. Same thing too.

In some alternative embodiments, the functions/operations noted in the block diagrams may occur out of the order noted in the operational illustrations. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending on the functionality/operations involved. Furthermore, the embodiments presented and described in the flowcharts of this application are provided by way of example for the purpose of providing a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logical flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and in which sub-operations described as part of a larger operation are performed independently.

Furthermore, although the present application is described in the context of functional modules, it should be understood that, unless stated to the contrary, one or more of the functions and/or features may be integrated in a single physical device and/or software module , or one or more functions and/or features may be implemented in separate physical devices or software modules. It will also be understood that a detailed discussion regarding the actual implementation of each module is not necessary for understanding the present application. Rather, the actual implementation of the various functional modules in the apparatus disclosed herein will be within the ordinary skill of an engineer, taking into account the properties, functions and internal relationships of the modules. Therefore, a person skilled in the art using ordinary skills will be able to implement the application as set forth in the claims without undue experimentation. It will also be understood that the specific concepts disclosed are illustrative only and are not intended to limit the scope of the application, which is to be determined by the full scope of the appended claims and their equivalents.

Functions may be stored in a computer-readable storage medium when implemented in the form of software functional units and sold or used as independent products. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program code. .

The logic and/or steps represented in the flowcharts or otherwise described herein, for example, may be considered a sequenced list of executable instructions for implementing the logical functions, and may be embodied in any computer-readable medium, For use by, or in combination with, instruction execution systems, devices or devices (such as computer-based systems, systems including processors or other systems that can fetch instructions from and execute instructions from the instruction execution system, device or device) or equipment. For the purposes of this specification, a "computer-readable medium" may be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

It should be understood that various parts of the present application can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if it is implemented in hardware, as in another embodiment, it can be implemented by any one or a combination of the following technologies known in the art: a logic gate circuit with a logic gate circuit for implementing a logic function on a data signal. Discrete logic circuits, application specific integrated circuits with suitable combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), etc.

In the above description of this specification, reference to the description of the terms "one embodiment/example", "another embodiment/example" or "certain embodiments/examples" etc. is meant to be described in connection with the embodiment or example A specific feature, structure, material, or characteristic is included in at least one embodiment or example of this application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present application have been shown and described, those of ordinary skill in the art will understand that various changes, modifications, substitutions and modifications can be made to these embodiments without departing from the principles and purposes of the present application. The scope of the application is defined by the claims and their equivalents.

Above, the above embodiments are only used to illustrate the technical solution of the present application, but not to limit it. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still implement the above-mentioned implementations. The technical solutions described in the examples are modified, or some of the technical features are equivalently substituted; however, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions in the embodiments of the present application.

Claims (5)

1. The intelligent lock circuit is characterized by comprising a signal transmission processing circuit and a detection circuit,

the detection circuit comprises a first capacitor, a first resistor and a second resistor, wherein the first capacitor and the first resistor are connected in parallel, a first end of the first capacitor is connected with a main control pin, a second end of the first capacitor is grounded, a first end of the second resistor is connected with a first end of the first capacitor, and a second end of the second resistor is connected with the signal transmission processing circuit;

the signal transmission processing circuit comprises a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a diode;

the third capacitor, the fourth capacitor and the fifth capacitor are connected in parallel, the first end of the sixth capacitor is connected with the first end of the second capacitor, the second end of the sixth capacitor is connected with the first end of the third capacitor, the first end of the second capacitor is connected with the main control pin, the second ends of the second capacitor and the third capacitor are connected with the first end of the third resistor, and the second end of the third resistor is grounded; the fourth resistor is connected in parallel with the seventh capacitor, the first end of the fourth resistor is connected with the first end of the fifth resistor, the second end of the fifth resistor is connected with the first end of the eighth resistor and the first end of the ninth resistor, the second end of the ninth resistor is connected with the first end of the sixth resistor and the first end of the seventh resistor, the second end of the seventh resistor is connected with the first end of the eighth resistor and the second end of the tenth resistor, the first end of the tenth resistor is connected with the second end of the sixth resistor, the second ends of the fourth resistor, the eighth capacitor and the sixth resistor are all grounded, and the second end of the eighth resistor is connected with a power supply;

the first end of the seventh resistor is connected with the first radio frequency antenna connecting wire, and the second end of the seventh resistor is connected with the second radio frequency antenna connecting wire;

the second end of the sixth capacitor is connected with the positive electrode of the diode, and the negative electrode of the diode is connected with the first end of the fifth resistor;

the second end of the second resistor is connected with the first end of the eighth capacitor;

the circuit also comprises a main control module, wherein the main control module transmits radio frequency signals through the signal transmission processing circuit and the radio frequency antenna;

the main control module detects feedback analog signals through the detection circuit and the radio frequency antenna;

the main control module converts the feedback analog signal into a digital signal;

the intelligent lock circuit is used for:

acquiring a feedback AD value;

if the absolute value difference value between the feedback AD value and the reference value is smaller than a first preset difference value, updating the reference value according to the feedback AD value;

the reference value is a feedback AD value obtained by testing in a card-free approaching state;

the obtaining the feedback AD value further includes:

detecting a feedback analog signal;

the feedback analog signal is converted into a feedback AD value.

2. An intelligent lock unlocking method applied to the intelligent lock circuit as claimed in claim 1, comprising:

obtaining the feedback AD value twice;

if the difference value between the feedback AD value obtained for the first time and the reference value is larger than or equal to a second preset difference value, and the difference value between the feedback AD value obtained for the first time and the feedback AD value obtained for the second time is larger than or equal to a third preset difference value, and the duration time is smaller than or equal to the first preset time, judging that the card is approaching slowly at present.

3. The smart lock unlocking method according to claim 2, wherein the method comprises:

if the difference value between the feedback AD value and the reference value is larger than or equal to a fourth preset difference value and the duration time is smaller than or equal to a second preset time, the current card is judged to be fast approaching, and the system is awakened to read the card.

4. Intelligent lock unlocking device, its characterized in that, the device includes:

at least one processor;

at least one memory for storing at least one program;

a smart lock unlocking method according to any one of claims 2-3, when at least one of said programs is executed by at least one of said processors.

5. A smart lock, wherein the smart lock comprises the smart lock circuit of claim 1.