CN115424372A - Intelligent lock circuit, unlocking method and device and intelligent lock - Google Patents

Abstract

The application discloses an intelligent lock circuit, an unlocking method, an unlocking device and an intelligent lock, the feedback AD value of a card is detected through a signal sending processing circuit and a detection circuit, the reference value of whether the card exists is updated and judged, whether the card accords with the characteristics of card swiping approaching and slow approaching to judge whether the card approaches, so that the environment without the card can be updated constantly, the situation that the card does not leave a panel and the error reference value is updated can be avoided, the card approaches to a quick response, and the function of the low-power consumption detection card is stable and reliable.

Description

Smart lock circuit, unlocking method, device and smart lock

technical field

The application relates to the field of smart locks, especially smart lock circuits, unlocking methods, devices and smart locks.

Background technique

Proximity card (IC card) is a verification method for smart locks to open the door. When the smart lock system is dormant, it can only judge whether there is a card approaching the card swiping panel of the smart lock by detecting whether there is a card that needs to be verified, resulting in long response time and slow response speed, which reduces the user experience.

Therefore, the above-mentioned technical problems existing in the related art need to be solved urgently.

Contents of the invention

This application aims to solve one of the technical problems in the related art. To this end, the embodiments of the present application provide a smart lock circuit, an unlocking method, a device, and a smart lock, which can improve the unlocking efficiency of the smart lock.

According to one aspect of the embodiment of the present application, a smart lock circuit is provided, the circuit includes a signal transmission processing circuit, a detection circuit,

The detection circuit includes a first capacitor, a first resistor, and a second resistor, the first capacitor and the first resistor are connected in parallel, the first end of the first capacitor is connected to the main control pin, and the first The second end of the capacitor is grounded, the first end of the second resistor is connected to the first end of the first capacitor, and the second end of the second resistor is connected to the signal sending and processing circuit.

Wherein, the signal sending processing circuit includes a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a third resistor, a Four resistors, fifth resistors, sixth resistors, seventh resistors, eighth resistors and diodes;

The third capacitor, the fourth capacitor, and the fifth capacitor are connected in parallel, the first end of the sixth capacitor is connected to the first end of the second capacitor, and the second end of the sixth capacitor is connected to the first end of the sixth capacitor. The first end of the three capacitors is connected, the first end of the second capacitor is connected to the main control pin, and the second end of the second capacitor and the third capacitor are connected to the first end of the third resistor , the second end of the third resistor is grounded; the fourth resistor is connected in parallel with the seventh capacitor, the first end of the fourth resistor is connected to the first end of the fifth resistor, and the fifth resistor The second end is connected to the first end of the eighth capacitor and the first end of the ninth capacitor, and the second end of the ninth capacitor is connected to the first end of the sixth resistor and the first end of the seventh resistor. connected, the second end of the seventh resistor is connected to the first end of the eighth resistor and the second end of the tenth capacitor, the first end of the tenth capacitor is connected to the second end of the sixth resistor connected, the second ends of the fourth resistor, the eighth capacitor, and the sixth resistor are all grounded, and the second end of the eighth resistor is connected to the power supply;

The first end of the seventh resistor is connected to the first radio frequency antenna connection line, and the second end of the seventh resistance is connected to the second radio frequency antenna connection line;

The second end of the sixth capacitor is connected to the anode of the diode, and the cathode of the diode is connected to the first end of the fifth resistor. wherein, the second end of the second resistor is connected to the first end of the eighth capacitor.

Wherein, the circuit further includes a main control module, and the main control module transmits radio frequency signals through the signal transmission processing circuit and the radio frequency antenna;

The main control module detects and feeds back an analog signal through the detection circuit and the radio frequency antenna;

The main control module converts the feedback analog signal into a digital signal.

According to one aspect of the embodiment of the present application, a smart lock unlocking method is provided, which is applied to the smart lock circuit described in the previous embodiment, and the method includes:

Get feedback AD value;

If the absolute value difference between the feedback AD value and the reference value is less than a first preset difference, updating the reference value according to the feedback AD value;

Wherein, the reference value is a feedback AD value obtained from a test in a state where no card is approaching.

Wherein, said acquiring the feedback AD value also includes:

Detect feedback analog signal;

Converting the feedback analog signal into a feedback AD value.

Wherein, the method also includes:

Obtain the feedback AD value twice;

If the difference between the feedback AD value obtained for the first time and the reference value is greater than or equal to the second preset difference, and the difference between the feedback AD value obtained for the first time and the feedback AD value obtained for the second time If the difference is greater than or equal to the third preset difference and the duration is less than or equal to the first preset time, it is determined that there is a card approaching slowly.

Wherein, the method includes:

If the difference between the feedback AD value and the reference value is greater than or equal to the fourth preset difference, and the duration is less than or equal to the second preset time, it is judged that there is a card approaching rapidly at present, and the system is awakened to read the card.

According to one aspect of the embodiment of the present application, a smart lock unlocking device is provided, and the device includes:

at least one processor;

at least one memory for storing at least one program;

When at least one of the programs is executed by at least one of the processors, the method for unlocking the smart lock as described in the previous embodiments is realized.

According to one aspect of an embodiment of the present application, a smart lock is provided, and the smart lock includes the smart lock circuit as described in the foregoing embodiments.

The beneficial effects of the smart lock circuit, unlocking method, device and smart lock provided by the embodiment of the present application are: the present application detects the feedback AD value of the card through the radio frequency circuit, the detection circuit and the transmitting circuit, and updates the reference value for judging whether there is a card , whether the card meets the characteristics of swiping card approaching and slow approaching to judge whether there is a card approaching, so that the environment without cards can be updated at all times, and when the card does not leave the panel, it can avoid updating the wrong reference value. The function of the power consumption detection card is stable and reliable.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

Fig. 1 is the circuit diagram of the intelligent lock circuit that the embodiment of the present application provides;

Fig. 2 is a schematic diagram of the smart lock device provided by the embodiment of the present application;

Fig. 3 is a schematic diagram of another smart lock device provided by an embodiment of the present application.

Detailed ways

In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiment of the application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the application. Obviously, the described embodiment is only It is an embodiment of a part of the application, but not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the scope of protection of this application.

The terms "first", "second", "third" and "fourth" in the specification, claims and drawings of the present application are used to distinguish different objects, rather than to describe a specific order. Furthermore, the terms "include" and "have", as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally further includes For other steps or units inherent in these processes, methods, products or apparatuses.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The occurrences of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is understood explicitly and implicitly by those skilled in the art that the embodiments described herein can be combined with other embodiments.

Proximity card (IC card) is a verification method for smart locks to open the door. When the smart lock system is dormant, it can only judge whether there is a card approaching the card swiping panel of the smart lock by detecting whether there is a card that needs to be verified, resulting in long response time and slow response speed, which reduces the user experience.

In order to solve the above problems, the present application proposes an intelligent lock circuit, an unlocking method, a device and an intelligent lock.

In this embodiment, when the smart lock system is dormant, it can only be judged whether there is a card close to the card swiping panel of the smart lock by detecting whether there is a card close to the card that needs to be verified, so that the function of low power consumption detection card can be achieved; low power consumption The card detection function is to detect the AD value of the feedback voltage of the antenna by sending the radio frequency (RFID enabled) to the card swiping circuit and the antenna to judge whether there is a card approaching. , The characteristics of fast card approach and card slow approach are used to implement the card approach algorithm, so as to achieve the purpose of waking up the system when the card is approaching and preventing the wake-up from being triggered by swiping the card by mistake.

Figure 1 legend: R47-first resistor, R48-second resistor, R55-third resistor, R51-fourth resistor, R49-fifth resistor, R52-sixth resistor, R53-seventh resistor, R56-eighth Resistor, C11-first capacitor, C17-second capacitor, C18-third capacitor, C19-fourth capacitor, C20-fifth capacitor, C13-sixth capacitor, C21-seventh capacitor, C22-eighth capacitor, C14-the ninth capacitor, C23-the tenth capacitor.

Specifically, Fig. 1 is a circuit diagram of the smart lock circuit provided by the embodiment of the present application. As shown in Fig. 1, the smart lock circuit proposed by the present application includes a radio frequency circuit, a detection circuit and a transmission circuit, and the circuit includes a signal transmission processing circuit, A detection circuit, the detection circuit includes a first capacitor, a first resistor, and a second resistor, the first capacitor and the first resistor are connected in parallel, and the first end of the first capacitor is connected to the main control pin, so The second end of the first capacitor is grounded, the first end of the second resistor is connected to the first end of the first capacitor, and the second end of the second resistor is connected to the signal sending and processing circuit.

Wherein, the signal sending processing circuit includes a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a third resistor, a Four resistors, the fifth resistor, the sixth resistor, the seventh resistor, the eighth resistor and a diode; the third capacitor, the fourth capacitor, and the fifth capacitor are connected in parallel, and the first terminal of the sixth capacitor is connected to the first terminal of the first capacitor. The first end of the second capacitor is connected, the second end of the sixth capacitor is connected to the first end of the third capacitor, the first end of the second capacitor is connected to the main control pin, and the first end of the sixth capacitor is connected to the main control pin. The second end of the second capacitor and the third capacitor are connected to the first end of the third resistor, and the second end of the third resistor is grounded; the fourth resistor is connected in parallel with the seventh capacitor, and the fourth resistor is connected in parallel with the seventh capacitor. The first end of the resistor is connected to the first end of the fifth resistor, the second end of the fifth resistor is connected to the first end of the eighth capacitor and the first end of the ninth capacitor, and the first end of the ninth capacitor The second terminal is connected to the first terminal of the sixth resistor and the first terminal of the seventh resistor, and the second terminal of the seventh resistor is connected to the first terminal of the eighth resistor and the second terminal of the tenth capacitor. connected, the first terminal of the tenth capacitor is connected to the second terminal of the sixth resistor, the second terminals of the fourth resistor, the eighth capacitor and the sixth resistor are all grounded, and the first terminal of the eighth resistor The two ends are connected to the power supply; the first end of the seventh resistor is connected to the first radio frequency antenna connection line, and the second end of the seventh resistance is connected to the second radio frequency antenna connection line; the second end of the sixth capacitor The terminal is connected to the anode of the diode, and the cathode of the diode is connected to the first end of the fifth resistor. wherein, the second end of the second resistor is connected to the first end of the eighth capacitor.

Wherein, the circuit further includes a main control module, the main control module transmits a radio frequency signal through the signal transmission processing circuit and the radio frequency antenna; the main control module detects and feeds back an analog signal through the detection circuit and the radio frequency antenna; The main control module converts the feedback analog signal into a digital signal.

It should be noted that the detection card circuit diagram and the feedback voltage AD value: send a 13.6M radio frequency signal to the circuit through RF_TXP, send it out through the antenna connected to CMP_INP and CMP_INN, and then use RF_ADC to detect the feedback AD value of the antenna; usually when no card is close , the AD value of the voltage detected by RF_ADC is M units, if the card is fast (approaching time is less than 300ms) the AD value of approaching is N units, if the card is slow (approaching time is greater than twice 300ms) the AD value of approaching Divided into two tests for P and Q units respectively.

Based on the smart lock unlocking circuit proposed in the above embodiment, this embodiment provides three unlocking situations, including:

(1) No card approaching detection algorithm:

The detection method when no card is approaching includes: obtaining the feedback AD value detected by the detection circuit; if the absolute value difference between the feedback AD value and the reference value is less than a first preset difference, then updating the A reference value; wherein, the reference value is a feedback AD value obtained by testing in a state where no card is approaching. Specifically, when no card approach is detected after power-on for the first time, the M value of no card approach is taken as the reference value D. At this time, M is equal to D. When no card approaches next time, the M value of no card approach detection If the absolute value difference between the value and the reference value D is less than 60 units, use M to update the reference value D of no card approach; on the contrary, if the absolute value difference between the value currently detected by M and the reference value D is greater than 60 units, then keep The reference value D remains unchanged (does not need to be updated). If the card does not leave the panel all the time, and the detected values are all values greater than plus or minus 60 units, the reference value will not be updated. The feedback AD value expression of the present embodiment is:

if(M>D-60&&M<D+60), D＝M

Among them, M is the voltage AD value detected by RF_ADC, and D is the reference value of no card approaching.

(2) Fast card approach detection algorithm

The detection method of fast card approaching includes: if the difference between the feedback AD value and the reference value is greater than or equal to the fourth preset difference, and the duration is less than or equal to the preset time, then it is judged that there is a card approaching quickly, and the system is woken up read card. Specifically, if the card is close to the card swiping panel for less than 300ms, the feedback AD value N is more than 800 units smaller than the reference value, and it is immediately judged that there is a card swiping close, and the card is read after waking up the system. The feedback AD value expression of the present embodiment is:

if(N<D-800)

(3) Slow card approach detection algorithm

The method for detecting the approach of the slow card includes: acquiring the feedback AD value twice; if the difference between the feedback AD value acquired for the first time and the reference value is greater than or equal to the second preset difference, and If the difference between the feedback AD value obtained for the second time and the feedback AD value acquired for the second time is greater than or equal to a third preset difference value, then it is determined that there is a card approaching slowly. Specifically, if the card is not more than 600ms when it is close to the card swiping panel, then the AD value P and Q units detected are divided into two times, wherein the first time P is more than 100 units less than the reference value D, and the second time Q is lower than the reference value D. P is smaller than 100 units. The feedback AD value expression of the present embodiment is:

if(P<D-100&&Q<P-100)

Wherein, P is the voltage AD value detected for the first time, and Q is the voltage AD value detected for the second time.

According to one aspect of the embodiment of the present application, a smart lock unlocking method is provided, which is applied to the smart lock circuit described in the previous embodiment. The method includes: obtaining the feedback AD value; if the absolute value difference between the feedback AD value and the reference value If the difference is smaller than the first preset difference, the reference value is updated according to the feedback AD value; wherein, the reference value is a feedback AD value obtained from a test in a state where no card is approaching. Wherein, said acquiring the feedback AD value further includes: detecting a feedback analog signal; converting the feedback analog signal into a feedback AD value. Wherein, the method further includes: acquiring the feedback AD value twice; if the difference between the feedback AD value acquired for the first time and the reference value is greater than or equal to the second preset difference, and the first acquired If the difference between the feedback AD value and the feedback AD value obtained for the second time is greater than or equal to a third preset difference, and the duration is less than or equal to a first preset time, it is determined that there is a card approaching slowly. Wherein, the method includes: if the difference between the feedback AD value and the reference value is greater than or equal to the fourth preset difference, and the duration is less than or equal to the second preset time, then judging that there is currently a card approaching rapidly, and waking up The system reads the card.

This application wakes up the low-power timer once every 300ms to detect the feedback AD value of the card to update the reference value for judging whether there is a card, and whether the card meets the characteristics of card swiping approach and slow approach to judge whether there is a card approaching, so that it can be updated all the time In the environment without cards, it can avoid updating the wrong reference value without leaving the panel, and the card can respond quickly when it is close, so that the function of the low-power detection card is stable and reliable.

Figure 2 is a schematic diagram of the smart lock device provided by the embodiment of the present application. As shown in Figure 2, the present application also provides a smart lock unlocking device. The device includes:

A detection module, configured to obtain a feedback AD value;

A judging module, configured to update the reference value according to the feedback AD value if the difference between the feedback AD value and the reference value is less than a first preset difference;

Wherein, the reference value is a feedback AD value obtained from a test in a state where no card is approaching.

Figure 2 is a schematic diagram of the smart lock device provided by the embodiment of the present application. As shown in Figure 3, the present application also provides a smart lock unlocking device. The device includes:

at least one processor;

at least one memory for storing at least one program;

When at least one of the programs is executed by at least one of the processors, the method for unlocking the smart lock as described in the previous embodiments is realized.

In addition, the present application also provides a smart lock, which includes the smart lock circuit as described in the previous embodiments.

Similarly, the content in the above-mentioned method embodiment is applicable to this device embodiment. The functions realized by this device embodiment are the same as those of the above-mentioned method embodiment, and the beneficial effects achieved are the same as those achieved by the above-mentioned method embodiment. Also the same.

In some alternative implementations, the functions/operations noted in the block diagrams may occur out of the order noted in the operational diagrams. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/operations involved. Furthermore, the embodiments presented and described in the flowcharts of this application are provided by way of example for the purpose of providing a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logical flow presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and in which sub-operations described as part of larger operations are performed independently.

Furthermore, although the present application has been described in the context of functional modules, it should be understood that one or more of the functions and/or features may be integrated into a single physical device and/or software module unless stated to the contrary. or one or more functions and/or features may be implemented in separate physical devices or software modules. It will also be appreciated that a detailed discussion of the actual implementation of each module is not necessary to understand this application. Rather, given the attributes, functions and internal relationships of the various functional blocks in the devices disclosed herein, the actual implementation of the blocks will be within the ordinary skill of the engineer. Accordingly, one skilled in the art using ordinary techniques can implement the present application set forth in the claims without undue experimentation. It is also to be understood that the particular concepts disclosed are illustrative only and are not intended to limit the scope of the application which is to be determined by the appended claims and their full scope of equivalents.

If the functions are realized in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes. .

The logic and/or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium, For use with instruction execution systems, devices, or devices (such as computer-based systems, systems including processors, or other systems that can fetch instructions from instruction execution systems, devices, or devices and execute instructions), or in conjunction with these instruction execution systems, devices or equipment for use. For the purposes of this specification, a "computer-readable medium" may be any device that can contain, store, communicate, propagate or transmit a program for use in or in conjunction with an instruction execution system, device or device.

It should be understood that each part of the present application may be realized by hardware, software, firmware or a combination thereof. In the embodiments described above, various steps or methods may be implemented by software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one or combination of the following techniques known in the art: Discrete logic circuits, ASICs with suitable combinational logic gates, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

In the above description of this specification, the description with reference to the terms "one embodiment/example", "another embodiment/example" or "some embodiments/example" means that the description is described in conjunction with the embodiment or example. A specific feature, structure, material, or characteristic is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present application have been shown and described, those skilled in the art can understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principle and spirit of the present application. The scope of the application is defined by the claims and their equivalents.

Above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be applied to the foregoing embodiments The technical solutions described in the examples are modified, or some of the technical features are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the application.

Claims (10)

1. The intelligent lock circuit is characterized in that the circuit comprises a signal sending processing circuit and a detection circuit,

the detection circuit comprises a first capacitor, a first resistor and a second resistor, the first capacitor is connected with the first resistor in parallel, the first end of the first capacitor is connected with the master control pin, the second end of the first capacitor is grounded, the first end of the second resistor is connected with the first end of the first capacitor, and the second end of the second resistor is connected with the signal sending processing circuit.

2. The intelligent lock circuit according to claim 1, wherein the signal transmission processing circuit comprises a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a diode;

the third capacitor, the fourth capacitor and the fifth capacitor are connected in parallel, a first end of the sixth capacitor is connected with a first end of the second capacitor, a second end of the sixth capacitor is connected with a first end of the third capacitor, a first end of the second capacitor is connected with the main control pin, second ends of the second capacitor and the third capacitor are connected with a first end of the third resistor, and a second end of the third resistor is grounded; the fourth resistor and the seventh capacitor are connected in parallel, a first end of the fourth resistor is connected with a first end of a fifth resistor, a second end of the fifth resistor is connected with a first end of an eighth capacitor and a first end of a ninth capacitor, a second end of the ninth capacitor is connected with a first end of a sixth resistor and a first end of a seventh resistor, a second end of the seventh resistor is connected with a first end of the eighth resistor and a second end of a tenth capacitor, a first end of the tenth capacitor is connected with a second end of the sixth resistor, second ends of the fourth resistor, the eighth capacitor and the sixth resistor are all grounded, and a second end of the eighth resistor is connected with a power supply;

the first end of the seventh resistor is connected with the first radio frequency antenna connecting line, and the second end of the seventh resistor is connected with the second radio frequency antenna connecting line;

and the second end of the sixth capacitor is connected with the anode of the diode, and the cathode of the diode is connected with the first end of the fifth resistor.

3. A smart lock circuit as claimed in claim 2, wherein the second terminal of the second resistor is connected to the first terminal of the eighth capacitor.

4. The intelligent lock circuit of claim 1, further comprising a master control module, wherein the master control module transmits radio frequency signals through the signal transmission processing circuit and the radio frequency antenna;

the main control module detects a feedback analog signal through the detection circuit and the radio frequency antenna;

and the main control module converts the feedback analog signal into a digital signal.

5. The intelligent lock unlocking method is applied to the intelligent lock circuit of claim 1, and comprises the following steps:

obtaining a feedback AD value;

if the absolute value difference value between the feedback AD value and the reference value is smaller than a first preset difference value, updating the reference value according to the feedback AD value;

and the reference value is a feedback AD value obtained by testing in a card-free approaching state.

6. The smart lock unlocking method according to claim 5, wherein the obtaining of the feedback AD value further includes:

detecting a feedback analog signal;

and converting the feedback analog signal into a feedback AD value.

7. The smart lock unlocking method of claim 6, further comprising:

obtaining the feedback AD value twice;

and if the difference value between the feedback AD value obtained for the first time and the reference value is larger than or equal to a second preset difference value, the difference value between the feedback AD value obtained for the first time and the feedback AD value obtained for the second time is larger than or equal to a third preset difference value, and the duration time is smaller than or equal to a first preset time, judging that the card is slowly approaching at present.

8. The smart lock unlocking method according to claim 6, wherein the method includes:

and if the difference value between the feedback AD value and the reference value is greater than or equal to a fourth preset difference value and the duration time is less than or equal to a second preset time, judging that the current card is close to the system quickly, and awakening the system to read the card.

9. Intelligence lock unlocking device, its characterized in that, the device includes:

at least one processor;

at least one memory for storing at least one program;

the smart lock unlocking method according to any one of claims 5-8, when at least one of said programs is executed by at least one of said processors.

10. Smart lock, characterized in that it comprises a smart lock circuit according to any of claims 1-4.

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