CN115394911A - Lower electrode of resistance-change memory and preparation method - Google Patents

Abstract

The invention provides a lower electrode of a resistive random access memory and a preparation method thereof, wherein the preparation method comprises the following steps: carrying out planarization treatment on the surface of the bottom dielectric layer to expose all or part of the conductive material layer filled in the dielectric layer; performing back etching on the conductive material layer, and performing dry and/or wet cleaning to enable the surface height of the conductive material layer to be lower than that of the dielectric layer; reducing the conductive material layer exposed at the upper end of the dielectric layer, selectively growing a lower electrode layer on the surface of the conductive material layer, wherein the surface height of the lower electrode layer is not lower than that of the dielectric layer; after growing the resistance change layer and the upper electrode lamination on the upper part of the lower electrode layer, sequentially etching the obtained basic structure of the memory; and filling an intermetallic dielectric substance into the etched memory structure and carrying out planarization treatment to complete the preparation of the lower electrode of the resistive random access memory. The invention can simplify the preparation process of the resistance-variable memory and improve the preparation quality.

Description

Bottom electrode and preparation method of resistive variable memory

technical field

The invention relates to the technical field of semiconductor manufacturing, and more specifically, to a lower electrode of a resistive variable memory and a preparation method thereof.

Background technique

In the design process of RRAM (Resistive Random Access Memory), in order to obtain better performance (such as device reliability (Reliability) and stability (Stability), data retention characteristics (Retention), high uniformity, Leakage is small, etc.), the metal film of the bottom electrode (BE, Bottom Electrode) of RRAM must have a very flat surface, and the roughness threshold (Rmax, Maximum Roughness) is lower than 2nm to prevent the resistive switching layer (SL) on the metal film , Switching Layer) a series of problems such as short circuit and uneven Cell Performance due to uneven thickness.

At present, most of the existing RRAM structures are metal injection molding (MIM, Metal Injection Moulding) structures, and the upper and lower electrodes are metal plates. The traditional manufacturing process is generally: lower electrode metal layer deposition, and then photolithography/etching/cleaning and other steps to pattern the metal layer of the lower electrode, then deposit the resistive variable layer and the metal layer of the upper electrode, and then perform masking and etching of the upper electrode to form an RRAM device. Such an existing RRAM structure cannot simultaneously meet the Rmax precision requirement on the upper surface of the metal film and the thickness requirement of the metal film.

The existing RRAM structure, its formation process mainly has the following two types:

The first type: roughly go through the following main process steps: sequentially form ReRAM and thin film stacks on the planarized BE VIA surface, form a ReRAM Cell Structure after photolithography, etching and cleaning, and then perform intermetallic dielectric filling and planarized to form the final device structure. The main difficulty and problem of this process lies in the etching process. In particular, during the process of etching the BE metal film, the metal film is very prone to backsputtering (Resputtering) and adheres to the Cell sidewall (Sidewall), resulting in problems such as A series of problems such as short circuits, residues, and defect states lead to device failure.

The second type: roughly go through the following main process steps: Compared with the first type, Spacer and SpacerEtch are added in order to prevent the influence of BE metal film Resputtering on the sidewall, specifically: Form a ReRAM film sequentially on the planarized BE VIA surface Lamination, photolithography and etching cleaning (Step 4) and other steps, especially, in the etching and cleaning step, the Endpoint stops on the BE metal film, and then the Dielectric Spacer space isolation layer is formed, and the BE W etching is performed , In this way, not only the probability of Resputter of the metal film is reduced, even if splashback occurs, it will not affect the device performance of ReRAM Cell, and finally the intermetal dielectric filling and planarization are performed to form the final device structure. The process steps are relatively complicated and lengthy, and the main difficulty and problem lies in the Spacer Etch&Wet Clean process. During the etching of the BE metal film and the subsequent cleaning process, the bottom of the Cell is prone to undercutting, which leads to problems such as ReRAM Film Damage&Loss , Undesired Profile, Cell Missing and a series of problems lead to device failure.

In order to solve the above technical problems, there is an urgent need for a method that can not only ensure that the Rmax on the upper surface of the BE metal film of RRAM meets the requirements, but also reduce the difficulty of the ReRAM etching process and its impact on the Cell Sidewall (groove sidewall), and at the same time effectively control method of the lower electrode size.

Contents of the invention

In view of the above problems, the purpose of the present invention is to provide a lower electrode and a preparation method of a resistive variable memory, so as to solve the complicated and lengthy preparation process of the existing resistive variable memory, easy side digging at the bottom of the device, short circuit, residues, defect states, etc., which can easily lead to problems such as device failure.

The method for preparing the lower electrode of the resistive variable memory provided by the present invention includes: performing planarization treatment on the surface of the bottom dielectric layer, so that all or part of the conductive material layer filled in the dielectric layer is exposed; Etching, and dry and/or wet cleaning, so that the surface height of the conductive material layer is lower than the surface of the dielectric layer; reduction treatment is performed on the conductive material layer exposed on the upper end of the dielectric layer. The lower electrode layer is selectively grown on the surface, and the surface height of the lower electrode layer is not lower than the surface height of the dielectric layer; after growing the resistive switch layer and the upper electrode stack on the upper part of the lower electrode layer, the obtained memory basic structure is sequentially Etching treatment: performing intermetallic dielectric filling and planarization treatment on the etched memory structure to complete the preparation of the lower electrode of the resistive variable memory.

In addition, an optional technical solution is that at least one electrode through hole is provided on the dielectric layer; the conductive material layer is filled in the electrode through hole, and all or part of the structure of the conductive material layer is exposed through the electrode through hole.

In addition, an optional technical solution is that the material of the conductive material layer is at least any one of Cu, W, Al, Co, Ru, Au, Ta, Ti, TaN, and TiN.

In addition, an optional technical solution is to planarize the surface of the lower electrode layer after selectively growing the lower electrode layer on the surface of the conductive material layer.

In addition, an optional technical solution is to sequentially perform etching on the obtained memory basic structure, including: the etching end point of the memory basic structure stays on the surface of the resistive layer.

In addition, an optional technical solution is to sequentially perform etching on the obtained memory basic structure, including: the etching end point of the memory basic structure stays on the upper surface of the dielectric layer.

In addition, an optional technical solution is that a metal wiring layer is provided at the bottom of the electrode through hole; an electrode etching stop layer is provided between the metal wiring layer and the bottom of the conductive material layer; and the electrode etching stop layer The height is not lower than the height of the metal wiring layer.

In addition, an optional technical solution is to sequentially perform etching on the obtained memory basic structure, including: the etching end point of the memory basic structure stays at the electrode etching stop layer.

In addition, an optional technical solution is that the materials of the intermetallic dielectric, the resistive switch layer, the dielectric layer, the metal wiring layer, and the electrode etching stop layer are the same or different.

According to another aspect of the present invention, a lower electrode of a resistive variable memory is provided, which is prepared by using the method for preparing the lower electrode of a resistive variable memory.

Utilizing the lower electrode of the above-mentioned resistive variable memory and its preparation method, self-alignment (Self-alignment) of the contact between the lower electrode and the conductive material layer can be realized, which not only effectively reduces the size of the lower electrode, but also expands the distance between the upper and lower electrodes. Optically align the window (Alignment&Overlay), so that the setting density of the resistive variable memory is effectively improved; in addition, the thickness of the film of the lower electrode layer and the roughness of the surface (especially the upper surface in contact with the resistive variable layer) can be effectively controlled Threshold, improve the uniformity and consistency of the surface; at the same time, the lower electrode layer is tightly wrapped and covered by the dielectric layer, so that it will not be damaged by etching and/or cleaning steps, and the overall yield rate is improved.

To the accomplishment of the above and related ends, one or more aspects of the invention include the features hereinafter described in detail. The following description and accompanying drawings detail certain exemplary aspects of the invention. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Furthermore, the invention is intended to include all such aspects and their equivalents.

Description of drawings

Other objects and results of the present invention will become clearer and easier to understand by referring to the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present invention. In the attached picture:

1 is a flowchart of a method for preparing a lower electrode of a resistive variable memory according to an embodiment of the present invention;

FIG. 2 is a detailed flowchart of a method for preparing a lower electrode of a resistive variable memory according to an embodiment of the present invention.

The reference signs include: electrode through hole 1, dielectric layer 2, conductive material layer 3, lower electrode layer 4, resistive layer 5, upper electrode stack 6, electrode etching stop layer 7, metal wiring layer 8 .

The same reference numerals indicate similar or corresponding features or functions throughout the drawings.

Detailed ways

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. It may be evident, however, that these embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more embodiments.

In describing the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " Back", "Left", "Right", "Vertical", "Horizontal", "Top", "Bottom", "Inner", "Outer", "Clockwise", "Counterclockwise", "Axial", The orientation or positional relationship indicated by "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying the referred device or element Must be in a particular orientation, be constructed in a particular orientation, and operate in a particular orientation, and therefore should not be construed as limiting the invention.

In order to describe in detail the lower electrode of the resistive variable memory of the present invention and the preparation method thereof, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

FIG. 1 and FIG. 2 respectively show a schematic flow and principle of a method for preparing a lower electrode of a resistive variable memory according to an embodiment of the present invention.

As shown in Fig. 1 and Fig. 2 together, the method for preparing the lower electrode of the resistive variable memory according to the embodiment of the present invention mainly includes the following steps:

S110: Perform planarization treatment on the surface of the bottom dielectric layer 2 to expose all or part of the conductive material layer 3 filled in the dielectric layer 2 .

Wherein, this step first planarizes the bottom electrode metal, that is, the surface of the dielectric layer 2, so that the conductive material filled in the dielectric layer 2 is completely or partially exposed; wherein, at least one electrode via can be arranged on the dielectric layer 2. hole 1, the cross-sectional shape of the electrode through hole 1 is a trapezoidal structure, and then the conductive material layer 3 is filled in the electrode through hole 1, and all or part of the structure of the conductive material layer 3 is exposed to the electrode through hole 1, so as to carry out subsequent lower electrode engraving. etch processing.

Further, the material of the conductive material layer 3 can be at least any one of Cu, W, Al, Co, Ru, Au, Ta, Ti, TaN, TiN, which can be flexibly selected according to the requirements of the processing technology or application scenarios. select.

S120 : Etching back the conductive material layer 3 , and dry and/or wet cleaning, so that the surface of the conductive material layer 3 is lower than the surface of the dielectric layer 2 .

Wherein, the conductive material layer 3 is subjected to etching back treatment, and dry and/or wet cleaning, so that the height of the conductive material layer 3 in the electrode through hole 1 is lower than the surface of the dielectric layer 2. The growth of the electrode layer 4 provides an escape space, which can effectively control the thickness of the lower electrode layer 4 and prevent it from being corroded or damaged in the later chemical treatment process.

S130: Perform reduction treatment on the conductive material layer 3 exposed on the upper end of the dielectric layer 2, selectively grow the lower electrode layer 4 on the surface of the conductive material layer 3, and the surface height of the lower electrode layer 4 is not lower than the dielectric layer 2 surface height.

Specifically, reduction treatment is performed on the conductive material layer 3 after etching and cleaning, and the lower electrode layer 4 is selectively grown on the surface of the conductive material layer 3, and the surface height of the lower electrode layer 4 is not lower than that of the dielectric layer 2. The height of the surface, that is, the height of the lower electrode layer 4 is equal to or slightly higher than the surface height of the dielectric layer 2, so as to facilitate the subsequent growth of the resistive switch layer 5 and the upper electrode stack 6.

Wherein, the grown lower electrode layer 4 , that is, the bottom electrode layer, may also be planarized to improve the surface uniformity of the lower electrode layer 4 .

S140: growing the resistive switch layer 5 and the stacked upper electrode 6 on the upper part of the lower electrode layer 4, and sequentially performing etching treatment on the obtained memory basic structure.

Specifically, the resistive switch layer 5 and the upper electrode stack 6 are grown on the upper part of the lower electrode layer 4, and then the structure is etched. The etching process includes: photolithography and etching. First, the After the growth of the resistive switch layer 5 and the upper electrode stack 6, the basic structure of the memory is subjected to photolithography treatment, and then to etching treatment, until the etching reaches a predetermined designated position.

S150: Filling and planarizing the etched memory structure with an intermetallic dielectric, so as to complete the preparation of the lower electrode of the resistive variable memory.

In a specific embodiment of the method for preparing the lower electrode of the variable memory according to the present invention, sequentially performing etching on the obtained memory basic structure may include: the etching end point of the memory basic structure stays on the surface of the resistive switch layer 5 .

In another embodiment, the etching process is performed sequentially on the obtained memory basic structure, including: the etching end point of the memory basic structure stays on the upper surface of the dielectric layer 2 .

In another embodiment, a metal wiring layer 8 is provided at the bottom of the electrode through hole 1; an electrode etching stop layer 7 is provided between the metal wiring layer 8 and the bottom of the conductive material layer 3; and, the electrode etching The height of the etch stop layer 7 is not lower than that of the metal wiring layer 8 .

Further, etching treatment is performed on the obtained memory basic structure in sequence, including: the etching end point of the memory basic structure stays at the electrode etching stop layer 7 .

It should be noted that the materials of the intermetallic dielectric, the resistive switch layer 5 , the dielectric layer 2 , the metal wiring layer 8 , and the electrode etching stop layer 7 may be the same or different materials.

As a specific example, the method for preparing the lower electrode of the resistive variable memory shown in FIG. 2 includes:

Step1: planarize the surface of the bottom dielectric layer 2, so that the conductive material layer 3 filled in the dielectric layer 2 is fully or partially exposed;

Step2: Etching back the conductive material layer 3, and dry and/or wet cleaning, so that the surface height of the conductive material layer 3 is lower than the surface of the dielectric layer 2;

Step3: Perform reduction treatment on the conductive material layer 3 exposed on the upper end of the dielectric layer 2, selectively grow the lower electrode layer 4 on the surface of the conductive material layer 3, and the surface height of the lower electrode layer 4 is not lower than the dielectric layer 2 surface height; then, grow a resistive switch layer 5 and an upper electrode stack 6 on the top of the lower electrode layer 4;

Step4: Perform photolithography processing on the obtained memory infrastructure;

Step5: Etch the obtained memory base structure, and etch to the preset specified position, such as the resistive layer 5, the dielectric layer 2 or the electrode etching stop layer 7; the specified position shown in the figure is resistive Layer 5.

Step6: Filling the etched memory structure with an intermetallic dielectric;

Step7: Planarize the filled intermetallic dielectric to complete the preparation of the lower electrode of the resistive memory.

Corresponding to the preparation method of the lower electrode of the resistive variable memory, the present invention also provides a lower electrode of the resistive variable memory.

Wherein, for the embodiment of the lower electrode of the resistive variable memory, reference may be made to the description in the embodiment of the preparation method of the lower electrode of the resistive variable memory, and details will not be repeated here.

According to the lower electrode of the resistive variable memory of the present invention and its preparation method, the lower electrode is selectively grown on the surface of the reduced conductive material layer by reducing the conductive material layer exposed in the through hole of the electrode Layer processing can realize the self-alignment of the contact between the lower electrode and the conductive material layer, which can not only effectively reduce the size of the lower electrode, but also expand the optical alignment window (Alignment&Overlay) between the upper and lower electrodes, so that the setting of the resistive variable memory The density is effectively improved; through the selective growth of the lower electrode layer, the thickness of the lower electrode layer and the surface roughness threshold can be effectively controlled, which improves the uniformity and consistency of the surface; at the same time, the lower electrode layer is in During the preparation process, the gap is tightly wrapped and covered by the dielectric layer within the height difference between it and the dielectric layer, so that it will not be damaged by etching and/or cleaning steps, and the yield rate is improved.

The lower electrode of the resistive memory and the manufacturing method thereof according to the present invention are described above by way of example with reference to FIGS. 1 and 2 . However, those skilled in the art should understand that various improvements can be made without departing from the content of the present invention for the bottom electrode of the resistive variable memory and its preparation method proposed in the present invention. Therefore, the protection scope of the present invention should be determined by the contents of the appended claims.

Claims (10)

1. A preparation method of a lower electrode of a resistive random access memory is characterized by comprising the following steps:

carrying out planarization treatment on the surface of the bottom dielectric layer to expose all or part of the conductive material layer filled in the dielectric layer;

performing back etching on the conductive material layer, and performing dry and/or wet cleaning to enable the surface height of the conductive material layer to be lower than that of the dielectric layer;

reducing the conductive material layer exposed at the upper end of the dielectric layer, selectively growing a lower electrode layer on the surface of the conductive material layer, wherein the surface height of the lower electrode layer is not lower than that of the dielectric layer;

after growing a resistance change layer and an upper electrode lamination layer on the upper part of the lower electrode layer, sequentially etching the obtained memory basic structure;

and filling an intermetallic dielectric substance into the etched memory structure and carrying out planarization treatment to complete the preparation of the lower electrode of the resistive random access memory.

2. The method for preparing a lower electrode of a resistive random access memory according to claim 1,

at least one electrode through hole is arranged on the dielectric layer;

the conductive material layer is filled in the electrode through hole, and all or part of the structure of the conductive material layer is exposed out of the electrode through hole.

3. The method for preparing a lower electrode of a resistive random access memory according to claim 1,

the conductive material layer is made of at least one of Cu, W, al, co, ru, au, ta, ti, taN and TiN.

4. The method for preparing a lower electrode of a resistive random access memory according to claim 1,

and after selectively growing a lower electrode layer on the surface of the conductive material layer, carrying out planarization treatment on the surface of the lower electrode layer.

5. The method for preparing the lower electrode of the resistive random access memory according to claim 1, wherein the sequentially etching the obtained basic structure of the resistive random access memory comprises:

and the etching end point of the memory basic structure stays on the surface of the resistance change layer.

6. The method for preparing the lower electrode of the resistive random access memory according to claim 1, wherein the etching treatment is sequentially performed on the obtained basic structure of the resistive random access memory, and comprises the following steps:

the etch endpoint of the memory infrastructure resides on the upper surface of the dielectric layer.

7. The method for manufacturing a lower electrode of a resistive random access memory according to claim 2,

a metal connecting wire layer is arranged at the bottom of the electrode through hole;

an electrode etching stop layer is arranged between the metal connecting line layer and the bottom of the conductive material layer; and the number of the first and second electrodes,

and the height of the electrode etching stop layer is not less than that of the metal connecting line layer.

8. The method for preparing a lower electrode of a resistive random access memory according to claim 7,

the etching treatment is sequentially carried out on the obtained memory basic structure, and the method comprises the following steps:

and the etching end point of the memory basic structure stays at the electrode etching stopping layer.

9. The method for preparing a lower electrode of a resistive random access memory according to claim 7,

the materials of the intermetallic dielectric substance, the resistance change layer, the dielectric layer, the metal connecting line layer and the electrode etching stop layer are respectively the same or different.

10. A lower electrode of a resistive random access memory, characterized by being prepared by the method for preparing a lower electrode of a resistive random access memory according to any one of claims 1 to 9.

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