CN112447900A - Electrode assembly manufacturing method - Google Patents
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- CN112447900A CN112447900A CN201910830009.8A CN201910830009A CN112447900A CN 112447900 A CN112447900 A CN 112447900A CN 201910830009 A CN201910830009 A CN 201910830009A CN 112447900 A CN112447900 A CN 112447900A
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- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000000758 substrate Substances 0.000 claims abstract description 108
- 239000004020 conductor Substances 0.000 claims abstract description 79
- 238000009792 diffusion process Methods 0.000 claims abstract description 50
- 230000004888 barrier function Effects 0.000 claims abstract description 45
- 239000007772 electrode material Substances 0.000 claims abstract description 18
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 56
- 238000005530 etching Methods 0.000 claims description 19
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 9
- 238000005498 polishing Methods 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 238000000227 grinding Methods 0.000 claims description 2
- 229910052707 ruthenium Inorganic materials 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 55
- 239000010949 copper Substances 0.000 description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 12
- 239000003989 dielectric material Substances 0.000 description 11
- 239000002346 layers by function Substances 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/80—Constructional details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention provides a preparation method of an electrode assembly, which comprises the following steps: providing a substrate with a through hole, wherein the side wall of the through hole is provided with a diffusion barrier layer; filling a conductive material in the through hole, and controlling the upper surface of the conductive material to be lower than the upper surface of the substrate; depositing a bottom electrode material on the substrate and the conductive material to form a bottom electrode. The preparation method of the electrode assembly can enable the diffusion barrier layer and the bottom electrode to form a closed space, and the conductive material is closed in the closed space, so that the conductive material is prevented from diffusing to the substrate.
Description
Technical Field
The invention relates to the technical field of magnetic random access memories, in particular to a preparation method of an electrode assembly.
Background
In recent years, Magnetic Random Access Memory (MRAM) based on Magnetic Tunnel Junction (MTJ) magnetoresistive effect has attracted much attention due to its characteristics such as fast read/write speed, high erasable frequency, low power consumption, and the like, and is considered to be one of the most promising new memories in the future. The stacking of magnetic/non-magnetic thin films up to tens of layers thick, even around 1A, makes it very sensitive to the surface roughness and planarization of the bottom electrode, and thus providing a flat bottom electrode of MRAM is a critical step in the fabrication of MRAM devices, which directly affects the performance of the subsequent MTJ cells.
In the existing technology for manufacturing the bottom electrode of the magnetic tunnel junction, copper is generally used as a metal material for filling the conductive through hole, but the copper is easy to diffuse into an insulating medium around the through hole, so that the performance such as the stability of a device is degraded. And the magnetic tunnel junction unit has higher requirements on the flatness/roughness of the substrate. Therefore, in the existing magnetic tunnel junction manufacturing process, materials such as Ta/TaN/Ti/TiN are covered on the through hole to be used as bottom electrode materials, and the flatness of the magnetic tunnel junction substrate is improved while copper diffusion is blocked.
However, the thickness of the bottom electrode is difficult to grasp in the manufacturing process. Due to the whole process fluctuation, a certain over-etching amount is needed to ensure that all the magnetic tunnel junctions are etched, and when the bottom electrode is too thin, the copper at the top end of the conductive through hole is easily exposed, so that the later copper diffusion is caused. And when the bottom electrode is too thick, it may cause lithography alignment difficulties.
Disclosure of Invention
The electrode assembly preparation method provided by the invention can avoid copper diffusion under the condition of influencing the alignment precision.
The invention provides a preparation method of an electrode assembly, which comprises the following steps:
providing a substrate with a through hole, wherein the side wall of the through hole is provided with a diffusion barrier layer;
filling a conductive material in the through hole, and controlling the upper surface of the conductive material to be lower than the upper surface of the substrate;
depositing a bottom electrode material on the substrate and the conductive material to form a bottom electrode.
Optionally, after filling a conductive material in the through hole, planarizing the substrate and the conductive material;
during planarization, the conductive material is removed excessively so that the upper surface of the conductive material is lower than the upper surface of the substrate material.
Optionally, the planarization process is chemical mechanical polishing, and the conductive material is excessively removed by using the chemical mechanical polishing with different grinding rates for the conductive material and the substrate.
Optionally, after depositing the bottom electrode material, the method further includes:
and flattening the bottom electrode to remove the bottom electrode material formed on the upper surface of the substrate and make the upper surface of the bottom electrode coplanar with the substrate.
Optionally, after forming the bottom electrode, the method further includes:
and etching the bottom electrode to remove a bottom electrode material formed on the upper surface of the substrate and enable the upper surface of the bottom electrode to be higher than the upper surface of the substrate.
Optionally, before etching the bottom electrode, the method further includes: and flattening the bottom electrode to eliminate a conformal topological structure at the through hole corresponding to the bottom electrode.
Optionally, the distance between the upper surface of the conductive material and the upper surface of the substrate is not less than 100 angstroms.
Optionally, the conductive material includes one or a combination of Cu, W, or Al.
Optionally, the diffusion barrier layer comprises one or a combination of TaN, TiN, Ti, Co, and Ru or Ta.
Optionally, the substrate at least comprises a bottom diffusion barrier layer, a dielectric layer and a top diffusion barrier layer which are sequentially stacked from bottom to top.
In the electrode assembly manufacturing method of the present invention, at least a portion of the bottom electrode is formed in the through-hole. The sidewall in the through hole is provided with a diffusion barrier layer, and the top of the through hole is sealed by the bottom electrode, so that the conductive material in the bottom through hole is completely sealed, and the conductive material is not exposed or even diffused due to the planarization of the bottom electrode. Therefore, when the bottom electrode is formed, the upper surface of the substrate can be formed as thin as possible according to requirements, and the thinner bottom electrode is beneficial to alignment in photoetching.
Drawings
FIG. 1 is a schematic view showing an electrode assembly manufacturing method according to example 1 of the present invention after formation of a through-hole;
FIG. 2 is a schematic view showing the electrode assembly of example 1 after being filled with a conductive material according to the method of manufacturing the electrode assembly of the present invention;
FIG. 3 is a schematic view showing a bottom electrode formed and planarized in example 1 of a method for manufacturing an electrode assembly according to the present invention;
FIG. 4 is a schematic view showing the remaining layers formed in example 1 of the electrode assembly manufacturing method according to the present invention;
FIG. 5 is a schematic view showing the formation of the remaining layers by etching and the formation of the dielectric material protection in example 1 of the method for manufacturing an electrode assembly according to the present invention;
FIG. 6 is a schematic view showing an electrode assembly manufacturing method according to example 2 of the present invention after formation of a through-hole;
FIG. 7 is a schematic view showing the electrode assembly of example 2 according to the present invention after being filled with a conductive material;
FIG. 8 is a schematic view showing an electrode assembly manufacturing method of example 2 of the present invention after forming a bottom electrode and etching;
FIG. 9 is a schematic view showing the remaining layers formed in example 2 of the electrode assembly manufacturing method according to the present invention;
FIG. 10 is a schematic view of the formation and etching of the remaining layers and the formation of a dielectric material protection in example 2 of the method for manufacturing an electrode assembly according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
An embodiment of the present invention provides a method for manufacturing an electrode assembly, as shown in fig. 1 to 5, the method including:
s1: a substrate 3 is provided having a through hole with a diffusion barrier 4 on the sidewall of the through hole.
Step S1 specifically includes the following steps:
s11: providing a substrate 3;
s12: forming a through hole on the substrate 3 through photoetching and etching, wherein the through hole penetrates through the substrate 3;
s13: a diffusion barrier layer 4 is formed on the sidewalls of the via.
As an alternative embodiment of this step: the diffusion barrier layer 4 comprises one or a combination of several of TaN, TiN, Ti or Ta.
S2: and filling a conductive material 5 in the through hole, and controlling the upper surface of the conductive material 5 to be lower than the upper surface of the substrate 3.
As an alternative embodiment of this step: the conductive material 5 comprises one or a combination of more of copper, W or Al; as a preferred embodiment of this step: copper is used as the conductive material 5.
The step S2 includes the following steps:
filling a conductive material 5 in the through hole of the substrate 3, and flattening the substrate 3 and the conductive material 5; during the planarization process, the conductive material 5 is excessively removed so that the upper surface of the conductive material 5 is lower than the upper surface of the material of the substrate 3.
As an optional implementation manner of this step, a damascene process is adopted when the conductive material 5 is filled;
as an alternative embodiment of this step: the planarization process is chemical mechanical polishing, and excessive removal is performed on the conductive material 5 by utilizing the speed selection ratio of the polishing solution. In the chemical mechanical polishing process, a polishing solution with a high removal rate of the conductive material 5 and a low removal rate of the material of the substrate 3 is used.
As an alternative embodiment of this step: the distance between the upper surface of the conductive material 5 and the upper surface of the substrate 3 is not less than 100 angstroms.
S3: depositing electrode material on the substrate 3 and the conductive material 5 forms a bottom electrode 6.
Optionally, in this step, when forming the bottom electrode 6, it is ensured that the upper surface of the bottom electrode 6 corresponding to the through hole is higher than the upper surface of the substrate 3 or flush with the upper surface of the substrate 3, so as to facilitate the subsequent planarization process.
Alternatively, in this step, when the bottom electrode 6 is formed, the upper surface of the bottom electrode 6 corresponding to the through hole may be lower than the upper surface of the substrate 3, and in the subsequent planarization process, the upper portion of the substrate 3 is removed until the substrate 3 is coplanar with the upper surface of the bottom electrode 6 in the through hole.
The electrode assembly manufacturing method of the present embodiment forms at least a portion of the bottom electrode 6 in the through-hole. The sidewalls have a diffusion barrier 4 in the via and the top of the via is closed by the bottom electrode 6 so that the conductive material 5 in the bottom via is completely closed and does not expose or even diffuse the conductive material 5 due to the planarization of the bottom electrode 6. Thus, the bottom electrode 6 can be formed as thin as possible on the upper surface of the substrate 3 as required when forming the bottom electrode 6, and the thinner bottom electrode 6 facilitates alignment in photolithography.
Optionally, this embodiment further includes the following steps:
s4: the bottom electrode 6 is planarized to remove the material of the bottom electrode 6 formed on the top surface of the substrate 3 and to make the top surface of the bottom electrode 6 coplanar with the substrate 3.
In the step, redundant bottom electrode materials are removed in a flattening mode, so that the process flow can be simplified. After the bottom electrode 6 is deposited, the original process has a flattening process, and the redundant bottom electrode material is removed in the flattening process, so that the process has higher conformity with the original process and equipment do not need to be further processed. Thereby enabling implementation costs to be reduced.
After the bottom electrode 6 is planarized, the functional layer 8, the top electrode 9 and the dielectric material 10 may be deposited in sequence, and then the above layers are etched into a pattern and the dielectric material 10 is deposited again for protection.
Optionally, before step S1, the method further includes: the lower surface of the substrate 3 is in contact with the bottom medium 1; forming a seed through hole at the position of the bottom medium 1 corresponding to the through hole; the seed layer 2 is formed in the seed via hole.
As an optional implementation manner of this embodiment, the substrate includes at least a bottom diffusion barrier layer 31, a dielectric layer 32, and a top diffusion barrier layer 33, which are stacked in this order from bottom to top.
When the conductive material 5 and the substrate 6 are planarized, the top diffusion barrier layer 33 can be selected to be completely removed; alternatively, a portion of the top diffusion barrier layer 33 may be removed, leaving the top diffusion barrier layer 33 remaining.
In the process of flattening the bottom electrode and the substrate, if the substrate has the residual top diffusion barrier layer 33, the bottom electrode 6 can be flattened to the top diffusion barrier layer 33, and the flattening is stopped; optionally, planarization is continued to dielectric layer 32 to completely remove top diffusion barrier layer 33. If the substrate 3 does not have a top diffusion barrier layer 33 remaining, it may be planarized to the dielectric layer 32.
Example 2
An embodiment of the present invention provides a method for manufacturing an electrode assembly, as shown in fig. 6 to 10, the method including:
s1: a substrate 3 is provided having a through hole with a diffusion barrier 4 on the sidewall of the through hole.
Step S1 specifically includes the following steps:
s11: providing a substrate 3;
s12: forming a through hole on the substrate 3 through photoetching and etching, wherein the through hole penetrates through the substrate 3;
s13: a diffusion barrier layer 4 is formed on the sidewalls of the via.
As an alternative embodiment of this step: the diffusion barrier layer 4 comprises one or a combination of several of TaN, TiN, Ti or Ta.
S2: and filling a conductive material 5 in the through hole, and controlling the upper surface of the conductive material 5 to be lower than the upper surface of the substrate 3.
As an alternative embodiment of this step: the conductive material 5 comprises one or a combination of more of copper, W or Al; as a preferred embodiment of this step: copper is used as the conductive material 5.
The step S2 includes the following steps:
filling a conductive material 5 in the through hole, and flattening the substrate 3 and the conductive material 5; during the planarization process, the conductive material 5 is excessively removed so that the upper surface of the conductive material 5 is lower than the upper surface of the material of the substrate 3.
As an optional implementation manner of this step, a damascene process is adopted when the conductive material 5 is filled;
as an alternative embodiment of this step: the planarization process is chemical mechanical polishing, and excessive removal is performed on the conductive material 5 by utilizing the speed selection ratio of the polishing solution.
As an alternative embodiment of this step: the distance between the upper surface of the conductive material 5 and the upper surface of the substrate 3 is not less than 100 angstroms.
S3: depositing electrode material on the substrate 3 and the conductive material 5 forms a bottom electrode 6.
Optionally, in this step, when forming the bottom electrode 6, it is ensured that the upper surface of the bottom electrode 6 corresponding to the through hole is higher than the upper surface of the substrate 3, so as to facilitate the subsequent processes.
The electrode assembly manufacturing method of the present embodiment forms at least a portion of the bottom electrode 6 in the through-hole. The sidewalls have a diffusion barrier 4 in the via and the top of the via is closed by the bottom electrode 6 so that the conductive material 5 in the bottom via is completely closed and does not expose or even diffuse the conductive material 5 due to the planarization of the bottom electrode 6. Thus, the bottom electrode 6 can be formed as thin as possible on the upper surface of the substrate 3 as required when forming the bottom electrode 6, and the thinner bottom electrode 6 facilitates alignment in photolithography.
Optionally, this embodiment further includes the following steps:
s4: and etching the bottom electrode 6 to remove the material of the bottom electrode 6 formed on the upper surface of the substrate 3 and make the upper surface of the bottom electrode 6 higher than the upper surface of the substrate 3.
In the step, the redundant bottom electrode material is removed in an etching mode, the size of the bottom electrode can be flexibly controlled, and flexible adjustment can be carried out according to requirements, so that the quality of the final magnetic tunnel junction is improved.
As an alternative embodiment of this step: after the bottom electrode 6 is etched, depositing a dielectric material 10 around the bottom electrode 6, and planarizing the bottom electrode 6 and the dielectric material 10. Here, a dielectric material 10 is deposited around the bottom electrode 6
As an alternative embodiment of this step: a diffusion barrier layer 4 is also arranged on the upper surface of the substrate 3, and at this time, the upper surface of the bottom electrode 6 in the through hole needs to be controlled to be higher than the upper surface of the diffusion barrier layer 4, and after the bottom electrode 6 layer is deposited, the bottom electrode 6 is firstly flattened. And then, removing the bottom electrode 6 and the diffusion barrier layer 4 by utilizing photoetching and etching processes, and removing the diffusion barrier layer 4 on the upper surface of the substrate 3 in the etching process until the upper surface of the substrate 3 is exposed.
After the bottom electrode 6 is etched, an insulating medium 7 is deposited around the bottom electrode 6 and planarized, and then a functional layer 8, a top electrode 9 and a dielectric material 10 can be sequentially deposited, and then the above layers are etched into patterns and a dielectric material 10 is deposited again for protection.
Optionally, before step S1, the method further includes: the lower surface of the substrate 3 is in contact with the bottom medium 1; forming a seed through hole at the position of the bottom medium 1 corresponding to the through hole; the seed layer 2 is formed in the seed via hole.
As an optional implementation manner of this embodiment, the substrate includes at least a bottom diffusion barrier layer 31, a dielectric layer 32, and a top diffusion barrier layer 33, which are stacked in this order from bottom to top.
As an optional implementation manner of this embodiment, further comprising planarizing the conductive material 5 and the substrate 6, the top diffusion barrier layer 33 may be selectively removed completely; alternatively, a portion of the top diffusion barrier layer 33 may be removed, leaving the top diffusion barrier layer 33 remaining.
As an optional implementation manner of this embodiment, before etching the bottom electrode 6, the method further includes: and flattening the bottom electrode 6 to eliminate the conformal topology structure formed by the bottom electrode 6 at the position corresponding to the through hole.
In this embodiment, the bottom electrode 6 is etched before the functional layer 8 is not deposited, but it will be understood by those skilled in the art that: in this embodiment, the functional layer 8 may be etched together with the deposited functional layer 8; alternatively, the functional layer 8 and the top electrode 9 may be deposited and then etched together with the functional layer 8 and the top electrode 9.
Example 3
The embodiment of the invention provides a preparation method of an electrode assembly, which comprises the following steps:
s1: providing a substrate with a through hole, wherein the side wall of the through hole is provided with a diffusion barrier layer.
Step S1 specifically includes the following steps:
s11: providing a substrate;
s12: forming a through hole on the substrate through photoetching and etching, wherein the through hole penetrates through the substrate;
s13: and forming a diffusion barrier layer on the side wall of the through hole.
As an alternative embodiment of this step: the diffusion impervious layer comprises one or a combination of more of TaN, TiN, Ti or Ta.
S2: and filling a conductive material in the through hole, and controlling the upper surface of the conductive material to be lower than the upper surface of the substrate.
As an alternative embodiment of this step: the conductive material comprises one or a combination of more of copper, W or Al; as a preferred embodiment of this step: copper is used as the conductive material.
The step S2 includes the following steps:
and filling a conductive material in the through hole of the substrate, and controlling the upper surface of the conductive material to be lower than the upper surface of the substrate. After the conductive material is formed, the upper surface of the conductive material is planarized, and the upper surface of the substrate is also planarized. The planarization processes of the conductive material and the substrate are independent of each other, and the planarization processes are respectively carried out, so that the upper surface of the conductive material is lower than the upper surface of the substrate. The difference between this step and the two embodiments is as follows: in the step, the height difference between the conductive material and the substrate is formed when the conductive material is deposited, the height difference formed in the deposition process is easy to control the size, and theoretically, the height difference is about large, so that the effect of the embodiment is better.
As an optional implementation manner of the step, a damascene process is adopted when the conductive material is filled;
as an alternative embodiment of this step: the distance between the upper surface of the conductive material and the upper surface of the substrate is not less than 100 angstroms.
S3: depositing an electrode material on the substrate and the conductive material to form a bottom electrode.
Optionally, in this step, when forming the bottom electrode, it is ensured that the upper surface of the bottom electrode corresponding to the through hole is higher than or flush with the upper surface of the substrate, so as to facilitate the subsequent planarization process.
Optionally, in this step, when the bottom electrode is formed, the upper surface of the bottom electrode corresponding to the through hole may be lower than the upper surface of the substrate, and in a subsequent planarization process, the upper portion of the substrate is removed until the substrate is coplanar with the upper surface of the bottom electrode in the through hole.
Optionally, whether the top surface of the bottom electrode in the via in S3 is higher than the top surface of the substrate, lower than the top surface of the substrate, or even with the top surface of the substrate, the bottom electrode may be further processed by the following steps:
in the method of manufacturing an electrode assembly according to the present embodiment, at least a portion of the bottom electrode is formed in the through-hole. The sidewall in the through hole is provided with a diffusion barrier layer, and the top of the through hole is sealed by the bottom electrode, so that the conductive material in the bottom through hole is completely sealed, and the conductive material is not exposed or even diffused due to the planarization of the bottom electrode. Therefore, when the bottom electrode is formed, the upper surface of the substrate can be formed as thin as possible according to requirements, and the thinner bottom electrode is beneficial to alignment in photoetching.
S4: and flattening the bottom electrode to remove the bottom electrode material formed on the upper surface of the substrate and make the upper surface of the bottom electrode coplanar with the substrate.
As an alternative embodiment of this step: and a diffusion barrier layer is also arranged on the upper surface of the substrate, and the diffusion barrier layer on the upper surface of the substrate is removed together in the planarization process until the upper surface of the substrate is exposed, so that the planarization is stopped.
Optionally, when the upper surface of the bottom electrode in the through hole is higher than the upper surface of the substrate, the bottom electrode may be further processed by the following steps:
s4: and etching the bottom electrode to remove a bottom electrode material formed on the upper surface of the substrate and enable the upper surface of the bottom electrode to be higher than the upper surface of the substrate.
As an alternative embodiment of this step: and after the bottom electrode is etched, depositing an insulating medium around the bottom electrode, and flattening the bottom electrode and the medium material.
As an alternative embodiment of this step: and a diffusion barrier layer is also arranged on the upper surface of the substrate, the upper surface of the bottom electrode in the through hole is required to be controlled to be higher than the upper surface of the diffusion barrier layer, and the bottom electrode is firstly flattened after the bottom electrode layer is deposited. And then, removing the bottom electrode and the diffusion barrier layer by utilizing photoetching and etching processes, and removing the diffusion barrier layer on the upper surface of the substrate in the etching process until the upper surface of the substrate is exposed.
After the bottom electrode is flattened or etched, the functional layer, the top electrode and the dielectric material can be deposited in sequence, and then the layers are etched into a pattern and the dielectric material is deposited again for protection.
Optionally, before step S1, the method further includes: the lower surface of the substrate is in contact with a bottom medium; forming a seed through hole at the position of the bottom medium corresponding to the through hole; and forming a seed layer in the seed through hole.
The above is only a specific embodiment of the present invention: the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily made by those skilled in the art within the technical scope of the present invention will be covered by the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A method of making an electrode assembly, comprising: the method comprises the following steps:
providing a substrate with a through hole, wherein the side wall of the through hole is provided with a diffusion barrier layer;
filling a conductive material in the through hole, and controlling the upper surface of the conductive material to be lower than the upper surface of the substrate;
depositing a bottom electrode material on the substrate and the conductive material to form a bottom electrode.
2. The method for preparing an electrode assembly according to claim 1, wherein:
after filling a conductive material in the through hole, flattening the substrate and the conductive material;
during planarization, the conductive material is removed excessively so that the upper surface of the conductive material is lower than the upper surface of the substrate material.
3. The method for preparing an electrode assembly according to claim 2, wherein: the planarization process is chemical mechanical polishing, and the conductive material is excessively removed by utilizing the different grinding rates of the chemical mechanical polishing to the conductive material and the substrate.
4. The method for preparing an electrode assembly according to claim 1, wherein: after the bottom electrode material is deposited, the method further comprises the following steps:
and flattening the bottom electrode to remove the bottom electrode material formed on the upper surface of the substrate and make the upper surface of the bottom electrode coplanar with the substrate.
5. The method for preparing an electrode assembly according to claim 1, wherein: after the bottom electrode is formed, the method further comprises the following steps:
and etching the bottom electrode to remove a bottom electrode material formed on the upper surface of the substrate and enable the upper surface of the bottom electrode to be higher than the upper surface of the substrate.
6. The method for preparing an electrode assembly according to claim 5, wherein: before etching the bottom electrode, the method further comprises the following steps: and flattening the bottom electrode to eliminate a conformal topological structure at the through hole corresponding to the bottom electrode.
7. A method for preparing an electrode assembly according to any one of claims 1 to 3, wherein: the distance between the upper surface of the conductive material and the upper surface of the substrate is not less than 100 angstroms.
8. The method for preparing an electrode assembly according to claim 1, wherein: the conductive material comprises one or more of Cu, W or Al.
9. The method for preparing an electrode assembly according to claim 1, wherein: the diffusion impervious layer comprises one or a combination of more of TaN, TiN, Ti, Co and Ru or Ta.
10. The method for preparing an electrode assembly according to claim 1, wherein: the substrate at least comprises a bottom diffusion barrier layer, a dielectric layer and a top diffusion barrier layer which are sequentially stacked from bottom to top.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910830009.8A CN112447900A (en) | 2019-09-03 | 2019-09-03 | Electrode assembly manufacturing method |
| PCT/CN2020/098496 WO2021042834A1 (en) | 2019-09-03 | 2020-06-28 | Electrode assembly preparation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910830009.8A CN112447900A (en) | 2019-09-03 | 2019-09-03 | Electrode assembly manufacturing method |
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| CN112447900A true CN112447900A (en) | 2021-03-05 |
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| CN201910830009.8A Pending CN112447900A (en) | 2019-09-03 | 2019-09-03 | Electrode assembly manufacturing method |
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| WO2021042834A1 (en) | 2021-03-11 |
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