CN115361017A - Clock skew calibration circuit based on phase interpolator - Google Patents
Clock skew calibration circuit based on phase interpolator Download PDFInfo
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Abstract
The application discloses clock skew calibration circuit based on phase interpolator, it includes: a bias voltage generating circuit for generating leading phase and lagging phase control signals according to the output of the digital-to-analog conversion circuit; at least one stage of delay control circuit, each stage comprises a phase lead unit, a first delay unit, a phase lag unit, a second delay unit and a connection unit. The phase advancing unit receives an input clock signal and outputs a phase advancing clock signal to the connection unit according to the leading phase and the lagging phase control signal, the first delay unit receives the input clock signal and outputs a first delayed clock signal to the connection unit, and the connection unit outputs to the second delay unit and the next phase advancing unit and the first delay unit. The second delay unit receives the connection unit output and outputs a second delayed clock signal to the phase lag unit, receives the second delayed clock signal and outputs a phase lag clock signal to the connection unit based on the lead phase and the lag phase control signals.
Description
Technical Field
The present invention relates generally to the field of integrated circuit technology, and more particularly to a clock skew calibration circuit based on a phase interpolator.
Background
Time Interleaved (TI) analog-to-digital converters (ADCs) have been widely adopted in high-speed communication systems to achieve accurate data recovery with reasonable power consumption. The TI architecture takes advantage of the power efficient sub-ADCs by relaxing the operating speed of each channel, while their inherent channel mismatch (offset, gain, and skew) errors limit the overall ADC performance. Furthermore, as ADC conversion speeds reach above 50GHz, even in the most advanced process technologies, it is not possible to drive a single-phase high-frequency clock source as the sampling clock for each channel ADC. Therefore, recent ultra-high speed ADCs generate sampling phases from multiple master clock sources with different phases (i.e., differential phase or quadrature phase clock sources), which introduces significant skew errors in the TI ADCs.
Disclosure of Invention
The invention aims to provide a clock skew calibration circuit based on a phase interpolator, which is used for calibrating skew errors among a plurality of sampling clocks, has the advantages of easy design, low area cost and low power due to small parasitic quantity.
The application discloses clock skew calibration circuit based on phase interpolator includes:
a bias voltage generating circuit that generates a leading phase control signal and a lagging phase control signal from an output of the digital-to-analog converting circuit;
at least one stage of delay control circuitry, each stage of the delay control circuitry comprising: the phase delay unit is connected with the second delay unit in series and then connected with the phase advancing unit and the first delay unit in parallel; the phase advancing unit receives an input clock signal and outputs a phase advancing clock signal to the connection unit according to the advancing phase control signal and the lagging phase control signal, the first delay unit receives the input clock signal and outputs a first delayed clock signal to the connection unit, and the connection unit outputs to the second delay unit and the phase advancing unit and the first delay unit of the next stage delay control circuit; the second delay unit receives the output of the connection unit and outputs a second delayed clock signal to the phase lag unit, which receives the second delayed clock signal and outputs a phase lag clock signal to the connection unit based on the lead phase control signal and the lag phase control signal.
In a preferred embodiment, the phase advancing unit and the phase retarding unit each include: a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor; the grid electrode of the first PMOS transistor is connected to the leading phase control signal, the source electrode of the first PMOS transistor is connected to a power supply end, and the drain electrode of the first PMOS transistor is connected to the source electrode of the second PMOS transistor; the gate of the first NMOS transistor is connected to the hysteresis phase control signal, the source is connected to ground, and the drain is connected to the source of the second NMOS transistor; and the grid electrodes of the second PMOS transistor and the second NMOS transistor are connected to be used as a clock signal input end, and the drain electrodes of the second PMOS transistor and the second NMOS transistor are connected to be used as a clock signal output end.
In a preferred embodiment, the parameters of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor and the second NMOS transistor in the delay control circuit of each stage are different to obtain different phase-leading or phase-lagging clock signals.
In a preferred embodiment, the parameters include a channel width and a length of the transistor.
In a preferred example, the bias voltage generating circuit includes third to fifth PMOS transistors, third to fourth NMOS transistors, and first and second resistors, sources of the third to fifth PMOS transistors being connected to a power supply terminal, gates of the third PMOS transistor and the fourth PMOS transistor being connected to the digital-to-analog converting circuit, a drain of the fourth PMOS transistor outputting the lagging phase control signal and being connected to one end of the first resistor and gates of the third and fourth NMOS transistors, the other end of the first resistor being connected to a drain of the third NMOS transistor, a drain of the fifth PMOS transistor being connected to one end of the second resistor, and a gate of the fifth NMOS transistor being connected to the other end of the second resistor and a drain of the fourth NMOS transistor and outputting the leading phase control signal.
In a preferred embodiment, the first delay unit comprises an inverter, an input of which is connected to the input clock signal and an output of which is connected to the connection unit.
In a preferred embodiment, the second delay unit comprises an inverter, the input of which is connected to the connecting unit and the output of which is connected to the input of the phase lag unit.
The application also discloses a clock skew calibration circuit based on a phase interpolator, which comprises:
a bias voltage generating circuit that generates a leading phase control signal and a lagging phase control signal from an output of the digital-to-analog conversion circuit;
a plurality of clock delay control branches, each clock delay control branch having at least one stage of delay control circuit, each stage of the delay control circuit comprising: the phase delay unit is connected with the second delay unit in series and then connected with the phase advancing unit and the first delay unit in parallel; the phase lead unit receives one path of input clock signals in a plurality of paths of input clock signals and outputs phase lead clock signals to the connection unit according to the lead phase control signals and the lag phase control signals, the first delay unit receives the input clock signals and outputs first delay clock signals to the connection unit, and the connection unit outputs the second delay unit, the phase lead unit of the next stage of delay control circuit and the first delay unit; the second delay unit receives the output of the connection unit and outputs a second delayed clock signal to the phase lag unit, and the lag phase unit receives the second delayed clock signal and outputs a phase lag clock signal to the connection unit based on the lead phase control signal and the lag phase control signal.
In a preferred embodiment, the clock skew calibration circuit includes 12 clock delay control branches.
Compared with the prior art, the clock skew calibration circuit based on the connection unit has at least the following beneficial effects:
the application provides a novel delay control circuit based on phase interpolation. In a conventional delay cell, the delay is controlled by changing the driving capability (gm) or load (capacitance) of the delay cell. The circuit provided by the application consists of an N-bit current digital-to-analog conversion circuit (IDAC), a bias voltage generation circuit and a delay control circuit. IDACs can adjust the early phase (phase lead) path and late phase (phase lag) path output impedance by the bias voltage generation circuit changing the bias voltage so the output clock edges can be sharper or slower. Compared with other structures such as a trimming capacitor, the structure is easy to design, the area cost is low, and the power is low due to small parasitic. And the jitter contribution and power consumption of the calibration circuit module are dynamically adjusted according to the specific clock skew error magnitude, that is, when the minimum mismatch exists, the circuit provided by the application generates the minimum jitter and consumes the minimum current.
The present specification describes a number of technical features distributed throughout the various technical aspects, and if all possible combinations of technical features (i.e. technical aspects) of the present specification are listed, the description is made excessively long. In order to avoid this problem, the respective technical features disclosed in the above summary of the invention of the present application, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which should be regarded as having been described in the present specification) unless such a combination of the technical features is technically infeasible. For example, in one example, the feature a + B + C is disclosed, in another example, the feature a + B + D + E is disclosed, and the features C and D are equivalent technical means for the same purpose, and technically only one feature is used, but not simultaneously employed, and the feature E can be technically combined with the feature C, then the solution of a + B + C + D should not be considered as being described because the technology is not feasible, and the solution of a + B + C + E should be considered as being described.
Drawings
Fig. 1 is a schematic diagram of a delay control based on a phase interpolator in one embodiment of the present application.
FIG. 2 is a circuit diagram of phase interpolator based clock skew calibration in one embodiment of the present application.
Fig. 3 is a circuit diagram of a phase advancing unit and a phase retarding unit in one embodiment of the present application.
Fig. 4 is a circuit diagram of a bias voltage generating circuit in an embodiment of the present application.
FIG. 5 is a schematic diagram of the output of the clock skew calibration circuit as a function of the output current of the digital to analog conversion circuit in one embodiment of the present application.
Fig. 6 is a schematic diagram of the mismatch and jitter of several clock delay control branches in an embodiment of the present application.
Detailed Description
In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those of ordinary skill in the art that the claimed embodiments may be practiced without these specific details and with various changes and modifications based on the following embodiments.
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
FIG. 1 shows a schematic diagram of a delay control circuit based on a phase interpolator in one embodiment, including: phase advancing section 101, first delay section 102, phase delaying section 103, second delay section 104, and connection section 105, and phase advancing section 101, first delay section 102, phase delaying section 103, second delay section 104, and connection section 105 constitute a phase interpolator. The phase lag unit 103 is connected in series with the second delay unit 104 and then connected in parallel with the phase lead unit 101 and the first delay unit 102. The phase advancing unit 101 outputs a phase advancing clock signal to the connection unit 105, the first delay unit 102 receives the input clock signal and outputs a first delayed clock signal to the connection unit 105, and the connection unit 105 outputs to the second delay unit 104. The second delay unit 104 receives the output of the connection unit and outputs a second delayed clock signal to the phase lag unit 103, and the phase lag unit 103 receives the second delayed clock signal and outputs a phase lag clock signal to the connection unit 105. Connection section 105 receives signals input from phase advancing section 101, first delay section 102 and phase delaying section 103, mixes and connects the different input signals to generate a new output. The connection unit 105 may be physically implemented by a metal connection line.
IN one embodiment, the first delay unit 102 comprises an inverter having an input connected to the input clock signal IN and an output connected to the connection unit 105.
In one embodiment, the second delay unit 104 comprises an inverter having an input connected to the connection unit 105 and an output connected to an input of the phase lag unit 103.
FIG. 2 shows a circuit diagram of a phase interpolator based clock skew calibration circuit in one embodiment. The clock skew calibration circuit includes a bias voltage generation circuit 206, at least one stage of delay control circuit. The delay control circuit may be the circuit of fig. 1, with two stages of delay control circuits 208, 208' shown in fig. 2. The bias voltage generating circuit 206 generates a leading phase control signal BSP and a lagging phase control signal BSN according to an output BSIN of a digital-to-analog converting circuit (not shown). Each stage of the delay control circuit 208, 208' includes: phase advancing units 201,201', first delay units 202,202', phase retarding units 203,203', second delay units 204,204' and connection units. The phase lag units 203,203 are connected in series with the second delay units 204,204' and then in parallel with the phase lead units 201,201' and the first delay units 202,202 '. The phase advancing unit 201 receives an input clock signal IN and outputs a phase advancing clock signal to the connection unit according to the advancing phase control signal BSP and the lagging phase control signal BSN, the first delay unit 202 receives the input clock signal and outputs a first delayed clock signal to the connection unit, and the connection unit outputs to the second delay unit 203, and the phase advancing unit 201' and the first delay unit 202' of the next stage delay control circuit 208'. The second delay unit 203 receives the output of the connection unit and outputs a second delayed clock signal to the phase lag unit 204, and the phase lag unit 204 receives the second delayed clock signal and outputs a phase lag clock signal to the connection unit according to the leading phase control signal BSP and the lagging phase control signal BSN.
Fig. 3 shows a circuit diagram of a phase advancing unit and a phase retarding unit in one embodiment. The phase advancing unit and the phase retarding unit each include: a first PMOS transistor P1, a first NMOS transistor N1, a second PMOS transistor P2, and a second NMOS transistor N2. The first PMOS transistor P1 has a gate connected to the leading phase control signal BSP, a source connected to a power source terminal, and a drain connected to the source of the second PMOS transistor N2. The gate of the first NMOS transistor N1 is connected to the hysteresis phase control signal BSN, the source is connected to ground, and the drain is connected to the source of the second NMOS transistor N2. The gates of the second PMOS transistor P2 and the second NMOS transistor N2 are connected as a clock signal input terminal IN, and the drains of the second PMOS transistor P2 and the second NMOS transistor N2 are connected as a clock signal output terminal OUT.
In one embodiment, the parameters of the first PMOS transistor P1, the first NMOS transistor N1, the second PMOS transistor P2, and the second NMOS transistor N2 in the delay control circuit of each stage are different to obtain different phase-leading or phase-lagging clock signals. In one embodiment, the parameters include a channel width and a length of the transistor.
Fig. 4 shows a circuit diagram of a bias voltage generating circuit in one embodiment. The bias voltage generating circuit includes a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a third NMOS transistor N3, a fourth NMOS transistor N4, a first resistor R1, and a second resistor R2, sources of the third PMOS transistor P3, the fourth PMOS transistor P4, and the fifth PMOS transistor P5 are connected to a power supply terminal, gates of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected to the digital-to-analog conversion circuit, a drain of the fourth PMOS transistor P4 outputs the lagging phase control signal BSN and is connected to one end of the first resistor R1, a gate of the third NMOS transistor N3 and a gate of the fourth NMOS transistor N4, the other end of the first resistor R1 is connected to a drain of the third NMOS transistor N3, a drain of the fifth PMOS transistor N5 is connected to one end of the second resistor R2, and a gate of the fifth NMOS transistor N5 is connected to the other end of the second resistor bsr 2 and the drain of the fourth NMOS transistor N4 and outputs the leading phase control signal P.
The IDAC in this embodiment adjusts the output impedance of the earlier phase (phase lead) path and the later phase (phase lag) path by the bias voltage generation circuit changing the bias voltage, so the output clock edge can be sharper or slower. Fig. 5 illustrates the variation of the output OUT of the clock skew calibration circuit shown In fig. 2 with the output current BSIN of the digital to analog conversion circuit In one embodiment, where Ip is the phase lag control current and In is the phase lead control current.
In another embodiment of the present application, a clock skew calibration circuit based on a phase interpolator is further disclosed, which includes: the device comprises a bias voltage generating circuit and a plurality of clock delay control branches. In one embodiment, the clock skew calibration circuit includes 12 clock delay control branches. The bias voltage generating circuit generates a leading phase control signal and a lagging phase control signal based on an output of the digital-to-analog conversion circuit. Each clock delay control branch has at least one stage of delay control circuit, each stage of the delay control circuit including: the phase delay unit is connected with the second delay unit in series and then connected with the phase advancing unit and the first delay unit in parallel; the phase advance unit receives one path of input clock signals in a plurality of paths of input clock signals and outputs phase advance clock signals to the connection unit according to the advance phase control signals and the lag phase control signals, the first delay unit receives the input clock signals and outputs first delay clock signals to the connection unit, and the connection unit outputs the second delay unit, the phase advance unit of the next stage of delay control circuit and the first delay unit; the second delay unit receives the output of the connection unit and outputs a second delayed clock signal to the phase lag unit, and the lag phase unit receives the second delayed clock signal and outputs a phase lag clock signal to the connection unit based on the lead phase control signal and the lag phase control signal.
In this embodiment, one clock delay control branch may include the multi-stage delay control circuit shown in fig. 2, and several clock delay control branches share one bias voltage generation circuit 206 shown in fig. 2. It should be understood that several clock delay control branches may also employ a separate cheating paper voltage generation circuit. Fig. 6 shows a schematic diagram of mismatch and jitter (jitter) of several clock delay control branches in one embodiment. The jitter contribution and power consumption of the calibration circuit module are dynamically adjusted according to the specific clock skew error, and when small mismatch exists, the circuit provided by the application has the minimum jitter and the minimum power.
It should be noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2,2 and more than 2, more than 2 and more than 2.
All documents mentioned in this specification are to be considered as being incorporated in their entirety into the disclosure of the present application so as to be subject to modification as necessary. It should be understood that the above description is only a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the present disclosure should be included in the scope of protection of one or more embodiments of the present disclosure.
Claims (9)
1. A phase interpolator based clock skew calibration circuit, comprising:
a bias voltage generating circuit that generates a leading phase control signal and a lagging phase control signal from an output of the digital-to-analog converting circuit;
at least one stage of delay control circuitry, each stage of the delay control circuitry comprising: the phase delay unit is connected with the second delay unit in series and then connected with the phase advancing unit and the first delay unit in parallel; the phase advancing unit receives an input clock signal and outputs a phase advancing clock signal to the connection unit according to the advancing phase control signal and the lagging phase control signal, the first delay unit receives the input clock signal and outputs a first delayed clock signal to the connection unit, and the connection unit outputs to the second delay unit and the phase advancing unit and the first delay unit of the delay control circuit of the next stage; the second delay unit receives the output of the connection unit and outputs a second delayed clock signal to the phase lag unit, and the phase lag unit receives the second delayed clock signal and outputs a phase lag clock signal to the connection unit according to the lead phase control signal and the lag phase control signal.
2. The clock skew calibration circuit of claim 1, wherein the phase lead unit and the phase lag unit each comprise: a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor; the grid electrode of the first PMOS transistor is connected to the leading phase control signal, the source electrode of the first PMOS transistor is connected to a power supply end, and the drain electrode of the first PMOS transistor is connected to the source electrode of the second PMOS transistor; the gate of the first NMOS transistor is connected to the hysteresis phase control signal, the source is connected to ground, and the drain is connected to the source of the second NMOS transistor; and the grid electrodes of the second PMOS transistor and the second NMOS transistor are connected to be used as a clock signal input end, and the drain electrodes of the second PMOS transistor and the second NMOS transistor are connected to be used as a clock signal output end.
3. The clock skew calibration circuit of claim 1, wherein the parameters are different between the first PMOS transistor, first NMOS transistor, second PMOS transistor, and second NMOS transistor in each stage of the delay control circuit to obtain different phase-leading or phase-lagging clock signals.
4. The clock skew calibration circuit of claim 3, wherein the parameters comprise a channel width and a length of a transistor.
5. The clock skew calibration circuit of claim 1, wherein the bias voltage generation circuit includes third to fifth PMOS transistors, third to fourth NMOS transistors, and first and second resistors, sources of the third to fifth PMOS transistors being connected to a power supply terminal, gates of the third PMOS transistor and the fourth PMOS transistor being connected to the digital-to-analog conversion circuit, a drain of the fourth PMOS transistor outputting the lagging phase control signal and being connected to one end of the first resistor and gates of the third and fourth NMOS transistors, the other end of the first resistor being connected to a drain of the third NMOS transistor, a drain of the fifth PMOS transistor being connected to one end of the second resistor, a gate of the fifth NMOS transistor being connected to the other end of the second resistor and the drain of the fourth NMOS transistor and outputting the leading phase control signal.
6. The clock skew calibration circuit of claim 1, wherein the first delay cell comprises an inverter having an input coupled to the input clock signal and an output coupled to the coupling cell.
7. The clock skew calibration circuit of claim 1, wherein the second delay cell comprises an inverter having an input coupled to the connection cell and an output coupled to an input of the phase lag cell.
8. A phase interpolator based clock skew calibration circuit, comprising:
a bias voltage generating circuit that generates a leading phase control signal and a lagging phase control signal from an output of the digital-to-analog converting circuit;
a plurality of clock delay control branches, each clock delay control branch having at least one stage of delay control circuit, each stage of the delay control circuit comprising: the phase delay unit is connected with the second delay unit in series and then connected with the phase advancing unit and the first delay unit in parallel; the phase advance unit receives one path of input clock signals in a plurality of paths of input clock signals and outputs phase advance clock signals to the connection unit according to the advance phase control signals and the lag phase control signals, the first delay unit receives the input clock signals and outputs first delay clock signals to the connection unit, and the connection unit outputs the second delay unit, the phase advance unit of the next stage of delay control circuit and the first delay unit; the second delay unit receives the output of the connection unit and outputs a second delayed clock signal to the phase lag unit, and the lag phase unit receives the second delayed clock signal and outputs a phase lag clock signal to the connection unit based on the lead phase control signal and the lag phase control signal.
9. The clock skew calibration circuit of claim 8, wherein the clock skew calibration circuit comprises 12 clock delay control branches.
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| CN202211065860.4A CN115361017B (en) | 2022-08-31 | 2022-08-31 | Clock skew calibration circuit based on phase interpolator |
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| US6125157A (en) * | 1997-02-06 | 2000-09-26 | Rambus, Inc. | Delay-locked loop circuitry for clock delay adjustment |
| CN1954494A (en) * | 2004-05-26 | 2007-04-25 | 松下电器产业株式会社 | Skew correction apparatus |
| CN103986461A (en) * | 2014-05-30 | 2014-08-13 | 华为技术有限公司 | Time-to-digital conversion method and time-to-digital converter |
| CN106849942A (en) * | 2016-12-29 | 2017-06-13 | 北京时代民芯科技有限公司 | A kind of ultrahigh speed low jitter multiphase clock circuit |
| US10218343B1 (en) * | 2017-10-31 | 2019-02-26 | Sandisk Technologies Llc | Duty cycle correction scheme |
| US10804919B1 (en) * | 2019-09-24 | 2020-10-13 | Microsoft Technology Licensing, Llc | Dynamic sequential approximation register (SAR) analog-to-digital converter (ADC) (SAR-ADC) clock delay calibration systems and methods |
| CN113890533A (en) * | 2020-07-02 | 2022-01-04 | 三星电子株式会社 | Delay circuit of delay locked loop circuit and delay locked loop circuit |
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2022
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6125157A (en) * | 1997-02-06 | 2000-09-26 | Rambus, Inc. | Delay-locked loop circuitry for clock delay adjustment |
| CN1954494A (en) * | 2004-05-26 | 2007-04-25 | 松下电器产业株式会社 | Skew correction apparatus |
| CN103986461A (en) * | 2014-05-30 | 2014-08-13 | 华为技术有限公司 | Time-to-digital conversion method and time-to-digital converter |
| CN106849942A (en) * | 2016-12-29 | 2017-06-13 | 北京时代民芯科技有限公司 | A kind of ultrahigh speed low jitter multiphase clock circuit |
| US10218343B1 (en) * | 2017-10-31 | 2019-02-26 | Sandisk Technologies Llc | Duty cycle correction scheme |
| US10804919B1 (en) * | 2019-09-24 | 2020-10-13 | Microsoft Technology Licensing, Llc | Dynamic sequential approximation register (SAR) analog-to-digital converter (ADC) (SAR-ADC) clock delay calibration systems and methods |
| CN113890533A (en) * | 2020-07-02 | 2022-01-04 | 三星电子株式会社 | Delay circuit of delay locked loop circuit and delay locked loop circuit |
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