CN115347037A - Semiconductor epitaxial structure and preparation method thereof - Google Patents

Abstract

The invention discloses a semiconductor epitaxial structure and a preparation method thereof. The semiconductor epitaxial structure includes a high quality epitaxial layer disposed on a substrate, which includes: epitaxial restriction layer and set up the second epitaxial growth layer on it, epitaxial restriction layer includes outer restriction unit, interior intermittent unit and first epitaxial growth layer, outer restriction unit is closed form all around and surrounds interior intermittent unit and first epitaxial growth layer, interior intermittent unit is the interval setting, and first epitaxial growth layer distributes and sets up between outer restriction unit and interior intermittent unit to and in adjacent in the region between the intermittent unit. The invention arranges discontinuous intervals in the internal discontinuous units, and utilizes the high dislocation between the substrate and the epitaxial layer to turn for many times at the position of the discontinuous intervals in the growth process of the epitaxial limiting layer, the dislocation is promoted to turn fully to achieve dislocation self annihilation, and the distribution of threading dislocation is greatly reduced, so that the crystal quality of the epitaxial semiconductor epitaxial layer of the heterogeneous substrate is improved.

Description

Semiconductor epitaxial structure and its preparation method

technical field

The invention relates to a semiconductor epitaxial structure and a preparation method thereof, belonging to the technical field of semiconductors.

Background technique

Gallium Nitride (GaN), as a third-generation semiconductor material, has the characteristics of high band gap, high critical breakdown electric field, high carrier saturation migration velocity, high thermal conductivity and direct band gap. Power microelectronic devices and high-performance optoelectronic devices have great application prospects. Since III-nitrides are generally heteroepitaxy on heterogeneous substrates such as sapphire or SiC, the lattice constant and thermal mismatch between different materials will generate dislocations or defects, which extend upward as the epitaxial layer grows , these dislocations behave as non-radiative recombination centers when the device is working, which affects the efficiency of the device. At the same time, as a leakage channel, the leakage current increases and the device ages rapidly, affecting the working efficiency and life of the device, which restricts its application in the field of semiconductor electronics. Applications.

Contents of the invention

The main purpose of the present invention is to provide a semiconductor epitaxial structure and its preparation method to overcome the deficiencies of the prior art.

In order to realize the aforementioned object of the invention, the technical solutions adopted in the present invention include:

An embodiment of the present invention provides a semiconductor epitaxial structure, including: a high-quality epitaxial layer disposed on a substrate; the high-quality epitaxial layer includes:

The epitaxial confinement layer includes an outer confinement unit, an inner discontinuity unit and a first epitaxial growth layer, the outer confinement unit surrounds the inner discontinuity unit and the first epitaxial growth layer in a closed shape, wherein the inner discontinuity units are arranged at intervals, And the first epitaxial growth layer is distributed and arranged in the region between the outer confinement unit and the inner discontinuity unit, and between adjacent inner discontinuity units;

The second epitaxial growth layer is arranged on the epitaxial confinement layer.

The embodiment of the present invention also provides a method for preparing a semiconductor epitaxial structure, which includes:

setting a bottom epitaxial layer on the substrate; and etching the bottom epitaxial layer to form a closed outer confinement unit;

discontinuous epitaxial layers and discontinuous sacrificial layers are arranged alternately inside the outer confinement unit;

Etching away part of the discontinuous epitaxial layer region and part of the discontinuous sacrificial layer region, removing the discontinuous sacrificial layer, retaining the discontinuous epitaxial layer, and obtaining internal discontinuous units arranged at intervals;

A first epitaxial growth layer is arranged in the region between the outer confinement unit and the inner discontinuity unit, and between adjacent inner discontinuity units, to form an epitaxial confinement layer;

A second epitaxial growth layer is arranged on the epitaxial confinement layer to obtain a semiconductor epitaxial structure.

Compared with the prior art, the beneficial effects of the present invention are at least:

In the semiconductor epitaxial structure provided by the present invention, a discontinuous discontinuity interval is set in the inner discontinuity unit, and the high dislocation between the substrate and the epitaxial layer is turned multiple times at the discontinuity interval position during the growth process of the epitaxial confinement layer, so that the dislocation is fully turned to achieve The self-annihilation of dislocations greatly reduces the extension of dislocations to the epitaxial growth layer and reduces the distribution of threading dislocations, which can improve the leakage and withstand voltage characteristics of devices, improve the crystal quality of epitaxial semiconductor epitaxial layers on heterogeneous substrates, and broaden the The application of semiconductor epitaxial wafers in the field of microelectronics can be applied to the epitaxial growth of semiconductor power devices.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments described in the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is a schematic diagram of the process of forming closed outer confinement units by etching in a typical embodiment of the present invention.

Fig. 2 is a top view of an outer confining unit in a typical embodiment of the present invention.

Fig. 3 is a schematic structural diagram of alternately setting discontinuous epitaxial layers and discontinuous sacrificial layers inside the outer confinement unit in a typical embodiment of the present invention.

Fig. 4 is a schematic diagram of the structure after etching the discontinuous epitaxial layer and the discontinuous sacrificial layer in a typical implementation case of the present invention.

FIG. 5 is a schematic structural diagram of an internal discontinuous unit after removing the discontinuous sacrificial layer region in a typical embodiment of the present invention.

Fig. 6 is a schematic structural diagram of an internal discontinuity unit in another typical embodiment of the present invention.

Fig. 7 is a schematic structural diagram of an internal discontinuity unit in another typical embodiment of the present invention.

Fig. 8 is a schematic diagram of dislocation turning when growing an epitaxial confinement layer in a typical embodiment of the present invention.

FIG. 9 is a schematic diagram of a semiconductor epitaxial structure in a typical embodiment of the present invention.

Fig. 10 is a graph showing half-peak widths of (102) plane rocking curves tested by XRD on the semiconductor epitaxial wafers obtained in Examples 1-5 and Comparative Examples 1-5 of the present invention.

Fig. 11 and Fig. 12 are the optical microscope pictures of the semiconductor epitaxial wafers obtained in Comparative Example 4 and Comparative Example 5 of the present invention, respectively.

Detailed ways

In view of the deficiencies in the prior art, the inventor of this case has been able to propose the technical solution of the present invention after long-term research and practice. The technical solution, its implementation process and principles will be further explained as follows.

A semiconductor epitaxial structure provided by some embodiments of the present invention includes a high-quality epitaxial layer disposed on a substrate, and the high-quality epitaxial layer includes:

The epitaxial confinement layer includes an outer confinement unit, an inner discontinuity unit and a first epitaxial growth layer, the outer confinement unit surrounds the inner discontinuity unit and the first epitaxial growth layer in a closed shape, wherein the inner discontinuity units are arranged at intervals, And the first epitaxial growth layer is distributed and arranged in the region between the outer confinement unit and the inner discontinuity unit, and between adjacent inner discontinuity units;

The second epitaxial growth layer is arranged on the epitaxial confinement layer.

In some embodiments, the outer confinement unit has a height of 1-5 μm.

In some embodiments, the wall thickness of the peripherally closed outer confinement unit is 0.2-5 μm.

Further, the material of the outer confinement unit may be GaN, but not limited thereto.

In some embodiments, the distance between two adjacent inner discontinuous units is 0.5-2 μm.

Further, the thickness of the inner discontinuous unit is 0.5-2.5 μm.

Further, cross-sectional areas of any two internal discontinuity units are the same or different, which is not limited.

Further, the material of the internal discontinuity unit includes any one of nitrides, oxides, metals, organic substances and the like. For example, any of GaN, AlN, InGaN, AlGaN, AlInGaN, AlInN, InN, Al ₂ O ₃ , SiO ₂ , Si ₃ N ₄ , Ga ₂ O ₃ , ZnO, Fe, Cu, Ag, etc. may be preferred. , but not limited to this.

In some embodiments, both ends of the inner discontinuity unit are respectively connected to the surrounding walls of the outer restriction unit.

In some implementations, the material of the first epitaxial growth layer may be GaN, but is not limited thereto.

Further, the thickness of the second epitaxial growth layer is 1 nm-20 μm.

Further, the material of the second epitaxial growth layer may be GaN, but is not limited thereto.

Further, the substrate may be a sapphire substrate, a silicon substrate, a silicon carbide substrate, etc., but is not limited thereto.

In the present invention, the mechanism of discontinuous unit being set inside the outer limiting unit is:

In the present invention, discontinuous discontinuities are arranged in the inner discontinuity unit, and the high dislocations between the substrate and the first epitaxial growth layer are turned multiple times in the discontinuity intervals during the growth process of the epitaxial confinement layer, so as to promote the dislocations to fully turn to reach the dislocation Self-annihilation greatly reduces the extension of dislocations to the second epitaxial growth layer and reduces the distribution of threading dislocations, thereby improving device leakage and withstand voltage characteristics, and broadening the application of semiconductor epitaxial wafers in the field of microelectronics.

Some embodiments of the present invention also provide a method for preparing a semiconductor epitaxial structure comprising:

setting a bottom epitaxial layer on the substrate; and etching the bottom epitaxial layer to form a closed outer confinement unit;

discontinuous epitaxial layers and discontinuous sacrificial layers are arranged alternately inside the outer confinement unit;

Etching away part of the discontinuous epitaxial layer region and part of the discontinuous sacrificial layer region, removing the discontinuous sacrificial layer, retaining the discontinuous epitaxial layer, and obtaining internal discontinuous units arranged at intervals;

A first epitaxial growth layer is arranged in the region between the outer confinement unit and the inner discontinuity unit, and between adjacent inner discontinuity units, to form an epitaxial confinement layer;

A second epitaxial growth layer is arranged on the epitaxial confinement layer to obtain a semiconductor epitaxial structure.

In some embodiments, the thickness of the bottom epitaxial layer is 1-5 μm.

Further, the material of the bottom epitaxial layer may be GaN, but is not limited thereto.

Further, the wall thickness of the surrounding closed outer confinement unit is 0.2-5 μm.

In some embodiments, the materials of the interrupted epitaxial layer or the interrupted sacrificial layer are different, and are independently selected from any one of nitrides, oxides, metals, organics, and the like. For example, any of GaN, AlN, InGaN, AlGaN, AlInGaN, AlInN, InN, Al ₂ O ₃ , SiO ₂ , Si ₃ N ₄ , Ga ₂ O ₃ , ZnO, Fe, Cu, Ag, etc. may be preferred. , but not limited to this.

Further, the thickness of the interrupted epitaxial layer or the interrupted sacrificial layer is 0.5-2.5 μm, and the total thickness of the interrupted epitaxial layer and the interrupted sacrificial layer does not exceed the height of the outer confinement unit.

Further, the thicknesses of any two interrupted epitaxial layers or interrupted sacrificial layers are the same or different.

Further, the preparation method includes: at least removing the interrupted sacrificial layer by solution wet etching.

In some embodiments, the preparation method includes: adopting MOCVD epitaxial growth technology, disposing a first epitaxial growth layer in a region between the outer confinement unit and the inner discontinuity unit, and between adjacent inner discontinuity units. Preferably, the present invention can also anneal the outer confinement unit and the inner discontinuity unit on the substrate before the growth of the first epitaxial growth layer, so as to eliminate the side walls of the outer confinement unit and the inner discontinuity unit caused by dry etching damage, so that complete interfacial properties can be formed when the first epitaxial growth layer grows. Wherein, the temperature of the annealing treatment is 500-700° C., and the time is 1-15 minutes.

In some embodiments, the growth temperature of the first epitaxial growth layer is 1000-1100° C., and the growth pressure is 200-400 torr.

Further, the growth temperature of the second epitaxial growth layer is 1100-1200° C., and the growth pressure is 100-300 torr.

Further, the material and thickness of the first epitaxial growth layer, the second epitaxial growth layer, and the substrate are as described above, and will not be repeated here.

In some embodiments, the method for preparing the semiconductor epitaxial structure specifically includes:

1) providing a substrate, and setting a bottom epitaxial layer on the substrate;

2) Etching the bottom epitaxial layer by etching to form an outer confinement unit in a closed shape;

3) discontinuous epitaxial layers and discontinuous sacrificial layers are arranged alternately inside the outer confinement unit;

4) forming alternately intermittent epitaxial layer regions and intermittent sacrificial layer regions inside the epitaxial confinement unit by an etching process;

5) removing the discontinuous sacrificial layer region to form an inner discontinuous unit inside the outer confinement unit, and the inner discontinuous section has a discontinuous discontinuous section;

6) setting the first epitaxial growth layer in the area adjacent to the outer confinement unit, the inner discontinuity unit and the discontinuity interval to form an epitaxial confinement layer;

7) A second epitaxial growth layer is arranged on the epitaxial confinement layer to obtain a high-quality epitaxial layer, and the high-quality epitaxial layer and the substrate form a semiconductor epitaxial wafer.

In a more specific embodiment, the preparation method of a kind of semiconductor epitaxial wafer provided by the present invention specifically comprises the following steps:

1) A sapphire substrate 100 is provided, and a GaN bottom epitaxial layer 200 with a thickness of 1-5 μm is provided on the substrate, as shown in FIG. 1 ;

2) As shown in FIG. 1, the GaN bottom epitaxial layer 200 is etched by ICP dry etching to form a GaN outer confinement unit 210 with a surrounding wall thickness of 1-10 mm, which is closed, and its top view is shown in FIG. 2 ;

3) Al ₂ O ₃ interrupted epitaxial layers 300 and SiO ₂ interrupted sacrificial layers 400 with a thickness of 0.5-2.5 μm are alternately arranged inside the GaN outer confinement unit 210, as shown in FIG. 3 , Al ₂ O ₃ interrupted epitaxial layers 300 and SiO 2 _2. The total thickness of the discontinuous sacrificial layer 400 does not exceed the height of the GaN outer confinement unit 210;

4) Alternating Al ₂ O ₃ intermittent epitaxial layer regions 310 and SiO ₂ interrupted sacrificial layer regions 410 are formed inside the GaN epitaxial confinement unit 210 by an etching process, as shown in FIG. 4 ;

5) Use 49% HF aqueous solution and 40% NH ₄ F aqueous solution to wet etch the mixed solution with a volume ratio of 1:6 to remove the SiO ₂ discontinuous sacrificial layer region 410, and form Al ₂ O in the GaN outer confinement unit 210 ₃ Inner discontinuity unit 320, the inner discontinuity section has discontinuous discontinuity intervals, as shown in FIG. 5 . Specifically, if the GaN outer confinement unit 210 is understood to be arranged vertically _on the substrate surface, the _Al2O3 inner discontinuity unit 320 is arranged along a direction parallel to the substrate;

According to the different conditions such as the growth position and thickness of the Al ₂ O ₃ interrupted epitaxial layer and the SiO ₂ interrupted sacrificial layer in step 3), the structural distribution of the Al ₂ O ₃ internal interrupted unit formed after the SiO ₂ interrupted sacrificial layer is finally removed is also different. It may be different, for example, please refer to FIG. 6 and FIG. 7 , both of which are also within the protection scope of the present invention.

6) Using MOCVD epitaxial growth technology, the outer confinement unit and inner discontinuity unit on the substrate are annealed in N ₂ atmosphere, and then the GaN outer confinement unit 210 and Al ₂ O ₃ inner discontinuity unit 320 and discontinuity interval are adjacent A first GaN epitaxial growth layer 500 is set in the region, as shown in FIG. 8 , forming a GaN epitaxial confinement layer 600;

7) Set the second GaN epitaxial growth layer 700 on the GaN epitaxial confinement layer 600 to obtain a high-quality GaN epitaxial layer. As shown in FIG. 9 , the high-quality GaN epitaxial layer and the sapphire substrate constitute a GaN semiconductor epitaxial wafer.

In summary, the semiconductor epitaxial wafer provided by the present invention is provided with discontinuous discontinuous intervals in the inner discontinuous unit, and utilizes the high dislocation between the substrate and the epitaxial layer to turn multiple times at the discontinuous interval position during the growth process of the epitaxial confinement layer (such as As shown in Figure 8), dislocations can be fully turned to achieve self-annihilation of dislocations, greatly reducing the extension of dislocations to the epitaxial growth layer, reducing the distribution of threading dislocations, thereby improving device leakage and withstand voltage characteristics, and improving heterogeneous The crystal quality of the substrate epitaxial semiconductor epitaxial layer broadens the application of semiconductor epitaxial wafers in the field of microelectronics and is suitable for epitaxial growth of semiconductor power devices.

The technical solution of the present application will be described in more detail below with reference to the accompanying drawings and several embodiments, but it should be understood that the following embodiments are only for explaining and illustrating the technical solution, but do not limit the scope of the present application. And, unless otherwise specified, the various raw materials, reaction equipment, detection equipment and methods used in the following examples are all known in the art.

Example 1

In this embodiment, a high-quality GaN epitaxial layer is taken as an example for illustration, the discontinuous epitaxial layer is made of Al ₂ O ₃ , and the discontinuous sacrificial layer is made of SiO ₂ . Concrete preparation process comprises the following steps:

1) Provide a sapphire substrate, grow a GaN bottom epitaxial layer with a thickness of 3 μm on the substrate, wherein the growth temperature is 1085° C., the growth pressure is 150 torr, and the growth atmosphere is H ₂ ;

2) Etch the GaN bottom epitaxial layer by ICP dry etching to form a closed GaN outer confinement unit with a wall thickness of 2 μm, in which the ICP power is 950W, and the etching gas is 20% BCl ₃ and 80 % Cl ₂ , the etching pressure is 10mtorr;

3) The Al ₂ O ₃ interrupted epitaxial layer with a thickness of 0.5 μm and the SiO ₂ interrupted sacrificial layer with a thickness of 0.5 μm are alternately arranged inside the GaN outer confinement unit by PECVD method, and the Al ₂ O ₃ interrupted epitaxial layer and the SiO ₂ interrupted sacrificial layer The total thickness does not exceed the height of the GaN outer confinement unit, where the Al ₂ O ₃ intermittent epitaxial layer uses trimethylaluminum (TMAl) and oxygen (O ₂ ), the growth temperature is 300°C, the growth pressure is 0.2torr, and the SiO ₂ is intermittent The sacrificial layer is made of silane (SiH ₄ ) and nitrogen dioxide (NO ₂ ), the growth temperature is 400°C, and the growth pressure is 3.5 torr;

4) Alternate Al ₂ O ₃ intermittent epitaxial layer regions and SiO ₂ interrupted sacrificial layer regions are formed inside the GaN epitaxial confinement unit by ICP dry etching process, where the ICP power is 950W, and the etching gas is 20% BCl ₃ and 80% Cl ₂ , the etching pressure is 10mtorr;

5) Use 49% HF aqueous solution and 40% NH ₄ F aqueous solution to wet etch the mixed solution with a volume ratio of 1:6 to remove the SiO ₂ discontinuous sacrificial layer region, and form an Al ₂ O ₃ inner layer inside the GaN outer confinement unit. A discontinuous unit, the inner discontinuous interval has discontinuous discontinuous intervals;

6) Using MOCVD epitaxial growth technology, set the first GaN epitaxial growth layer with a thickness of 3 μm in the adjacent area of the GaN outer confinement unit, the Al ₂ O ₃ inner discontinuity unit and the discontinuity interval to form the GaN epitaxial confinement layer, wherein the growth temperature is 1005℃℃, the growth pressure is 400torr;

7) Continue to epitaxially grow the second GaN epitaxial growth layer with a thickness of 5 μm on the GaN epitaxial confinement layer to obtain a high-quality GaN epitaxial layer. The high-quality GaN epitaxial layer and the sapphire substrate constitute a GaN semiconductor epitaxial wafer, wherein the growth temperature is 1125°C, the growth pressure is 200torr, and the growth atmosphere is H ₂ .

Example 2

Compared with Embodiment 1, this embodiment differs in that:

In step 6), the thickness of the grown first GaN epitaxial growth layer is 1 μm, the growth temperature is 1000° C., and the growth pressure is 300 torr.

In step 7), the thickness of the grown second GaN epitaxial growth layer is 0.2 μm.

Example 3

Compared with Embodiment 1, this embodiment differs in that:

In step 6), the thickness of the grown first GaN epitaxial growth layer is 5 μm, the growth temperature is 1100° C., and the growth pressure is 200 torr.

In step 7), the thickness of the grown second GaN epitaxial growth layer is 15 μm.

Example 4

Compared with Embodiment 1, this embodiment differs in that:

In step 6), annealing is first performed on the outer confinement unit and inner discontinuity unit on the substrate, and then the first GaN epitaxial growth layer is grown. The annealing temperature is 700° C. and the time is 1 min.

In step 7), the growth temperature of the second GaN epitaxial growth layer is 1100° C., the growth pressure is 300 torr, and the thickness of the grown second GaN epitaxial growth layer is 1 nm.

Example 5

Compared with Embodiment 1, this embodiment differs in that:

In step 6), annealing is first performed on the outer confinement unit and inner discontinuity unit on the substrate, and then the first GaN epitaxial growth layer is grown. The annealing temperature is 500° C. and the time is 15 minutes.

In step 7), the growth temperature of the second GaN epitaxial growth layer is 1200° C., the growth pressure is 100 torr, and the thickness of the grown second GaN epitaxial growth layer is 20 μm.

The thickness of the bottom epitaxial layer in the above embodiments may be any value in the range of 1-5 μm, and the wall thickness of the surrounding closed outer confinement unit may be any value in the range of 0.2-5 μm. The thickness of the discontinuous epitaxial layer or discontinuous sacrificial layer can be controlled at 0.5-2.5 μm.

Comparative example 1

Compared with Example 1, this comparative example differs in that: a second GaN epitaxial growth layer with a thickness of 5 μm is continuously epitaxially grown on the GaN bottom epitaxial layer in step 1).

Comparative example 2

Compared with Example 1, this comparative example differs in that: the second GaN epitaxial growth layer with a thickness of 0.2 μm is continuously epitaxially grown on the GaN bottom epitaxial layer in step 1).

Comparative example 3

Compared with Example 1, this comparative example differs in that: the second GaN epitaxial growth layer with a thickness of 15 μm is continuously epitaxially grown directly on the GaN bottom epitaxial layer in step 1).

Comparative example 4

The difference from Example 1 is that the second GaN epitaxial growth layer is directly epitaxially grown on the GaN bottom epitaxial layer in step 1), and the growth temperature is 1075°C.

Comparative example 5

The difference from Example 1 is that the second GaN epitaxial growth layer is directly grown on the GaN bottom epitaxial layer in step 1), and the growth temperature is 1275°C.

Examples 1-5 and Comparative Examples 1-5 were respectively tested by XRD for the half-peak width of the rocking curve of the (102) plane, and the data are shown in FIG. 10 .

As can be seen from Figure 10, the above embodiments have lower (102) half-value widths than the comparative examples, because the (102) half-value widths directly reflect the distribution of threading dislocations in the epitaxial layer, and the low (102) Half width has low threading dislocations, so the examples have lower threading dislocations. In addition, the overall fluctuation of the (102) half-peak width of Examples 1 to 5 is small, while the fluctuation of the (102) half-peak width is relatively large in the comparative examples, especially in comparative examples 4 and 5, the (102) half-peak width exceeds 350arcsec, Compared with Comparative Example 1, the (102) half-maximum width of Comparative Example 4 and Comparative Example 5 is greatly affected by the growth temperature, and it is found that Comparative Example 4 has a large number of black dot distributions (as shown in Figure 11) by optical microscopy, while for Comparative Example 4 Ratio 5 has a large amount of hexagonal defects (as shown in Figure 12); Compared with Example 1, the half peak widths of Example 4 and Example 5 are all less than 200arcsec, and the examples all have smooth surfaces, illustrating that the present invention is implemented The growth temperature of the example has a larger process window, which improves the stability of the growth process.

The above embodiments are only preferred embodiments for fully illustrating the present invention, and the protection scope of the present invention is not limited thereto. Equivalent substitutions or transformations made by those skilled in the art on the basis of the present invention are all within the protection scope of the present invention. The protection scope of the present invention shall be determined by the claims.

Claims (10)

1. A semiconductor epitaxial structure, comprising: a high quality epitaxial layer disposed on the substrate; the high quality epitaxial layer includes:

the epitaxial limiting layer comprises an outer limiting unit, an inner interruption unit and a first epitaxial growth layer, wherein the outer limiting unit surrounds the inner interruption unit and the first epitaxial growth layer in a closed shape at the periphery, the inner interruption unit is arranged at intervals, and the first epitaxial growth layer is distributed and arranged between the outer limiting unit and the inner interruption unit and in the area between the adjacent inner interruption units;

and the second epitaxial growth layer is arranged on the epitaxial limiting layer.

2. The semiconductor epitaxial structure of claim 1, wherein: the height of the outer limiting unit is 1-5 mu m; and/or the wall thickness of the outer limiting unit with closed periphery is 0.2-5 microns;

and/or the material of the outer limiting unit comprises GaN.

3. The semiconductor epitaxial structure of claim 1, wherein: the distance between two adjacent internal discontinuous units is 0.5-2 mu m; and/or the thickness of the internal discontinuous unit is 0.5-2.5 μm; and/or the cross-sectional areas of any two of the internal interruption units are the same or different;

and/or the material of the internal discontinuous unit comprises any one of nitride, oxide, metal and organic matter.

4. The semiconductor epitaxial structure of claim 3, wherein: the material of the internal discontinuous unit comprises GaN, alN, inGaN, alGaN, alInGaN, alInN, inN and Al ₂ O ₃ 、SiO ₂ 、Si ₃ N ₄ 、Ga ₂ O ₃ Any one of ZnO, fe, cu and Ag;

and/or two ends of the inner discontinuous unit are respectively connected with the peripheral wall of the outer limiting unit.

5. The semiconductor epitaxial structure of claim 1, wherein: the material of the first epitaxial growth layer comprises GaN; and/or the thickness of the second epitaxial growth layer is 1 nm-20 mu m; and/or the material of the second epitaxial growth layer comprises GaN;

and/or the substrate comprises any one of a sapphire substrate, a silicon substrate and a silicon carbide substrate.

6. A preparation method of a semiconductor epitaxial structure is characterized by comprising the following steps:

arranging a bottom epitaxial layer on a substrate; etching the bottom epitaxial layer to form an outer limiting unit with closed periphery;

alternately arranging intermittent epitaxial layers and intermittent sacrificial layers inside the outer limiting unit;

etching off a part of the discontinuous epitaxial layer region and a part of the discontinuous sacrificial layer region, removing the discontinuous sacrificial layer, and keeping the discontinuous epitaxial layer to obtain inner discontinuous units arranged at intervals;

arranging first epitaxial growth layers between the outer limiting units and the inner discontinuous units and in the areas between the adjacent inner discontinuous units to form epitaxial limiting layers;

and arranging a second epitaxial growth layer on the epitaxial limiting layer to obtain the semiconductor epitaxial structure.

7. The method of manufacturing according to claim 6, characterized in that: the thickness of the bottom epitaxial layer is 1-5 mu m; and/or the material of the bottom epitaxial layer comprises GaN;

and/or the wall thickness of the outer limiting unit with the closed periphery is 0.2-5 mu m.

8. The method of claim 6, wherein: the discontinuous epitaxial layer or the discontinuous sacrificial layer is made of different materials and is independently selected from any one of nitride, oxide, metal and organic matter;

and/or the thickness of the discontinuous epitaxial layer or the discontinuous sacrificial layer is 0.5-2.5 microns, and the total thickness of the discontinuous epitaxial layer and the discontinuous sacrificial layer does not exceed the height of the outer limiting unit;

and/or the thicknesses of any two discontinuous epitaxial layers or discontinuous sacrificial layers are the same or different.

9. The method of claim 8, wherein: the discontinuous epitaxial layer or the discontinuous sacrificial layer is made of GaN, alN, inGaN, alGaN, alInGaN, alInN, inN and Al ₂ O ₃ 、SiO ₂ 、Si ₃ N ₄ 、Ga ₂ O ₃ Any one of ZnO, fe, cu and Ag;

and/or, the preparation method comprises: and removing the discontinuous sacrificial layer by at least wet etching.

10. The method of claim 6, comprising: setting a first epitaxial growth layer between the outer limiting unit and the inner discontinuous unit and between adjacent inner discontinuous units by adopting an MOCVD epitaxial growth technology, wherein the growth temperature is 1000-1100 ℃, and the growth pressure is 200-400 torr; and/or the material of the first epitaxial growth layer comprises GaN;

and/or, the preparation method comprises: before the first epitaxial growth layer grows, annealing the external limiting unit and the internal interruption unit at the temperature of 500-700 ℃ for 1-15 min;

and/or the growth temperature of the second epitaxial growth layer is 1100-1200 ℃, and the growth pressure is 100-300 torr;

and/or the thickness of the second epitaxial growth layer is 1 nm-20 mu m; and/or the material of the second epitaxial growth layer comprises GaN; and/or, the substrate comprises a sapphire substrate.

Images