CN115346912B - Preparation method of shallow trench isolation structure - Google Patents
Preparation method of shallow trench isolation structure Download PDFInfo
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- CN115346912B CN115346912B CN202211276822.3A CN202211276822A CN115346912B CN 115346912 B CN115346912 B CN 115346912B CN 202211276822 A CN202211276822 A CN 202211276822A CN 115346912 B CN115346912 B CN 115346912B
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- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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Abstract
The application provides a preparation method of a shallow trench isolation structure, which comprises the following steps: providing a semiconductor substrate; forming a graphical silicon nitride layer, and forming a shallow trench by dry etching; forming a silicon dioxide isolation structure in the shallow trench, wherein the height difference between the upper surface of the silicon dioxide isolation structure and the upper surface of the semiconductor substrate forms a first step height; removing part of the silicon nitride layer and the silicon dioxide isolation structure by first silicon nitride wet etching, wherein the height difference between the upper surface of the residual silicon dioxide isolation structure and the upper surface of the semiconductor substrate forms a second step height which is smaller than the first step height; and removing the residual silicon nitride layer by second silicon nitride wet etching, wherein the etching rate of the residual silicon nitride layer to silicon dioxide is 0A/min. The method and the device control the etching amount of the silicon dioxide layer in the shallow trench isolation structure in the wet etching process of the silicon nitride layer by introducing two steps of different wet etching processes, so that the step height of the shallow trench isolation structure is accurately controlled.
Description
Technical Field
The present disclosure relates to the field of semiconductor integrated circuit manufacturing, and more particularly, to a method for manufacturing a shallow trench isolation structure.
Background
In integrated circuit processes with critical dimensions smaller than 0.25um or less, shallow Trench Isolation (STI) structures are generally required to be formed between devices in order to prevent leakage current formed between the devices from affecting the normal operation of the devices.
At present, in the process of manufacturing a shallow trench isolation structure, a shallow trench is generally formed by dry etching, and a silicon dioxide layer is formed in the shallow trench by chemical vapor deposition to form the shallow trench isolation structure. In forming a silicon dioxide layer by chemical vapor deposition, the silicon dioxide layer is deposited on both the shallow trench and the surface of the semiconductor substrate. Silicon nitride layer is generally used as a hard mask layer for dry etching shallow trenches and a stop layer for chemical mechanical polishing of silicon dioxide layer on the surface of semiconductor substrate.
However, after the cmp process is completed and the silicon nitride layer is removed, the silicon dioxide isolation structure in the shallow trench is higher than the surface of the semiconductor substrate and forms a step height (step high), and the control of the step height directly affects the device and adversely affects the stability of the pattern formation and the subsequent processes.
Therefore, it is necessary to provide a new method for fabricating a shallow trench isolation structure to solve the above problems.
Disclosure of Invention
In view of the above disadvantages of the prior art, an object of the present invention is to provide a method for manufacturing a shallow trench isolation structure, which is used to solve the problems that the step height of the shallow trench isolation structure cannot be precisely controlled, and adverse effects are caused on the pattern formation and the stability of the subsequent process in the prior art.
In order to achieve the above and other related objects, the present application provides a method for manufacturing a shallow trench isolation structure, comprising the steps of:
providing a semiconductor substrate;
forming a patterned silicon nitride layer on the semiconductor substrate, and forming a shallow trench in the semiconductor substrate by dry etching by taking the silicon nitride layer as an etching mask;
forming a silicon dioxide isolation structure in the shallow trench, wherein the height difference between the upper surface of the silicon dioxide isolation structure and the upper surface of the semiconductor substrate forms a first step height;
removing part of the silicon nitride layer and part of the silicon dioxide isolation structure through first silicon nitride wet etching, wherein the first silicon nitride wet etching has a determined etching rate for silicon dioxide, the height difference between the upper surface of the remaining silicon dioxide isolation structure and the upper surface of the semiconductor substrate forms a second step height, and the second step height is smaller than the first step height;
and removing the rest of the silicon nitride layer by second silicon nitride wet etching, wherein the etching rate of the second silicon nitride wet etching to silicon dioxide is 0A/min.
As an alternative of the present application, the process of forming the silicon dioxide isolation structure in the shallow trench includes the steps of:
depositing a silicon dioxide layer in the shallow trench and on the surface of the silicon nitride layer;
and taking the silicon nitride layer as a stop layer of chemical mechanical polishing, and removing the silicon dioxide layer on the surface of the silicon nitride layer by chemical mechanical polishing.
As an alternative of the present application, after the silicon dioxide layer on the surface of the silicon nitride layer is removed by chemical mechanical polishing, a step of back etching the silicon dioxide layer in the shallow trench is further included.
As an alternative of the present application, the method of depositing a silicon dioxide layer in the shallow trench and on the surface of the silicon nitride layer comprises chemical vapor deposition; and before depositing the silicon dioxide layer in the shallow trench and on the surface of the silicon nitride layer, forming a barrier oxide layer in the shallow trench.
As an alternative of the application, before the patterned silicon nitride layer is formed on the semiconductor substrate, the method further comprises the step of forming a liner oxide layer on the semiconductor substrate.
As an alternative of the present application, the etching Time (Tank a) of the first silicon nitride wet etching and the etching Time (Tank B) of the second silicon nitride wet etching are obtained by the following formula:
Time (Tank A) =
，
Time (Tank B) = K*(
-
，
in the above formula, THK (STI-OX) is a thickness of the silicon dioxide layer of the silicon dioxide isolation structure before the first silicon nitride wet etching, THK (OX) is a thickness of the silicon dioxide layer of the silicon dioxide isolation structure after the second silicon nitride wet etching, THK (SIN) is a thickness of the silicon nitride layer before the first silicon nitride wet etching, ER (Tank a-OX) is an etching rate of the first silicon nitride wet etching on the silicon dioxide layer of the silicon dioxide isolation structure, ER (Tank a-SIN) is an etching rate of the first silicon nitride wet etching on the silicon nitride layer, ER (Tank B-SIN) is an etching rate of the second silicon nitride wet etching on the silicon nitride layer, and K is an influence factor of over etching.
As an alternative of the present application, the first silicon nitride wet etch has an etch rate ER (Tank a-OX) for silicon dioxide of 0.5-5 a/min; the etching rate ER (Tank A-SIN) of the first silicon nitride wet etching to the silicon nitride layer is 35-70A/min; and the etching rate ER (Tank B-SIN) of the second silicon nitride wet etching to the silicon nitride layer is 35-70A/min.
As an alternative of the present application, the first silicon nitride wet etching uses a phosphoric acid solution with a temperature of 160 ℃ and a mass fraction of 85% as an etching solution, and the second silicon nitride wet etching uses a phosphoric acid solution obtained after performing a certain amount of silicon nitride dummy wafer etching on a phosphoric acid solution with a temperature of 160 ℃ and a mass fraction of 85% as an etching solution.
As an alternative of the present application, the wet tank performing the first silicon nitride wet etching maintains a certain etching rate of the silicon nitride layer by periodically changing the phosphoric acid solution.
As an alternative of the present application, the etching rate ER (Tank B-OX) of the second silicon nitride wet etching for silicon dioxide and the number x of the silicon nitride dummy etches are obtained by the following formula:
ER(Tank B-OX) = -3×10 -8 x 3 + 3×10 -5 x 2 - 0.0118x + 1.557。
as described above, according to the preparation method of the shallow trench isolation structure provided by the application, the etching amount of the silicon dioxide layer in the shallow trench isolation structure in the wet etching process of the silicon nitride layer is controlled by introducing two different wet etching steps, so that the step height of the shallow trench isolation structure can be accurately controlled, and the production yield can be improved.
Drawings
Fig. 1 is a flowchart illustrating a method for fabricating a shallow trench isolation structure according to a first embodiment of the present disclosure.
Fig. 2 is a schematic view of a semiconductor substrate provided in a first embodiment of the present application.
Fig. 3 is a schematic diagram illustrating a patterned silicon nitride layer formed on a semiconductor substrate according to a first embodiment of the present application.
Fig. 4 is a schematic diagram illustrating the formation of shallow trenches in a semiconductor substrate according to a first embodiment of the present disclosure.
Fig. 5 is a schematic diagram illustrating a deposition of a silicon dioxide layer in a shallow trench and on a surface of a silicon nitride layer according to a first embodiment of the present disclosure.
Fig. 6 is a schematic diagram illustrating the removal of the silicon dioxide layer on the surface of the silicon nitride layer by chemical mechanical polishing according to one embodiment of the present disclosure.
Fig. 7 is a schematic diagram illustrating a process of etching back a silicon dioxide layer in a shallow trench according to an embodiment of the present disclosure.
Fig. 8 is a schematic diagram illustrating a first silicon nitride wet etching process to remove a portion of a silicon nitride layer and a portion of a silicon dioxide isolation structure according to a first embodiment of the present disclosure.
Fig. 9 is a schematic diagram illustrating the removal of the remaining silicon nitride layer by the second silicon nitride wet etching process in the first embodiment of the present application.
Fig. 10 is a schematic view of a multi-tank wet process apparatus provided in the first embodiment of the present application.
Fig. 11 is a graph showing the relationship between the etching rate of the phosphoric acid solution for the silicon dioxide layer and the etching amount of the silicon nitride dummy wafer according to the first embodiment of the present application.
Description of the element reference numerals
101-a semiconductor substrate; 102-a liner oxide layer; 103-a silicon nitride layer; 104-shallow trench; 105-a silicon dioxide layer; 106-silicon dioxide isolation structures; 200-multi-groove wet equipment; 201-a first wet bath; 202-a second wet process tank; 203-a third wet process tank; 204-fourth wet tank; 205-fifth wet tank.
Detailed Description
The following embodiments of the present application are described by specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure of the present application. The present application is capable of other and different embodiments and its several details are capable of modifications and/or changes in various respects, all without departing from the spirit of the present application. As in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Spatially relative terms, such as "under," "below," "lower," "below," "over," "upper," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
Please refer to fig. 1 to 11. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present application, and although the drawings only show the components related to the present application and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
Referring to fig. 1 to 11, the present embodiment provides a method for fabricating a shallow trench isolation structure, including the following steps:
1) Providing a semiconductor substrate;
2) Forming a patterned silicon nitride layer on the semiconductor substrate, and forming a shallow trench in the semiconductor substrate by dry etching by taking the silicon nitride layer as an etching mask;
3) Forming a silicon dioxide isolation structure in the shallow trench, wherein the height difference between the upper surface of the silicon dioxide isolation structure and the upper surface of the semiconductor substrate forms a first step height;
4) Removing part of the silicon nitride layer and part of the silicon dioxide isolation structure through first silicon nitride wet etching, wherein the first silicon nitride wet etching has a determined etching rate for silicon dioxide, the height difference between the upper surface of the remaining silicon dioxide isolation structure and the upper surface of the semiconductor substrate forms a second step height, and the second step height is smaller than the first step height;
5) And removing the rest of the silicon nitride layer by second silicon nitride wet etching, wherein the etching rate of the second silicon nitride wet etching to silicon dioxide is 0A/min.
In step 1), referring to S1 of fig. 1 and fig. 2, a semiconductor substrate 101 is provided. Optionally, the semiconductor substrate 101 includes a silicon substrate. As a stress buffer layer between the subsequently grown silicon nitride layer and the silicon substrate, a liner oxide layer 102 may also be grown on the semiconductor substrate 101 through a thermal oxidation process.
In step 2), referring to S2 of fig. 1 and fig. 3 to 4, a patterned silicon nitride layer 103 is formed on the semiconductor substrate 101, and a shallow trench 104 is formed in the semiconductor substrate 101 by dry etching using the silicon nitride layer 103 as an etching mask. Alternatively, as shown in fig. 3, the step of forming a patterned silicon nitride layer 103 on the semiconductor substrate 101 includes: forming a silicon nitride layer 103 on the semiconductor substrate 101 by chemical vapor deposition; forming a patterned photoresist layer through a photoetching process; using the photoresist layer as an etching mask by using CF 4 、CHF 3 The dry etching of the etching gas is performed to form the patterned silicon nitride layer 103, and the remaining photoresist layer is removed by ashing to remove the photoresist and wet cleaning. As shown in fig. 3, dry etching is performed when the patterned silicon nitride layer 103 is formedThe etching also etches away the underlying pad oxide layer 102 at the same time. Optionally, as shown in fig. 4, the patterned silicon nitride layer 103 is used as an etching mask to form a shallow trench 104 in the semiconductor substrate 101 by dry etching, and the dry etching for forming the shallow trench 104 adopts SF 6 、Cl 2 Or HBr or the like as the etching gas.
In step 3), please refer to S3 of fig. 1 and fig. 5 to 7. A silicon dioxide isolation structure 106 is formed in the shallow trench 104, and a height difference between an upper surface of the silicon dioxide isolation structure 106 and an upper surface of the semiconductor substrate 101 forms a first step height H1.
As an example, as shown in fig. 5 to 6, the process of forming the silicon dioxide isolation structure 106 in the shallow trench 104 includes the following steps:
depositing a silicon dioxide layer 105 in the shallow trench 104 and on the surface of the silicon nitride layer 103;
the silicon nitride layer 103 is used as a stop layer for chemical mechanical polishing, and the silicon dioxide layer 105 on the surface of the silicon nitride layer 103 is removed by chemical mechanical polishing. Finally, the silicon dioxide isolation structure 106 is formed in the shallow trench 104, i.e., the silicon dioxide isolation structure 106 is composed of a silicon dioxide layer.
As an example, as shown in fig. 5 to fig. 7, after the silicon dioxide layer 105 on the surface of the silicon nitride layer 103 is removed by chemical mechanical polishing, a step of etching back the silicon dioxide layer 105 in the shallow trench 104 is further included. As shown in fig. 6, the silicon dioxide isolation structures 106 after chemical mechanical polishing have an upper surface substantially flush with the surface of the silicon nitride layer 103, but are slightly recessed due to the chemical mechanical polishing. As shown in fig. 7, the silicon dioxide isolation structure 106 is formed by etching back the silicon dioxide layer 105 in the shallow trench 104, and the height difference between the upper surface of the silicon dioxide isolation structure and the upper surface of the semiconductor substrate 101 forms a first step height H1. It is noted that, in the present embodiment, the first step height H1 is a height from the top surface of the pad oxide layer 102 to the top surface of the silicon dioxide isolation structure 106, but in other embodiments of the present invention, the first step height H1 may be directly measured from the top surface of the semiconductor substrate 101. Since the pad oxide layer 102 is thin, the difference has little effect.
As an example, as shown in fig. 5, the method of depositing the silicon dioxide layer 105 in the shallow trench 104 and on the surface of the silicon nitride layer 103 includes chemical vapor deposition; before depositing the silicon dioxide layer 105 in the shallow trench 104 and on the surface of the silicon nitride layer 103, a step of forming a blocking oxide layer in the shallow trench 104 is further included. Since the silicon dioxide layer formed by cvd generally has more impurities, the diffusion of impurities in the semiconductor substrate 101 can be prevented by forming a barrier oxide layer on the sidewall of the shallow trench 104 by a thermal oxidation process. The barrier oxide layer is not shown in fig. 5.
In step 4), please refer to S4 and fig. 8 of fig. 1. And removing part of the silicon nitride layer 103 and part of the silicon dioxide isolation structure 106 by using a first silicon nitride wet etching method, wherein the first silicon nitride wet etching method has a determined etching rate for silicon dioxide, the height difference between the upper surface of the remaining silicon dioxide isolation structure 106 and the upper surface of the semiconductor substrate 101 forms a second step height H2, and the second step height H2 is smaller than the first step height H1.
It should be noted that, in the present embodiment, the second step height H2 is a height from the top surface of the pad oxide layer 102 to the top surface of the silicon dioxide isolation structure 106, but in other embodiments of the present invention, the second step height H2 may be directly calculated from the top surface of the semiconductor substrate 101. Since the pad oxide layer 102 is thin, the difference has little effect.
In step 5), please refer to S5 of fig. 1 and fig. 8 to 9. The remaining silicon nitride layer 103 is removed by a second silicon nitride wet etch having an etch rate of 0 a/min for silicon dioxide, i.e., the second silicon nitride wet etch does not etch or substantially does not etch silicon dioxide.
As an example, as shown in fig. 10, the first silicon nitride wet etching and the second silicon nitride wet etching are performed by a multi-groove wet etching process. In fig. 10, the multi-Tank wet method apparatus 200 has a plurality of wet tanks, wherein the first wet Tank 201, the second wet Tank 202 and the fifth wet Tank 205 are all deionized water cleaning tanks, and the third wet Tank 203 and the fourth wet Tank 204 are a first silicon nitride wet etching Tank and a second silicon nitride wet etching Tank, respectively, which are respectively denoted as Tank a and Tank B. The multi-tank wet processing apparatus 200 may perform batch processing on the wafer of the semiconductor substrate 101 in this embodiment. A plurality of wafers are placed in the wafer frame and sequentially pass through the first wet process groove 201 to the fifth wet process groove 205, so as to complete the wet etching process. According to the invention, the second step height H2 can be accurately controlled by controlling the etching time of the wafer in the third wet-method groove 203 and the fourth wet-method groove 204.
As an example, the etching Time (Tank a) of the first silicon nitride wet etching and the etching Time (Tank B) of the second silicon nitride wet etching are obtained by the following formula:
Time(Tank A)=
，（1-1）
Time(Tank B)=K*(
-
，（1-2）
in the formulas (1-1) and (1-2), THK (STI-OX) is the thickness of the silicon dioxide layer of the silicon dioxide isolation structure 106 before the first silicon nitride wet etching, as shown in fig. 7, which includes a first step height H1 and a height H0 of the remaining silicon dioxide layer in the substrate; THK (OX) is a thickness of the silicon dioxide layer of the silicon dioxide isolation structure 106 after the second silicon nitride wet etching, as shown in fig. 9, which includes a second step height H2 and a height H0 of a remaining silicon dioxide layer in the substrate; THK (SIN) is the thickness of the silicon nitride layer before the first silicon nitride wet etching, i.e. the thickness of the silicon nitride layer 103 in fig. 7; ER (Tank a-OX) is an etching rate of the first silicon nitride wet etching on the silicon dioxide layer of the silicon dioxide isolation structure 106; ER (Tank A-SIN) is the etching rate of the first silicon nitride wet etching to the silicon nitride layer 103; ER (Tank B-SIN) is the etching rate of the second silicon nitride wet etching to the silicon nitride layer 103; k is an influence factor of over etching, for example, when the amount of over etching is 20%, K =1.2.
The thickness THK (OX) = THK (STI-OX) - (ER (Tank A-OX) \8727; time (Tank A) + ER (Tank B-OX) \8727; time (Tank B)) = THK (STI-OX) -ER (Tank A-OX) \8727; time (Tank A), and the thickness THK (SIN) of the silicon nitride layer before the first silicon nitride wet etching is less than or equal to ER (Tank A-SIN) \8727, time (Tank A) + ER (Tank B-SIN) \87278727andtime (Tank B), and the formulas (1-1) and (1-2) can be obtained by combining the two formulas.
As an example, an etch rate ER (Tank a-SIN) of the first wet silicon nitride etch to the silicon nitride layer is 35-70 a/min, optionally 56 ± 3 a/min; an etch rate ER (Tank B-SIN) of the second silicon nitride wet etching to the silicon nitride layer is 35-70A/min, which may be selected to be 53.5 +/-2A/min. The first silicon nitride wet etching has an etching rate ER (Tank A-OX) of 0.5-5A/min, optionally 0.8-1.3A/min, for silicon dioxide; and the etching rate ER (Tank B-OX) of the second silicon nitride wet etching to the silicon dioxide is 0A/min. Optionally, in this embodiment, the etching rate of the silicon nitride layer is the etching rate of the silicon nitride after the product process, such as high temperature annealing.
As an example, the first silicon nitride wet etching uses a phosphoric acid solution with a temperature of 160 ℃ and a mass fraction of 85% as an etching solution, and the second silicon nitride wet etching uses a phosphoric acid solution obtained by etching a certain number of silicon nitride dummy wafers (dummy wafers) with a temperature of 160 ℃ and a mass fraction of 85% as an etching solution, that is, the phosphoric acid solution used in the first silicon nitride wet etching is a new solution that is not subjected to an over-etching treatment. FIG. 11 is a graph showing the relationship between the etching rate of phosphoric acid solution to the silicon dioxide layer and the etching amount of the silicon nitride dummy. In fig. 11, the abscissa is the number of silicon nitride dummy wafer etches and the ordinate is the etch rate of the phosphoric acid solution for the silicon dioxide layer. After the silicon nitride dummy wafers of the 1 st wafer, the 70 th wafer, the 170 th wafer, the 340 th wafer and the 500 th wafer are etched, the etching rate of the phosphoric acid solution to the silicon dioxide layer is collected, and a change curve is fitted according to data points. As can be seen in fig. 11, when the number of silicon nitride dummy wafer etches is greater than 275, the etch rate of the phosphoric acid solution for the silicon dioxide layer is already approximately 0 a/min and is closer to 0 a/min as the number of silicon nitride dummy wafer etches increases. Optionally, the silicon nitride dummy wafer is a silicon substrate wafer grown with a 2000 a silicon nitride layer.
As an example, as shown in fig. 11, the etching rate ER (Tank B-OX) of the second silicon nitride wet etching for silicon dioxide and the number x of the dummy silicon nitride etches are obtained by the following formula:
ER(Tank B-OX) = -3×10 -8 x 3 + 3×10 -5 x 2 - 0.0118x + 1.557，
i.e., the fitted curve for each data point in fig. 11 satisfies the above-equation relationship.
As an example, the wet bath performing the first silicon nitride wet etching maintains a determined etching rate of the silicon nitride layer by periodically changing the phosphoric acid solution. Since the first silicon nitride wet etch needs to maintain an etch rate for silicon dioxide, ER (Tank A-OX), of 0.5-5A/min, which may be selected to be 0.8-1.3A/min. In order to avoid the decrease of the etching rate of silicon dioxide caused by the increase of the number of etched silicon nitride, the phosphoric acid solution in the third wet tank 203 needs to be periodically replaced with acid, for example, a part of the phosphoric acid solution is replaced with a new phosphoric acid solution, so as to avoid the decrease of the etching rate of the phosphoric acid solution on silicon dioxide after a certain amount of silicon nitride is etched, as shown in fig. 11.
In this embodiment, the second step height H2 after wet etching may be accurately controlled by controlling the etching Time (Tank a) of the first silicon nitride wet etching and the etching Time (Tank B) of the second silicon nitride wet etching. For example, the etch rate ER (Tank a-SIN) of the first silicon nitride wet etch to the silicon nitride layer 103 is controlled to be 38 a/min, the etch rate ER (Tank B-SIN) of the second silicon nitride wet etch to the silicon nitride layer 103 is controlled to be 33 a/min, the etch rate ER (Tank a-OX) of the first silicon nitride wet etch to the silicon dioxide layer of the silicon dioxide isolation structure 106 is controlled to be 3 a/min, the thickness THK (SIN) of the silicon nitride layer before the first silicon nitride wet etch is 1000 a, and the impact factor K of the over-etch is 1.2. When the thickness THK (STI-OX) of the silicon dioxide layer of the silicon dioxide isolation structure 106 before the first silicon nitride wet etching is 3050 a and the thickness THK (OX) of the silicon dioxide layer of the silicon dioxide isolation structure 106 after the second silicon nitride wet etching is set to 2980 a, substituting the above conditions into formula (1-1) and formula (1-2) may result in an etching Time (Tank a) of the first silicon nitride wet etching of 23.3min and an etching Time (Tank B) of the second silicon nitride wet etching of 4.16min. By setting the etching time, the etching amount of the silicon dioxide layer in the wet etching process can be accurately controlled, so that the step height is controlled.
The invention realizes the accurate control of the step height of the shallow trench isolation structure by introducing two different wet etching processes, namely the first silicon nitride wet etching and the second silicon nitride wet etching. The first silicon nitride wet etching also has a certain etching rate for the silicon dioxide layer while etching the silicon nitride layer, and the second silicon nitride wet etching has an etching rate of 0A/min for the silicon dioxide when etching the silicon nitride layer. Before the silicon nitride wet etching is carried out, the initial step height of the shallow trench isolation structure is the first step height, and the second step height is completely determined by the etching of the silicon dioxide layer by the first silicon nitride wet etching. By respectively controlling the etching time of the first silicon nitride wet etching and the second silicon nitride wet etching, the step height required by design can be ensured, and sufficient over-etching amount can be ensured to ensure that the silicon nitride layer is thoroughly removed by the wet etching, thereby being beneficial to improving the production yield.
Example two: in this embodiment, the second step height H2 after the wet etching may be accurately controlled by controlling the etching Time (Tank a) of the first silicon nitride wet etching and the etching Time (Tank B) of the second silicon nitride wet etching. As in the example, the etch rate ER (Tank a-SIN) of the first silicon nitride wet etch to the silicon nitride layer 103 is controlled to be 38 a/min, the etch rate ER (Tank B-SIN) of the second silicon nitride wet etch to the silicon nitride layer 103 is controlled to be 33 a/min, the etch rate ER (Tank a-OX) of the first silicon nitride wet etch to the silicon dioxide layer of the silicon dioxide isolation structure 106 is controlled to be 3 a/min, the thickness THK (SIN) of the silicon nitride layer prior to the first silicon nitride wet etch is 1000 a, and the impact factor K of over-etching is 1.2. The difference from embodiment one is that when the thickness of the silicon dioxide layer THK (STI-OX) of the silicon dioxide isolation structure 106 before the first silicon nitride wet etching is 2990 a and the thickness of the silicon dioxide layer THK (OX) of the silicon dioxide isolation structure 106 after the second silicon nitride wet etching is set to 2980 a, the etching Time (Tank a) of the first silicon nitride wet etching is 3.3min and the etching Time (Tank B) of the second silicon nitride wet etching is 31.8min can be obtained by substituting the above conditions into equations (1-1) and (1-2). By setting the etching time, the etching amount of the silicon dioxide layer in the wet etching process can be accurately controlled, so that the step height is controlled.
Example three: in this embodiment, the second step height H2 after wet etching may be accurately controlled by controlling the etching Time (Tank a) of the first silicon nitride wet etching and the etching Time (Tank B) of the second silicon nitride wet etching. As in the example, the etch rate ER (Tank a-SIN) of the first silicon nitride wet etch to the silicon nitride layer 103 is controlled to be 38 a/min, the etch rate ER (Tank B-SIN) of the second silicon nitride wet etch to the silicon nitride layer 103 is controlled to be 33 a/min, the etch rate ER (Tank a-OX) of the first silicon nitride wet etch to the silicon dioxide layer of the silicon dioxide isolation structure 106 is controlled to be 3 a/min, the thickness THK (SIN) of the silicon nitride layer prior to the first silicon nitride wet etch is 1000 a, and the impact factor K of over-etching is 1.2. The difference from embodiment one is that when the thickness of the silicon dioxide layer THK (STI-OX) of the silicon dioxide isolation structure 106 before the first silicon nitride wet etching is 3020 a and the thickness of the silicon dioxide layer THK (OX) of the silicon dioxide isolation structure 106 after the second silicon nitride wet etching is set to 2980 a, the etching Time (Tank a) of the first silicon nitride wet etching is 13.3min and the etching Time (Tank B) of the second silicon nitride wet etching is 17.98min can be obtained by substituting the above conditions into equations (1-1) and (1-2). By setting the etching time, the etching amount of the silicon dioxide layer in the wet etching process can be accurately controlled, so that the step height is controlled.
In summary, the present application provides a method for manufacturing a shallow trench isolation structure, which includes the following steps: providing a semiconductor substrate; forming a patterned silicon nitride layer on the semiconductor substrate, and forming a shallow trench in the semiconductor substrate by dry etching by taking the silicon nitride layer as an etching mask; forming a silicon dioxide isolation structure in the shallow trench, wherein the height difference between the upper surface of the silicon dioxide isolation structure and the upper surface of the semiconductor substrate forms a first step height; removing part of the silicon nitride layer and part of the silicon dioxide isolation structure through first silicon nitride wet etching, wherein the first silicon nitride wet etching has a determined etching rate for silicon dioxide, the height difference between the upper surface of the remaining silicon dioxide isolation structure and the upper surface of the semiconductor substrate forms a second step height, and the second step height is smaller than the first step height; and removing the rest of the silicon nitride layer by second silicon nitride wet etching, wherein the etching rate of the second silicon nitride wet etching to silicon dioxide is 0A/min. According to the method, the etching amount of the silicon dioxide layer in the shallow trench isolation structure in the wet etching process of the silicon nitride layer is controlled by introducing two different wet etching steps, so that the step height of the shallow trench isolation structure is accurately controlled, and the production yield is improved.
The above embodiments are merely illustrative of the principles and utilities of the present application and are not intended to limit the application. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present disclosure be covered by the claims of the present application.
Claims (10)
1. A preparation method of a shallow trench isolation structure is characterized by comprising the following steps:
providing a semiconductor substrate;
forming a patterned silicon nitride layer on the semiconductor substrate, and forming a shallow trench in the semiconductor substrate by dry etching by taking the silicon nitride layer as an etching mask;
forming a silicon dioxide isolation structure in the shallow trench, wherein the height difference between the upper surface of the silicon dioxide isolation structure and the upper surface of the semiconductor substrate forms a first step height;
removing part of the silicon nitride layer and part of the silicon dioxide isolation structure through first silicon nitride wet etching, wherein the first silicon nitride wet etching has a determined etching rate for silicon dioxide, the height difference between the upper surface of the remaining silicon dioxide isolation structure and the upper surface of the semiconductor substrate forms a second step height, and the second step height is smaller than the first step height;
removing the remaining silicon nitride layer by a second silicon nitride wet etch having an etch rate for silicon dioxide of 0A/min,
the phosphoric acid solution used in the first silicon nitride wet etching is a new solution which is not subjected to etching treatment, and the phosphoric acid solution obtained after etching of a certain number of silicon nitride dummy wafers is adopted in the second silicon nitride wet etching as an etching liquid.
2. The method of claim 1, wherein the step of forming the silicon dioxide isolation structure in the shallow trench comprises the steps of:
depositing a silicon dioxide layer in the shallow trench and on the surface of the silicon nitride layer;
and taking the silicon nitride layer as a stop layer of chemical mechanical polishing, and removing the silicon dioxide layer on the surface of the silicon nitride layer by chemical mechanical polishing.
3. The method as claimed in claim 2, further comprising a step of etching back the silicon dioxide layer in the shallow trench after removing the silicon dioxide layer on the surface of the silicon nitride layer by chemical mechanical polishing.
4. The method of claim 2, wherein the step of depositing the silicon dioxide layer in the shallow trench and on the surface of the silicon nitride layer comprises chemical vapor deposition; and before depositing the silicon dioxide layer in the shallow trench and on the surface of the silicon nitride layer, forming a barrier oxide layer in the shallow trench.
5. The method of claim 1 further comprising the step of forming a pad oxide layer on the semiconductor substrate prior to forming the patterned silicon nitride layer on the semiconductor substrate.
6. The method for preparing a shallow trench isolation structure according to claim 1, wherein the etching time of the first silicon nitride wet etching and the etching time of the second silicon nitride wet etching are obtained by the following formula:
Time (Tank A) =
，
Time (Tank B) = K*( 
- 
，
in the above formula, time (Tank a) is an etching Time of a first silicon nitride wet etching, time (Tank B) is an etching Time of a second silicon nitride wet etching, THK (STI-OX) is a thickness of a silicon dioxide layer of the silicon dioxide isolation structure before the first silicon nitride wet etching, THK (OX) is a thickness of the silicon dioxide layer of the silicon dioxide isolation structure after the second silicon nitride wet etching, THK (SIN) is a thickness of the silicon nitride layer before the first silicon nitride wet etching, ER (Tank a-OX) is an etching rate of the first silicon nitride wet etching on the silicon dioxide layer of the silicon dioxide isolation structure, ER (Tank a-SIN) is an etching rate of the first silicon nitride wet etching on the silicon nitride layer, ER (Tank B-SIN) is an etching rate of the second silicon nitride wet etching on the silicon nitride layer, and K is an influence factor of over etching.
7. The method of preparing a shallow trench isolation structure according to claim 6, wherein the first wet etching of silicon nitride has an etch rate ER (Tank A-OX) for silicon dioxide of 0.5-5A/min; the etching rate ER (Tank A-SIN) of the first silicon nitride wet etching to the silicon nitride layer is 35-70A/min; and the etching rate ER (sink B-SIN) of the second silicon nitride wet etching to the silicon nitride layer is 35-70A/min.
8. The method for preparing the shallow trench isolation structure according to claim 6, wherein the first silicon nitride wet etching adopts a phosphoric acid solution with a mass fraction of 85% and a temperature of 160 ℃ as an etching solution, and the second silicon nitride wet etching adopts a phosphoric acid solution obtained by etching a certain number of silicon nitride dummy wafers with a mass fraction of 85% and a temperature of 160 ℃ as an etching solution.
9. The method as claimed in claim 8, wherein the wet tank for performing the first wet etching of silicon nitride is configured to maintain a certain etching rate of the silicon nitride layer by performing a regular liquid change on the phosphoric acid solution.
10. The method for preparing the shallow trench isolation structure according to claim 8, wherein the etching rate ER (Tank B-OX) of the second silicon nitride wet etching to silicon dioxide and the number x of the silicon nitride dummy wafer etching are obtained by the following formula:
ER(Tank B-OX) = -3×10 -8 x 3 + 3×10 -5 x 2 - 0.0118x + 1.557。
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1949472A (en) * | 2005-10-14 | 2007-04-18 | 松下电器产业株式会社 | Semiconductor device and method for producing the same |
| CN107464784A (en) * | 2016-06-03 | 2017-12-12 | 瑞萨电子株式会社 | The manufacture method of semiconductor devices |
| CN107690692A (en) * | 2015-06-10 | 2018-02-13 | 密克罗奇普技术公司 | The method for forming shallow trench isolation (STI) structure |
| CN112670233A (en) * | 2019-10-16 | 2021-04-16 | 意法半导体(鲁塞)公司 | Process for manufacturing an integrated circuit and corresponding integrated circuit |
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| US20110014726A1 (en) * | 2009-07-20 | 2011-01-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming shallow trench isolation structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1949472A (en) * | 2005-10-14 | 2007-04-18 | 松下电器产业株式会社 | Semiconductor device and method for producing the same |
| CN107690692A (en) * | 2015-06-10 | 2018-02-13 | 密克罗奇普技术公司 | The method for forming shallow trench isolation (STI) structure |
| CN107464784A (en) * | 2016-06-03 | 2017-12-12 | 瑞萨电子株式会社 | The manufacture method of semiconductor devices |
| CN112670233A (en) * | 2019-10-16 | 2021-04-16 | 意法半导体(鲁塞)公司 | Process for manufacturing an integrated circuit and corresponding integrated circuit |
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