CN115237538A - A system-on-chip simulation platform and its construction method - Google Patents

Abstract

The invention belongs to the technical field of system-on-chip simulation, and particularly relates to a system-on-chip simulation platform and a construction method thereof. The simulation platform comprises: the system comprises a bus module, a CPU bus function model unit and a system storage module. The CPU bus function model unit is connected with the bus module through an AXI interface or an AHB interface and is provided with a DPI interface; the DPI interface is used for opening tasks in the bus function model unit to the C language interface. The system memory module is connected with the AXI interface or the AHB interface. The invention virtualizes a CPU to replace a real CPU in the simulation environment of the system on a chip through the DPI, thereby not only leading a software developer to start code development as soon as possible, but also leading a hardware verifier to construct more application scenes for the chip by using the codes developed by the software developer, and achieving the purpose of verifying the chip more efficiently and more comprehensively.

Description

A system-on-chip simulation platform and its construction method

technical field

The invention relates to the technical field of system-on-chip simulation, in particular to a system-on-chip simulation platform and a construction method thereof.

Background technique

With the rapid development of the semiconductor industry, silicon has reached unprecedented levels of size, function and software complexity. In order to achieve the goal of launching the product at the expected time, it is necessary to introduce parallelism in the product development cycle and carry out simulation testing during the product development process.

In the existing development methods, there are two common simulation testing methods: building a system-on-chip simulation environment and using a CPU bus function model (Bus Function Model, BFM) to simulate the system-on-chip. However, the existing SoC simulation environment is simulated by executing C code on a real CPU. This simulation method will not be able to build and debug the SoC verification platform when the CPU IP is not imported in time. Early software development. Using the CPU bus function model BFM to build Verilog or System Verilog to stimulate the simulation of the SoC, the C language code for software development in this way cannot be directly run on the SoC simulation platform, which is not conducive to software code development and SoC application scenarios. Construct.

SUMMARY OF THE INVENTION

In order to solve the deficiencies in the prior art, the present invention proposes a system-on-chip simulation platform and a construction method thereof. The simulation platform and the construction method can virtualize a CPU through DPI to replace the real CPU in the system-on-chip simulation environment. Not only can software developers start code development as soon as possible, but also hardware verifiers can use the codes developed by software developers to build more application scenarios for the chip, so as to achieve the purpose of more efficient and comprehensive verification of the chip.

To achieve the above object, the present invention has adopted the following technical solutions:

According to a first aspect of the present invention, a system-on-chip simulation platform is provided, the simulation platform includes: a bus module, a CPU bus function model unit and a system storage module.

The bus module includes an AXI bus control unit, an AXI-AHB transfer bridge, an AHB bus control unit, an AHB-AXI transfer bridge, an APB bus control unit, an AHB-APB transfer bridge and an AXI-APB transfer bridge.

The CPU bus functional model unit is connected to the bus module through an AXI interface or an AHB interface, and the CPU bus functional model unit is provided with a DPI interface; the DPI interface is used to connect the data in the CPU bus functional model unit. The task is open to the C language interface.

The system storage module includes a static random access memory SRAM; the system storage module is connected to the AXI interface or the AHB interface.

The above aspects and any possible implementation manners further provide an implementation manner, wherein the CPU bus function model unit is generated by using the System Verilog language.

According to the above aspect and any possible implementation manner, an implementation manner is further provided, wherein the AXI bus control unit, the AHB bus control unit and the APB bus control unit all include a master port and a slave port.

The above aspects and any possible implementations further provide an implementation, the CPU bus function model unit, which uses write_bus and read_bus tasks to operate the bus module, uses delay_cyc as a delay task, adopts main_thread as the entry task.

The above aspects and any possible implementation manners further provide an implementation manner, wherein the C language interface completes operations on the bus module by calling the tasks of write_bus, read_bus, delay_cyc and main_thread.

The above-mentioned aspect and any possible implementation mode further provide an implementation mode, the bus module is connected with a plurality of IPs, and the main_thread task is used to access the register of the device connected to the bus module, or after the system memory module is initialized For use with devices connected to the bus module.

According to a second aspect of the present invention, a method for constructing the above-mentioned system-on-chip simulation platform is provided, the method comprising:

(1) Build a bus module.

(2) Using the System Verilog language to generate the CPU bus functional model unit, and connect the CPU bus functional model unit with the bus module through the AXI interface or the AHB interface.

(3) The static random access memory SRAM is used to construct the system memory module, and the system memory module is connected with the slave of the AXI interface or the AHB interface.

(4) Use the DPI interface to connect the CPU bus functional model unit with the C language interface, so that the tasks in the CPU bus functional model unit are opened to the C language interface, and the C language interface calls the write_bus, read_bus, delay_cyc and main_thread tasks to complete the bus module. operate.

The above-mentioned aspects and any possible implementation manners further provide an implementation manner, the method further includes constructing a test case, instantiating a bus module, a CPU bus functional model unit and a system memory module, and generating a clock and a reset task.

Compared with the prior art, the present invention has the following beneficial effects:

The present invention virtualizes a CPU through DPI to replace the real CPU in the system-on-chip simulation environment of the chip, so that not only software personnel can develop codes as soon as possible, but also hardware verification personnel can use the codes developed by software personnel to build more chips for the chip. It can achieve the purpose of more efficient and comprehensive verification of the chip.

Description of drawings

1 is a schematic diagram of a system-on-chip simulation platform in the present invention;

Fig. 2 is the structural block diagram of the system-on-chip simulation platform in the present invention;

FIG. 3 is a flowchart of a method for constructing a system-on-chip simulation platform in the present invention.

in:

110, bus module, 120, CPU bus function model unit, 130, AHB interface, 140, AXI interface, 150, system memory module, 160, C language interface.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In addition, the term "and/or" in this article is only an association relationship to describe the associated objects, indicating that there can be three kinds of relationships, for example, A and/or B, it can mean that A exists alone, A and B exist at the same time, There are three cases of B alone. In addition, the character "/" in this document generally indicates that the related objects are an "or" relationship.

The present invention virtualizes a CPU through DPI to replace the real CPU in the system-on-chip simulation environment of the chip, so that not only software personnel can develop codes as soon as possible, but also hardware verification personnel can use the codes developed by software personnel to build more chips for the chip. It can achieve the purpose of more efficient and comprehensive verification of the chip.

FIG. 1 shows a schematic diagram of a system-on-chip simulation platform in the present invention, and FIG. 2 shows a structural block diagram of the system-on-chip simulation platform. The simulation platform includes: a bus module 110 , a CPU bus function model unit 120 and a system storage module 150 .

The bus module 110 includes an AXI bus control unit, an AXI-AHB switching bridge, an AHB bus control unit, an AHB-AXI switching bridge, an APB bus control unit, an AHB-APB switching bridge and an AXI-APB switching bridge. The bus module 110 is connected with a plurality of IPs, and the main_thread task is used to access the registers of the device connected to the bus module, or the system memory module is initialized for use by the device connected to the bus module. The AXI bus control unit is 4*4, including 4 master ports and 4 slave ports. The switching bridge of the AXI-AHB is 4*4, including 4 master ports and 4 slave ports. The APB bus control unit includes 4 slave ports.

The CPU bus function model unit 120 is connected to the bus module 110 through the AXI interface 140 or the AHB interface 130 , and the CPU bus function model unit 120 is provided with a DPI interface. The tasks in the BFM of the CPU are opened to the C language interface 160 through the DPI interface. The C language can directly call main_thread and internally call write_bus and read_bus to complete the bus operation, and call delay to complete the delay task.

The CPU bus function model unit 120 is a virtual CPU, which uses write_bus and read_bus tasks to operate the bus module 110, uses delay_cyc as a delay task, and uses main_thread as an entry task. The C language interface completes the operation of the bus module by calling the tasks of write_bus, read_bus, delay_cyc and main_thread.

The system storage module 160 includes a static random access memory SRAM; the system storage module 160 is connected to the AXI interface 140 or the AHB interface 130 .

The invention virtualizes a CPU through DPI to replace the real CPU in the system-on-chip simulation environment, so that the software personnel can start code development as soon as possible, and the hardware verification personnel can also use the codes developed by the software personnel to build more application scenarios for the chip. To achieve the purpose of more efficient and more comprehensive verification of the chip.

On the one hand, the purpose of the present invention is to introduce more parallelism in the chip development process, including the parallelism of system-on-chip simulation and design integration, the parallelism of software development and system-on-chip simulation verification, and the like. On the other hand, it can be combined with software applications to add more system-level behaviors in the SoC simulation stage, which is convenient for software development to use SoC simulation and debugging when encountering problems, and it is convenient for hardware to cover more application scenarios.

FIG. 3 shows a flowchart of a method 300 for constructing a system-on-chip simulation platform.

At block 310, a bus module is constructed. The master port and slave port of the bus module can be connected to different IPs. In the task main_thread, the register access to the connected IP can be completed, and the content of the static random access memory SRAM can be initialized for the connected IP to use.

At block 320, the CPU bus functional model unit is generated using the System Verilog language, and the CPU bus functional model unit is connected with the bus module through the AXI interface or the AHB interface. The CPU bus function model unit creates a CPU BFM through SystemVerilog, has a set of AXI or AHB bus interfaces to connect with the bus system, abstracts the operation of the bus module into two tasks of write_bus and read_bus, and adds a delay_cyc as a delay task, add a CPU entry task main_thread to build other tasks required by the C language.

At block 330, a system memory module is constructed using static random access memory (SRAM), and the system memory module is connected to the slave of the AXI interface or the AHB interface.

At block 340, the DPI interface is used to connect the CPU bus functional model unit with the C language interface, so that the tasks in the CPU bus functional model unit are exposed to the C language interface, and the C language interface calls the write_bus, read_bus, delay_cyc and main_thread tasks to complete the bus module operation.

At block 350, a test case is constructed, the bus module, the CPU bus functional model unit, and the system memory module are instantiated, and clock and reset tasks are generated. Hardware verifiers and software developers can build C language test cases at the same time.

The simulation environment of the present invention is simple, and does not require a series of processes of compiling C language into hex and a related cross-compilation environment, and only needs to compile C language into a relevant shared library. Software development and hardware verification personnel can perform the simulation of existing IP and software code development when there is no real CPU, and it is beneficial to shorten the entire chip development cycle by starting the work as early as possible. The present invention can better reproduce the problem. When the tasks in the BFM of the CPU are rich enough to cover all situations of software development, the software and hardware can develop use cases on one platform at the same time. The hardware emulation platform is reproduced. In addition, hardware verifiers can better use rich software libraries to cover more system-level application scenarios, and to discover and solve possible hidden problems in the system as soon as possible.

The above-mentioned embodiments are only to describe the preferred embodiments of the present invention, and do not limit the scope of the present invention. On the premise of not departing from the design spirit of the present invention, those of ordinary skill in the art can make various Variations and improvements should fall within the protection scope determined by the claims of the present invention.

Claims (8)

1. A system-on-chip simulation platform, comprising: the system comprises a bus module, a CPU bus function model unit and a system storage module;

the bus module comprises an AXI bus control unit, an AXI-AHB transfer bridge, an AHB bus control unit, an AHB-AXI transfer bridge, an APB bus control unit, an AHB-APB transfer bridge and an AXI-APB transfer bridge;

the CPU bus function model unit is connected with the bus module through an AXI interface or an AHB interface and is provided with a DPI interface; the DPI interface is used for opening the tasks in the CPU bus functional model unit to a C language interface;

the system storage module comprises a Static Random Access Memory (SRAM); the system memory module is connected to the AXI interface or the AHB interface.

2. The System-on-chip simulation platform of claim 1, wherein the CPU bus functional model unit is generated using a System Verilog language.

3. The system-on-chip emulation platform of claim 1, in which the AXI bus control unit, the AHB bus control unit, and the APB bus control unit each comprise a master port and a slave port.

4. The system-on-chip emulation platform of claim 1, in which the CPU bus functionality model unit operates the bus module using write _ bus and read _ bus tasks, delay _ cyc as a latency task, and main _ thread as an entry task.

5. The SOC emulation platform of claim 4, wherein the C language interface completes the operation of the bus module by invoking the write _ bus, read _ bus, delay _ cyc, and main _ thread tasks.

6. The system-on-chip emulation platform of claim 1, wherein the bus module has multiple IPs attached thereto, and wherein a main thread task is used to access registers of a device attached to the bus module or to initialize the system memory module for use with the device attached to the bus module.

7. The method for constructing a system-on-chip simulation platform according to any one of claims 1 to 6, comprising:

(1) Constructing a bus module;

(2) Generating a CPU bus function model unit by adopting a System Verilog language, and connecting the CPU bus function model unit with a bus module through an AXI interface or an AHB interface;

(3) A system memory module is constructed by adopting a Static Random Access Memory (SRAM), and is connected with an AXI interface or a slave of an AHB interface;

(4) And the CPU bus function model unit is connected with the C language interface by adopting a DPI interface, so that tasks in the CPU bus function model unit are opened to the C language interface, and the C language interface calls write _ bus, read _ bus, delay _ cyc and main _ thread tasks to complete the operation on the bus module.

8. The method of claim 7, further comprising building test cases, instantiating bus modules, CPU bus functional model units and system memory modules, and generating clock and reset tasks.

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