CN118313325A - A design method for CMU simulator of onboard computer based on QEMU virtual environment - Google Patents

Abstract

The present invention discloses a design method of a satellite computer CMU simulator based on a QEMU virtual environment, the method comprising: a) customizing a QEMU system simulator of a SPARC architecture; b) simulating a processor chip of a SPARC V8 architecture to simulate a real operating environment of satellite embedded software; c) simulating a peripheral IO controller interface chip of a CMU simulator to implement satellite control subsystem joint debugging and other design steps. Compared with the prior art, the present invention has better reusability and rapid construction, stronger controllability, and more abundant debugging and testing means, high performance, flexibility and real-time guarantee. By simulating the satellite computer CMU hardware device, loading the real satellite embedded software in the virtual CPU to simulate the real satellite state, the real operating environment of the satellite embedded software can be simulated more realistically, greatly reducing the risk and cost of hardware testing, and has good application prospects and commercial value.

Description

A design method for CMU simulator of onboard computer based on QEMU virtual environment

Technical Field

The invention relates to the technical field of virtual satellite testing, in particular to a design method of a satellite-borne computer CMU simulator based on a QEMU virtual environment.

Background technique

With the rapid development of aerospace technology, satellite missions have become increasingly complex. Traditional hardware-based onboard embedded software testing methods are difficult to build, expensive, have long testing cycles, and are difficult to monitor operating status, which has great limitations. At present, the aerospace field’s hardware testing improvement solutions include semi-physical simulation testing and full-digital simulation testing, but the test controllability of semi-physical simulation is not as good as that of a full-digital simulation environment. The onboard computer CMU simulator refers to a software-based simulation of a real onboard computer CMU hardware device on a host platform, providing a simulation execution environment for onboard embedded software, so that the binary code used for solidification can run directly on the onboard computer CMU simulator, representing the same functional characteristics as the real hardware. The simulation of onboard computer CMU hardware devices relies on system-level virtual simulation technology.

At present, typical system-level solutions on the market include Bochs developed by Kevin Lawton, ARMulator developed by ARM, Simics developed by Wind River, SkyEye developed by Tsinghua University team, and QEMU (Quick Emulator) originally developed and open-sourced by French engineer Fabrice Bellard. QEMU's flexibility, cross-platform support, multi-architecture instruction set simulation, hardware device simulation, and active support from the open source community make it a powerful technical support in the field of virtualization, simulation, and emulation. At present, many system-level virtualization solutions at home and abroad are implemented based on QEMU.

The existing virtual satellite testing hardware technology is incomplete, and has problems such as high testing cost, long testing cycle and difficult monitoring of operating status.

Summary of the invention

The purpose of the present invention is to provide a method for designing a satellite computer CMU simulator based on a QEMU virtual environment in view of the deficiencies in the prior art. The method adopts a method of loading real satellite embedded software in a virtual CPU to design a SPARC architecture satellite computer CMU simulator. The method is based on software simulation of the satellite computer central management unit CMU, and includes two key parts: one is to provide an instruction set simulator to realize the translation of the satellite computer SPARC architecture instruction set to the host machine x86 instruction set; the second is to realize the simulation of the hardware operating environment of the satellite embedded software; and the third is to complete the satellite control subsystem joint debugging design. The present invention simulates the satellite computer CMU hardware equipment and loads real satellite embedded software in the virtual CPU to simulate the real satellite state, which is of great significance for virtual satellite testing. Compared with the satellite model that directly shields the real hardware interaction interface, this method can more realistically simulate the real operating environment of the onboard embedded software; compared with the hardware-based test platform, this method has better reusability and rapid construction, can greatly reduce the risk and cost of hardware testing, and at the same time has stronger controllability and more abundant debugging and testing methods; compared with other satellite digital simulation solutions, this method has the advantages of high performance, flexibility and real-time guarantee. The present invention has good application prospects and commercial value.

The specific technical solution for achieving the purpose of the present invention is: a method for implementing a CMU simulator for a spaceborne computer based on a QEMU virtual environment, which is characterized by adopting a method of loading real spaceborne embedded software in a virtual CPU to produce an effect consistent with running in real hardware. The specific design of the CMU simulator for a spaceborne computer based on a SPARC architecture includes the following steps:

Step 1: Configure the QEMU environment, customize the QEMU system simulator for the SPARC architecture, and build a virtual test environment;

Step 2: Simulate the SPARC V8 architecture processor chip and simulate the real operating environment of the onboard embedded software;

Step 3: Simulate the CMU simulator peripheral IO controller interface chip, integrate the CMU module, and realize the satellite control subsystem joint debugging design.

The step 1 specifically includes: deploying a virtual target machine based on the virtualization platform QEMU; building a SPARC cross-compilation environment, and generating executable code running on a SPARC architecture target machine on an x86_64 architecture host machine.

The specific steps of deploying the virtual target machine are as follows:

Step 01. Install the basic libraries and tools required for QEMU compilation in the host operating system.

Step 02. Set QEMU configuration items based on configure.

Step 03. Compile and install the virtual target machine in parallel to the system environment.

The step 2 specifically includes: simulating on-chip peripherals such as an interrupt controller, a timing unit, and a serial port of a SPARC V8 architecture processor chip, and building a SPARC V8 architecture processor chip Machine.

The specific steps of simulating the SPARC V8 architecture processor chip interrupt controller are as follows:

Step 01. Register interrupt handling events in the QEMU main event loop, detect interrupt signals at the end of each translation block executed by the processor, and once an interrupt is detected, respond immediately and start the corresponding interrupt handler, with the program counter pointing to the starting address of the corresponding interrupt handler.

Step 02. Based on the hardware block diagram and hardware data description of the interrupt controller of the SPARC V8 architecture processor chip, design a virtual interrupt controller to implement functions including: access control of the hardware registers of the interrupt controller IO space, receiving interrupt requests generated by interrupt sources, interrupt arbitration, reporting interrupts, responding to interrupts, and clearing interrupts. The details are as follows:

ⅰ. Based on the QOM design pattern, design the virtual interrupt controller device structure, including: mounted system bus objects, memory mapped IO areas, interrupt request status information and interrupt request signals.

ⅱ. Register the virtual interrupt controller device model to the QEMU system. Specifically, it includes: setting a unique identifier for the virtual interrupt controller device QOM model; providing a virtual interrupt controller device class initialization interface and an instance initialization interface; and implementing the registration of the virtual interrupt controller reset interface.

The specific steps of simulating the timing unit of the SPARC V8 architecture processor chip are as follows:

Step 01. Based on the hardware block diagram and hardware data description of the timing unit of the SPARC V8 architecture processor chip, design a virtual timing unit to implement functions including: access control of timing unit registers, timer clock simulation, and timer interrupt simulation.

The specific steps of designing the virtual timing unit are as follows:

ⅰ. Implement access control of the timing unit register based on the memory-mapped IO area, allocate space consistent with the hardware scale, and map it to a specific location in the system bus space according to the hardware description, so that the memory-mapped IO area is addressable on the system bus.

ⅱ. Based on QEMU's ptimer mechanism, the timer is initialized to complete the timer clock simulation. In the timing unit, each tick pulse generated by the prescaler is not accurately simulated, only the scaler is maintained, and the clock frequency of the four timers and one watchdog that share the prescaler is set to CLK/(scaler+1). Among them, CLK is the CPU clock frequency.

ⅲ. When the timer underflows, the corresponding timer interrupt handler is executed; if the watchdog times out and the dog is not fed, a system reset signal is generated. Design a timer expiration callback function to implement timer interrupt simulation.

Step 02. Add the timer event to the listener list in the QEMU main event loop to complete the timer unit initialization.

Step 03. Start the timer and then start the timer timing process.

The specific steps of simulating the serial port of the SPARC V8 architecture processor chip are as follows:

Step 01. Allocate and bind a character device in the form of a file descriptor to the serial port device.

Step 02. Control the interruption and data transmission of the character device by reading and writing access control to the control register, status register and data register of the serial port device.

Step 03. Register the corresponding file descriptor's listening event in the QEMU main event loop. When a readable or writable event occurs on the character device file descriptor, receive and send data operations are performed according to the specific character device.

Step 04. Realize the function of sending data through the serial port device.

Step 05. Realize the function of receiving data on the serial port device.

The specific steps of constructing the SPARC V8 architecture processor chip Machine are as follows:

Step 01. Specify the SPARC V8 architecture processor chip. The default CPU type of Machine is LEON3.

Step 02. Based on the support provided by QEMU for LEON3 CPU, design the callback function to be executed when the CPU responds to an interrupt and implement the corresponding processing logic.

Step 03. Allocate the storage space address of the SPARC V8 architecture processor chip, including PROM, RAM, IO and other areas;

Step 04. Design your own Bootloader and load it into the ROM area of the SPARC V8 architecture processor chip memory.

Step 05. After the CPU is powered on, it starts to execute the Bootloader startup program, completes the initialization of the on-chip devices of the SPARC V8 architecture processor chip (optional), and then jumps to the entry address of the RAM area.

Step 06. Load the onboard embedded software into the RAM area entry address in the form of kernel.

Step 07. Set the CPU stack pointer according to the user-specified memory area size, specifically initialized to the RAM area first address + user-specified RAM size.

Step 08. Complete the registration and instantiation of the SPARC V8 architecture processor chip interrupt controller, timing unit, and serial port device, connect each on-chip device to the system bus SysBus, and map the IO address space allocated to each device to the memory space.

Step 09. Use GPIO input and output lines to abstract the input and output pin properties of hardware devices; devices are connected to each other through GPIO lines; the triggering of signals on the hardware is designed in the software to monitor the occurrence of an event and execute the corresponding callback function.

The step 3 specifically includes: simulating the CMU simulator peripheral IO controller interface chip; integrating the CMU module to realize the satellite control subsystem joint debugging design.

The specific steps of the simulated CMU simulator peripheral IO controller interface chip design are as follows:

Step 01. Based on the system bus device, the peripheral IO controller interface device xxxDevice is abstracted. The 80-channel GPIO ports, 16-channel asynchronous serial ports, 10-channel synchronous serial ports, star time module and other devices in the peripheral IO controller interface chip structure are inherited to this structure, and finally each device is registered to the peripheral IO controller interface chip.

Step 02. Design an interface for data exchange between the CMU module and other peripheral hardware simulators that provide the target data environment. Consider factors such as transmission rate, resource utilization, and code reusability to select a shared memory solution. Specifically, use the POSIX interface mmap under the Linux system to implement it.

The satellite control subsystem specifically includes a central management unit CMU, a remote control and telemetry unit TTU, sensors, actuators, dynamic models, etc. To complete the entire control subsystem test in a virtual environment, it is necessary to build simulators for each component. The SPARC architecture processor chip and the peripheral IO controller interface chip based on QEMU simulation implemented by the present invention serve as CMU simulators in the entire control subsystem of the spacecraft. The specific steps for implementing the satellite control subsystem joint debugging design are as follows:

Step 01. According to the onboard software control cycle, the peripheral hardware simulator and CMU simulator that provide the target data environment are synchronously controlled.

The specific steps of the synchronous control are as follows:

ⅰ. When starting the CMU simulator, start the Monitor in blocking mode and add the "-S" option so that after the virtual machine is initialized, the VCPU thread blocks and waits before the first instruction is executed.

ⅱ. When the peripheral hardware simulator that provides the target data environment is initialized, the Monitor is connected, and the CMU simulator starts to perform initialization work and stops before the first instruction is executed.

ⅲ. In each control cycle of the target data environment simulator, first send a cont command to the Monitor to resume running the CMU simulator.

ⅳ. The target data environment simulator sleeps for 64ms based on the host machine clock, and then sends a stop command to the Monitor to stop running the CMU simulator.

Step 02. The onboard software completes the task scheduling within a control cycle and generates thrust pulse data.

Step 03. The target data environment simulator completes the dynamics simulation and continues to generate data excitation to the CMU.

Step 04. Execute the loop to complete the closed-loop joint debugging of the entire control subsystem.

Compared with the prior art, the present invention has the following beneficial technical effects and significant technical progress:

1) Compared with the satellite model that directly shields the real hardware interaction interface, the present invention can simulate the real operating environment of the satellite-borne embedded software more realistically.

2) Compared with the hardware-based test platform, the present invention has better reusability and rapid construction, can greatly reduce the risk and cost of hardware testing, and has stronger controllability and more abundant debugging and testing methods.

3) Compared with other satellite digital simulation solutions, this invention has the advantages of high performance, flexibility and real-time performance, and is suitable for the simulation and testing needs of various onboard computers. By taking advantage of QEMU, a fast and efficient onboard computer simulation environment is provided; the simulation control interface allows users to customize the simulation process as needed to adapt to different application scenarios; the simulator is synchronized with the actual hardware to ensure the accuracy and real-time performance of the simulation results.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a flow chart of the present invention;

FIG2 is a model structure diagram of a virtual interrupt controller of a SPARC V8 architecture processor chip;

FIG3 is a diagram showing the structure of a virtual independent clock model used by a timing unit of a SPARC V8 architecture processor chip;

FIG4 is a block diagram of the minimum system-on-chip of a SPARC V8 architecture processor chip;

FIG5 is a diagram showing the connection relationship between the hardware devices of the SPARC V8 architecture processor chip;

FIG6 is a schematic diagram of the satellite control subsystem data flow;

FIG7 is an architectural diagram of the satellite control subsystem virtual environment.

Detailed ways

The present invention is further described in detail below in conjunction with specific examples and drawings. The processes and methods for implementing the present invention, except for the contents specifically mentioned below, are common knowledge and common common sense in the art and are not particularly limited by the present invention.

Example 1

Referring to FIG. 1 , the present invention provides a method for implementing a CMU simulator of a satellite computer based on a QEMU virtual environment, specifically comprising the following steps:

Step 1: Configure the QEMU environment, customize the QEMU system simulator for the SPARC architecture, and build a virtual test environment.

Install the basic libraries and tools required for QEMU compilation in the host operating system, including: providing the basic tool build-essential required for software compilation; the tool pkg-config used to check the version information of the installed libraries on the system to help QEMU find the correct version of the external library when compiling; providing libglib2.0-dev of the GLib library to ensure that the GLib library can be correctly linked when QEMU is compiled. Set the QEMU configuration items based on configure, set the "target-list" parameter to "sparc-softmmu", specify the target machine instruction set architecture as SPARC, and based on the system state mode under the QEMU virtualization platform; add the configuration item "--enable-debug" to allow debugging of QEMU. Use the command "make -j4" for parallel compilation; use the command "make install" to install the virtual target machine to the system environment.

Step 2: Simulate the SPARC V8 architecture processor chip and simulate the real operating environment of the onboard embedded software. Specifically, it includes the simulation of the SPARC V8 architecture processor chip interrupt controller, timing unit, serial port and other on-chip peripheral devices and the construction of the SPARC V8 architecture processor chip Machine.

Step 3: Simulate the CMU simulator peripheral IO controller interface chip to realize the satellite control subsystem joint debugging design. The simulation of the peripheral IO controller interface chip includes the simulation of 80 GPIO ports, 16 asynchronous serial ports, 10 synchronous serial ports, satellite time and other modules. Through the shared memory solution, the QEMU instruction set simulation kernel can improve the efficiency of peripheral IO space reading and writing simulation.

Referring to FIG. 2 , the functions of the virtual interrupt controller of the SPARC V8 architecture processor chip designed by the present invention include: access control of the hardware registers of the IO space, receiving interrupt requests generated by the interrupt source, interrupt arbitration, reporting interrupts, responding to interrupts, clearing interrupts, etc. The device structure of the interrupt controller of the SPARC V8 architecture processor chip simulated by the present invention is based on the QOM design mode, and is composed of a mounted system bus object, a memory-mapped IO area, interrupt request status information, and an interrupt request signal.

The specific implementation steps of the SPARC V8 architecture processor chip virtual interrupt controller are as follows:

Step 01. Design a virtual interrupt controller that inherits from the system bus device SysBusDvice and directly mounts the on-chip interrupt controller of the SPARC V8 architecture processor chip to the system bus.

Step 02. Design the access control of the virtual interrupt controller registers to rely on the memory mapped IO area and allocate the memory mapped area for the registers of the interrupt controller.

Step 03. Register a read/write callback function for the memory-mapped IO area described in step 02, and simulate the read/write access control logic for the four registers of the interrupt mask and priority controller, interrupt pending register, forced interrupt register, and interrupt clear register.

Step 04. The interrupt request status information is maintained in the VICIRQState structure, including: the interrupt level bitmap ilevel of the 15 interrupt sources, the interrupt mask bitmap imask, the interrupt suspension bitmap ipend, the interrupt force bitmap iforce, and the interrupt clear bitmap iclear.

Step 05. Use IRQState to simulate the interrupt request signal, design a function pointer to point to the callback function when the interrupt source triggers the interrupt, and provide a function interface to the outside to implement the processing of the interrupt signal.

In QEMU simulation, the interrupt signal is detected at the end of the execution of each translation block. Once an interrupt is detected, it will immediately respond and start the corresponding interrupt handler to ensure timely response and effective processing of the interrupt. When an interrupt request is generated, if the interrupt is not masked, it will detect whether it is a forced interrupt. If not, the interrupt will be suspended. All suspended interrupts and forced interrupts will be forwarded to the priority selector. The priority selector will select the interrupt with the highest interrupt number at the high priority level. If there is no suspended interrupt at the high priority level, the suspended interrupt with the highest interrupt number at the low priority level will be selected and forwarded to the CPU. When the CPU receives the interrupt request signal sent by the interrupt controller, it will respond to the interrupt, and the interrupt controller will clear the interrupt. If it is a forced interrupt, the forced interrupt will be cleared. Otherwise, the corresponding suspended interrupt will be cleared.

Refer to Figure 3. The virtual timer (virtual independent clock) used by the timing unit of the SPARC V8 architecture processor chip is closely related to the application of the internal clock source of the virtual processor VCPU. The ptimer mechanism provided by QEMU can establish a connection between the timer and the internal clock source of the CPU. When simulating the timing unit, each tick pulse generated by the prescaler is not accurately simulated, and only the scaler factor is maintained. The four timers and the watchdog are each bound to a ptimer to perform the underlying counting operation. The operation of the timer is ultimately equivalent to the operation of the ptimer. After the timer is initialized, it is added to the listening list in the QEMU main event loop. If the timer has expired, the timer expiration callback function will report the corresponding timer interrupt to the interrupt controller. If the current expired timer is in the loop counting mode, it is necessary to use the interface function timer_mod provided by QEMU to re-count.

The specific implementation steps of the present invention to simulate the serial port device are as follows:

Step 01. Allocate and bind a character device in the form of a file descriptor to the serial port device.

Step 02. Control the interruption and data transmission of the character device by reading and writing access control to the control register, status register and data register of the serial port device.

Step 03. Register the corresponding file descriptor's listening event in the QEMU main event loop. When a readable or writable event occurs on the character device file descriptor, receive and send data operations are performed according to the specific character device.

Step 04. Implement the function of sending data from the serial port device. After writing byte data to the serial port data register, determine whether the character device connected to the serial port model is in an available state. If it is available, determine whether the send bit of the serial port control register is enabled. If it is enabled, send a byte of data through the character device. After writing is completed, determine whether the corresponding bit of the mask register in the interrupt controller is enabled. If it is enabled, send an interrupt pulse to the interrupt controller. If the character device is not available or the send bit of the serial port control register is not enabled, the data sending operation is masked.

Step 05. Implement the function of receiving data by the serial port device. When the serial port model receives external data, the QEMU event main loop will continuously poll according to the IOCanReadHandler callback function bound to the character device to determine whether the serial port can receive data. If it can, it will call the IOReadHandler callback function xxx_uart_receive bound to the character device to process the specific data receiving logic. In the specific implementation, a FIFO buffer is designed to store the received data. After receiving the data, the FIFO needs to modify the Data Ready bit in the status register to notify the program that the data has been received. If the receive interrupt flag bit in the serial port control register is enabled, the serial port will also send an interrupt signal to request data reception interrupt processing.

Referring to FIG. 4 , the minimum system-on-chip of the SPARC V8 architecture processor chip designed by the present invention, the specific steps of constructing the SPARC V8 architecture processor chip Machine are as follows:

Step 01. Specify the SPARC V8 architecture processor chip. The default CPU type of Machine is LEON3.

Step 02. Based on the support provided by QEMU for LEON3 CPU, design the callback function to be executed when the CPU responds to an interrupt and implement the corresponding processing logic.

Step 03. Allocate the storage space address of the SPARC V8 architecture processor chip, including PROM, RAM, IO and other areas.

Step 04. Design your own Bootloader and load it into the ROM area of the SPARC V8 architecture processor chip memory.

Step 05. After the CPU is powered on, it starts executing the Bootloader startup program, completes the initialization of the on-chip devices of the SPARC V8 architecture processor chip (optional), and then jumps to the entry address of the RAM area.

Step 06. Load the onboard embedded software into the RAM area entry address in the form of kernel.

Step 07. Set the CPU stack pointer according to the user-specified memory area size, specifically initialized to the RAM area first address + user-specified RAM size.

Step 08. Complete the registration and instantiation of the SPARC V8 architecture processor chip interrupt controller, timing unit, and serial port device as described in claim 3; mount each on-chip device on the system bus SysBus; and map the IO address space allocated for each device to the memory space.

Step 09. Use GPIO input and output lines to abstract the input and output pin properties of hardware devices.

Referring to Figure 5, the devices are connected to each other through GPIO lines. The triggering of the signal on the hardware is designed in the software to monitor the occurrence of a certain event and execute the corresponding callback function. When starting the CMU simulator, the user can use the "-M" option to specify the Machine on which the onboard embedded software to be tested runs. In the present invention, a unique identifier is set for the SPARC V8 architecture processor chip Machine.

The peripheral IO controller interface chip is used for data transmission between the entire control subsystem devices of the spacecraft, and is specifically composed of 80 GPIO ports, 16 asynchronous serial ports, 10 synchronous serial ports, star time and other modules. The idea of high modularity is adopted in the simulation process, and the IO interface device xxxDevice is abstracted based on the system bus device SysbusDevice. The devices contained in the peripheral IO interface chip are all inherited to this structure and finally registered to the peripheral IO interface chip. A unified data processing interface is provided in xxxDevice and instantiated during the simulation of specific components. The present invention facilitates the expansion of peripheral IO interface devices, and other devices can be conveniently registered on the peripheral IO interface chip without changing the existing model. When designing the data interaction interface, the present invention proposes a shared memory solution, which can effectively improve the efficiency of the QEMU instruction set simulation kernel in reading and writing peripheral IO space.

Referring to Figure 6, the present invention integrates the CMU module and completes the satellite control subsystem joint debugging design, wherein the satellite control subsystem specifically includes the central management unit CMU, the remote control and telemetry unit TTU, the sensor, the actuator and the dynamic model. To complete the entire control subsystem test in a virtual environment, it is necessary to build simulators for each component.

Referring to FIG. 7 , the SPARC architecture processor chip and the peripheral IO controller interface chip based on QEMU simulation implemented by the present invention are used as CMU simulators in the entire control subsystem of the spacecraft. Three peripheral IO interface chips are mounted on the SPARC V8 architecture processor chip, which are used as PM board, IO1 board, and IO2 board respectively, and the memory mapping base addresses are 0x20000000, 0x20300000, and 0x20400000 respectively. The data path of each peripheral device is connected to a certain hardware interface of which peripheral IO interface chip according to the design of the specific model, including: GPIO port, asynchronous serial port, synchronous serial port, etc. The data interaction interface between the peripheral IO interface chip and the peripheral hardware simulator is realized using shared memory.

The specific steps of the satellite control subsystem joint debugging design are as follows:

Step 01. According to the onboard software control cycle, the peripheral hardware simulator and CMU simulator that provide the target data environment are synchronously controlled.

Step 02. The onboard software completes the task scheduling within a control cycle and generates thrust pulse data.

Step 03. The target data environment simulator completes the dynamics simulation and continues to generate data excitation to the CMU;

Step 04. Execute the loop to complete the closed-loop joint debugging of the entire control subsystem.

The specific implementation steps of the synchronous control are as follows:

Step 01. When starting the CMU simulator, start Monitor in blocking mode and add the "-S" option so that after the virtual machine is initialized, the VCPU thread blocks and waits before the first instruction is executed.

Step 02. When the peripheral hardware simulator that provides the target data environment is initialized, connect the Monitor, the CMU simulator starts to perform initialization work, and stops before the first instruction is executed.

Step 03. In each control cycle of the target data environment simulator, first send a cont command to Monitor to resume running the CMU simulator.

Step 04. The target data environment simulator sleeps for 64ms based on the host machine clock, and then sends a stop command to the Monitor to stop running the CMU simulator.

The above is only a further explanation of the present invention and is not intended to limit this patent. Any equivalent implementation of the present invention should be included in the scope of the claims of this patent.

Claims (8)

1. A design method of a satellite-borne computer CMU simulator based on a QEMU virtual environment is characterized in that a method of loading real satellite-borne embedded software in a virtual CPU is adopted to design the satellite-borne computer CMU simulator of a SPARC architecture, and the specific design comprises the following steps:

Step 1: configuring a QEMU environment, customizing a QEMU system simulator of an SPARC architecture, and building a virtual test environment;

step 2: simulating a SPARC V8 architecture processor chip, simulating a real running environment of satellite-borne embedded software, wherein the simulation of the SPARC V8 architecture processor chip comprises the following steps: simulation of an interrupt controller, a timing unit and serial on-chip peripheral equipment, construction of a SPARC V8 architecture processor chip Machine and integration of a CMU module;

Step 3: the simulation of the peripheral IO controller interface chip of the simulation CMU simulator realizes satellite control subsystem joint debugging and realizes the design of the satellite-borne computer CMU simulator, and the simulation of the peripheral IO controller interface chip comprises the following steps: simulation of 80 GPIO ports, 16 asynchronous serial ports, 10 synchronous serial ports and a satellite-time module.

2. The method for designing the on-board computer CMU simulator based on the QEMU virtual environment of claim 1, wherein the step 1 specifically comprises: deploying a virtual target machine based on a QEMU of a virtualization platform, constructing a SPARC cross compiling environment, and generating executable codes running on the SPARC framework target machine on a host machine of an x86_64 framework;

The specific deployment of the virtual target machine is as follows:

step 1-1: installing a basic library and tools required by QEMU compiling in a host operating system;

step 1-2: setting a QEMU configuration item based on configuration;

step 1-3: and compiling and installing the virtual target machine to the system environment in parallel.

3. The method for designing the on-board computer CMU simulator based on the QEMU virtual environment according to claim 1, wherein the specific design of the processor chip of the simulation SPARC V8 architecture in the step 2 is as follows:

step 2-1: designing an interrupt controller of a processor chip with a simulation SPARC V8 architecture to process interrupt requests from various internal and external interrupt sources, and selecting the interrupt request with the highest priority through priority arbitration to send to a processor;

Step 2-2: designing a simulation SPARC V8 architecture processor chip timing unit, wherein the simulation SPARC V8 architecture processor chip timing unit comprises a 16-bit pre-divider PRESCALER, four 32-bit timers and a 32-bit watchdog;

step 2-3: designing two paths of serial ports of the simulation SPARC V8 architecture processor chip, and realizing the data transmission function of the serial ports;

Step 2-4: constructing a new Machine based on QEMU, and virtualizing a minimum system on chip of a SPARC V8 architecture processor chip;

The specific steps of the step 2-1 design simulation SPARC V8 architecture processor chip interrupt controller are as follows:

Step 3-1: registering an interrupt handling event in the QEMU master event loop, detecting an interrupt signal at the end of each translation block executed by the processor, and immediately responding and starting a corresponding interrupt handler upon detection of an interrupt, with a program counter pointing to a corresponding interrupt handler start address;

Step 3-2: according to the hardware block diagram and hardware data description of the SPARC V8 architecture processor chip interrupt controller, designing a virtual interrupt controller, and realizing functions comprises: the method comprises the steps of controlling access to an IO space hardware register of an interrupt controller, receiving an interrupt request generated by an interrupt source, performing interrupt arbitration, reporting an interrupt, responding to the interrupt and clearing the interrupt;

The specific steps of the step 3-2 for designing the virtual interrupt controller are as follows:

Step 4-1: based on the QOM setting mode, the virtual interrupt controller device structure is designed, and specifically comprises: the system bus object, the memory mapping IO area, the interrupt request state information and the interrupt request signal are installed;

step 4-2: registering the virtual interrupt controller equipment model into the QEMU system;

The specific steps of the virtual interrupt controller device structure design in the step 4-1 are as follows:

Step 5-1: designing a virtual interrupt controller to inherit from the system bus device;

step 5-2: designing access control of a virtual interrupt controller register to depend on a memory mapping IO region, and distributing the memory mapping region for the register of the interrupt controller;

Step 5-3: registering a read-write callback function in the memory mapping IO area, and simulating read-write access control logic for each register of the interrupt controller;

Step 5-4: maintaining interrupt request state information;

Step 5-5: simulating an interrupt request signal, designing a callback function when a function pointer points to an interrupt source to trigger interrupt, and providing a function interface to the outside to realize the processing of the interrupt signal;

The specific steps of registering the virtual interrupt controller equipment model in the QEMU system in the step 4-2 are as follows:

step 6-1: setting a unique identifier for a QOM model of the virtual interrupt controller device;

step 6-2: providing a virtual interrupt controller device class initialization interface;

step 6-3: providing an initialization interface of a virtual interrupt controller instance to initialize equipment attributes;

step 6-4: registration of a reset interface of the virtual interrupt controller is realized;

The specific steps of the step 2-2 design simulation SPARC V8 architecture processor chip timing unit are as follows:

step 7-1: according to the hardware block diagram and the hardware data description of the SPARC V8 architecture processor chip timing unit, the functions realized by designing the virtual timing unit comprise: access control of a timing unit register, timer clock simulation and timer interrupt simulation;

Step 7-2: adding a timing event to a monitoring list in the QEMU main event cycle to finish the initialization of the timing unit;

Step 7-3: and starting the timing processing flow of the timer after starting the timer.

4. The method for designing the on-board computer CMU simulator based on the QEMU virtual environment according to claim 1, wherein the specific design of the peripheral IO controller interface chip of the simulation CMU simulator in the step 3 is as follows:

Step 8-1: abstracting peripheral IO interface equipment xxxDevice based on system bus equipment, inheriting equipment of an 80-path GPIO port, a 16-path asynchronous serial port, a 10-path synchronous serial port and a star time module in a peripheral IO interface chip composition structure to the structure, and finally registering all the equipment to the peripheral IO interface chip;

step 8-2: designing an interface for performing data interaction between the CMU module and other peripheral hardware simulators providing a target data environment;

The satellite control subsystem in the step 3 specifically comprises: the system comprises a central management unit CMU, a remote control telemetry unit TTU, a sensor, an execution mechanism and a dynamics model;

The specific steps of the satellite control subsystem joint debugging in the step 3 are as follows:

step 9-1: according to the control period of the on-board software, synchronously controlling a peripheral hardware simulator and a CMU simulator which provide a target data environment;

Step 9-2: the on-board software completes task scheduling in a control period and generates thrust pulse data;

step 9-3: the target data environment simulator completes the dynamics simulation and continues to generate data stimulus to the CMU;

Step 9-4: and circularly executing to complete the joint debugging of the closed loop of the whole control subsystem.

5. The method for designing a QEMU virtual environment based on a satellite borne computer CMU simulator of claim 3, wherein the specific steps of designing the virtual timing unit in step 7-1 are as follows:

Step 10-1: realizing access control of a timing unit register based on the memory mapping IO region;

the method comprises the following steps of: a ptimer mechanism based on QEMU initializes a timer to complete timer clock simulation;

The method comprises the following steps of: designing a timer expiration callback function to realize timer interrupt simulation;

The design timer expiration callback function specifically comprises: judging whether the interrupt shielding of the interrupt controller and the special interrupt of the corresponding timer in the priority register are enabled or not; if enabled, reporting an interrupt to an interrupt controller, performing subsequent interrupt arbitration and reporting to a processor by the interrupt controller, and finally executing a corresponding timer interrupt processing program by the processor; if the shielding is performed, no operation is performed.

6. The method for designing the on-board computer CMU simulator based on the QEMU virtual environment according to claim 3, wherein the specific steps of designing the two serial ports of the processor chip with the simulated SPARC V8 architecture in step 2-3 are as follows:

step 11-1: distributing and binding character equipment in the form of file descriptors for the serial port equipment;

Step 11-2: the method comprises the steps of performing interrupt and data transmission control on a character device through read-write access control on a control register, a status register and a data register of the serial device;

Step 11-3: registering a monitoring event corresponding to the file descriptor in the QEMU master event loop, and executing data receiving and transmitting operations according to the character equipment when the readable or writable event occurs in the character equipment file descriptor;

Step 11-4: the function of transmitting data by the serial port equipment is realized;

step 11-5: the function of receiving data by the serial device is realized.

7. The method for designing a spaceborne computer CMU simulator based on QEMU virtual environment according to claim 3, wherein the specific steps of constructing a new Machine based on QEMU in steps 2-4 are as follows:

Step 12-1: designating a SPARC V8 architecture processor chip Machine default CPU type as LEON3, and designing a callback function to be executed when the CPU responds to the interrupt by itself to realize corresponding processing logic;

step 12-2: allocating the memory space address of the SPARC V8 architecture processor chip;

Step 12-3: bootloader is designed by itself and loaded to ROM area of processor chip memory of SPARC V8 architecture;

Step 12-4: loading the satellite-borne embedded software into an entry address of the RAM area in a kernel mode;

step 12-5: setting a stack pointer of the CPU according to the size of the memory area designated by the user;

Step 12-6: the registration and instantiation of the SPARC V8 architecture processor chip interrupt controller, the timing unit and the serial port device are completed, each on-chip device is hung on the system bus SysBus, and IO address space allocated for each device is mapped to the memory space;

Step 12-7: GPIO input and output lines are used to abstract the input and output pin properties of hardware devices, and devices are connected with each other through GPIO lines.

8. The method for designing the on-board computer CMU simulator based on the QEMU virtual environment according to claim 4, wherein the specific steps of providing the peripheral hardware simulator of the target data environment and performing synchronous control with the CMU simulator in step 9-1 are as follows:

Step 13-1: when the CMU simulator is started, a Monitor is started in a blocking mode, an 'S' option is added, and after the initialization of the virtual machine is completed, a VCPU thread is blocked and waits before the execution of a first instruction;

step 13-2: when a peripheral hardware simulator providing a target data environment is initialized, connecting a Monitor, and starting to execute initialization work by the CMU simulator and stopping before the execution of a first instruction;

step 13-3: in each control period of the target data environment simulator, firstly sending a cont instruction to the Monitor to resume the operation of the CMU simulator;

Step 13-4: the target data environment simulator sleeps for 64ms based on the host clock, and then sends a stop instruction to the Monitor to stop running the CMU simulator.