CN115208472A - Data transmission system and data sending and receiving method - Google Patents

Abstract

A data transmission system and a data transmission and reception method, the system includes at least two data transmission units, the first data transmission unit includes at least one optical signal receiving end, the second data transmission unit at least includes an optical signal transmitting end, and the optical signal The receiving end is connected with the optical signal transmitting end through an optical fiber. The steps of the sending method: the data generating source sends N circuits of electrical signal aggregation conversion to the data transmission unit, generates M circuits of electrical signals, and converts them into T circuits of optical signals through a photoelectric conversion device. The steps of the receiving method: the optical signal source sends out T-path optical signals to the data transmission unit, and converts them into M-path electrical signals through a photoelectric conversion device; the M-path electrical signals are separated to obtain target signals and send to the data application terminal. After the electrical signal is multiplexed and converted into an optical signal, the transmission link is relatively simple. At the same time, when the number of Ethernet transmission channels is increased, only the configuration of the software interface needs to be increased, and the number of optical fibers does not need to be re-laid.

Description

A data transmission system and data transmission and reception method

technical field

The invention belongs to the technical field of communication, and in particular relates to a data transmission system and a data sending and receiving method.

Background technique

At present, train communication generally adopts WTB (Twisted Wire Train Bus) or Ethernet electric bus network. With the improvement of domestic high-speed rail and subway operation speed, passengers have higher and higher requirements for train ride safety, comfort and convenience, such as Passengers' demands for in-vehicle entertainment facilities, etc., so the data network throughput requirements of the train will become higher and higher, and the traditional bus rate cannot meet the transmission requirements of the system. The entertainment system, health management system and car control system on the train are currently three completely independent networks, as shown in Figure 1, all of which are transmitted through cables. The link laying workload on the train is heavy, the electromagnetic environment is complex, and data transmission is required. Packet loss often occurs. The disadvantages of the traditional communication system for trains are summarized as follows:

(1) At present, the 100M network is generally used for communication on trains, and the communication rate is low;

(2) The Ethernet signal is transmitted by cable, and the transmission distance is within nearly 100m. Affected by the complex electromagnetic environment of the train, the network will lose packets;

(3) At present, there are mainly three network systems on the train: entertainment system, health management system and car control system.

SUMMARY OF THE INVENTION

In order to solve the above-mentioned technical problems of traditional cable laying workload, low communication rate and easy occurrence of packet loss, the present invention provides a data transmission system and a data transmission and reception method.

The purpose of the present invention is to adopt the following technical solutions to achieve. A data transmission system according to the present invention includes at least two data transmission units, wherein the two data transmission units are respectively a first data transmission unit and a second data transmission unit, and the first data transmission unit at least includes an optical signal receiving unit. The second data transmission unit includes at least one optical signal transmitting end, and the optical signal receiving end receives the optical signal sent by the optical signal transmitting end through the optical fiber.

Further, the second data transmission unit includes a second digital signal receiving part and a second digital signal processing part, and the second digital signal receiving part is communicatively connected with the N-channel cable for receiving the electrical signals of the N-channel cable, The second digital signal processing unit aggregates the received N circuits of electrical signals to form M circuits of electrical signals, the second digital signal processing unit is connected to the second photoelectric conversion device, and the M circuits of electrical signals are converted into T by the second photoelectric conversion device The optical signal is sent through the optical signal sending end and transmitted by the optical fiber, where N≥1, M≤N, T≤N.

Further, the second data transmission unit includes a second switch, the N-way cable is connected to the second switch, a second Ethernet signal conversion device is arranged between the second switch and the second digital signal receiving part, and the N-way cable is The electrical signal is transmitted to the second Ethernet signal conversion device through the second switch, and the converted signal is transmitted to the second digital signal receiving part.

Further, the second digital signal processing unit includes a framing module, a clock domain transformation module, a scrambling module, an encoding module, a link error detection module, a parallel-to-serial conversion module, a high-speed serial transceiver module, and an N-channel electrical signal. The above-mentioned modules are aggregated into M circuits of electrical signals.

Further, the first data transmission unit includes a first digital signal receiving part and a first digital signal processing part, the optical signal receiving end is connected to the first photoelectric conversion device, and the first photoelectric conversion device The optical signal is converted into M circuits of electrical signals, and then transmitted to the first digital signal receiving unit. After the M circuits of electrical signals are processed by the first digital signal processing unit, they are restored to N circuits of electrical signals and transmitted to the corresponding N circuits of electrical signals. cable, or, the first digital signal receiving part sends the M circuit electrical signals to another photoelectric conversion device, and sends the converted signal to another data transmission unit, the N≥1, M≤N, T ≤N.

Further, the first digital signal processing part is connected with the first switch through the first Ethernet signal conversion device, the first switch is connected with the corresponding N-way cables, and the N-way electrical signals are converted by the first Ethernet conversion device and transmitted to the first switch. A switch and then passed to the N-way cable.

Further, the first digital signal processing unit includes a serial-to-parallel conversion module, a link error detection module, a decoding module, a descrambling module, a clock domain transformation module, a de-framing module, a high-speed serial transceiver module, and M circuits of electrical signals. After the above-mentioned module processing, it is restored to N circuits of electrical signals.

A method for sending N-way data, the method uses the data transmission system, and the method comprises the following steps:

Step 1. The data generating source sends N electrical signals to the data transmission unit, where N≥1;

Step 2, the data transmission unit receives the N circuits of electrical signals, and aggregates and converts the N circuits of electrical signals to generate M circuits of electrical signals, where M≤N;

Step 3. The M circuits of electrical signals are converted into T circuits of optical signals by the photoelectric conversion device, where T≤N;

Step 4: The T-path optical signal is sent through the optical signal sending end, and is transmitted by the T-path optical fiber.

Further, in the process of data aggregation conversion, the N circuits of electrical signals are assembled according to the set frame format through the framing module in the data transmission unit, and passed through the encoding module, the parallel-serial conversion module, and the high-speed serial transceiver module. Output the M circuit electrical signals.

Further, the data transmission unit sets up multiple clock domains, including Ethernet clock domain, framing/de-framing, check processing clock domain, signal sending and receiving clock domain; Ethernet clock domain includes Gigabit Ethernet clock domain, Fast Ethernet clock domain The network clock domain, the Gigabit Ethernet clock domain includes the Gigabit Ethernet acquisition module, the 100M Ethernet clock domain includes the 100M Ethernet acquisition module, the framing/de-framing, check processing clock domain includes the framing/de-framing module , the signal transceiver clock domain includes high-speed serial transceiver module, link error detection module, 64B/66B encoding/decoding module, parallel-serial/serial-parallel conversion module, scrambling/descrambling module; asynchronous FIFO For isolation, in the process of data aggregation and conversion, the conversion between multiple clock domains is processed by the clock domain transformation module.

Further, in the process of data aggregation conversion, the encoded serial data is input into the scrambling code module in the data transmission unit, and the scrambled code data is output after the scramble code is calculated.

Further, in the data aggregation conversion process, in the data transmission unit, the test code generator in the sending part of the link error detection module generates a test digital sequence, which is encoded and sent to the input end of the data transmission unit, and transmitted through the data transmission unit. output later.

A method for receiving optical signal data, using the data transmission system, the method includes the following steps:

Step 1. The optical signal source sends T optical signals to the data transmission unit, and the T optical signals are transmitted by T optical fibers;

Step 2, the T-path optical signal is converted into the M-path electrical signal through the photoelectric conversion device;

Step 3, the data transmission unit performs a signal separation operation on the M circuits of electrical signals to obtain a target signal, and the target signal is composed of N circuits of sub-signals;

Step 4, sending the N-way sub-signals to the data application terminal;

Said N≥1, M≤N, T≤N.

Further, during the signal separation operation, the M circuits of electrical signals pass through the serial-to-parallel conversion module and the decoding module to restore the data frame form, and output the target signal through the de-frame module.

Further, the data transmission unit sets up multiple clock domains, including Ethernet clock domain, framing/de-framing, check processing clock domain, signal sending and receiving clock domain; Ethernet clock domain includes Gigabit Ethernet clock domain, Fast Ethernet clock domain The network clock domain, the Gigabit Ethernet clock domain includes the Gigabit Ethernet acquisition module, the 100M Ethernet clock domain includes the 100M Ethernet acquisition module, the framing/de-framing, check processing clock domain includes the framing/de-framing module , the signal transceiver clock domain includes high-speed serial transceiver module, link error detection module, 64B/66B encoding/decoding module, parallel-serial/serial-parallel conversion module, scrambling/descrambling module; asynchronous FIFO For isolation, during the signal separation operation, the conversion between multiple clock domains is processed by the clock domain transformation module.

Further, during the signal separation operation, the scrambled data is input into the descrambling module, and after calculation, the descrambled data is output, and then decoded in the decoding module.

Further, in the signal separation operation process, in the data transmission unit, the signal enters the receiving part of the link error detection module for decoding, and obtains the synchronization clock from the signal, and the test code generator of the receiving part generates the same and the sending part. The synchronous digital sequence is compared with the received signal. If it is inconsistent, it is a bit error. The counter is used to count the number of error bits, and then the test results are recorded, stored, analyzed and displayed.

Compared with the prior art, the present invention has the advantages that: in the prior art, the train transmits through the Ethernet signal, and each signal is transmitted separately, and the train needs to lay a corresponding number of cable assemblies if several Ethernet signals are needed. . This solution converts electrical signals into optical signals after multiplexing, and the transmission link is relatively simple. One channel (using wavelength division multiplexing optical module) or two channels of optical fiber can meet the transmission requirements of multi-channel Ethernet signals, while adding Ethernet When the number of transmission channels is increased, only the configuration of the software interface needs to be increased, and there is no need to increase the number of laying fibers.

The above description is only an overview of the technical solutions of the present invention, in order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand , the following specific preferred embodiments, and in conjunction with the accompanying drawings, are described in detail as follows.

Description of drawings

1 is a schematic diagram of the transmission of a train Ethernet signal cable in the prior art;

2 is a schematic diagram of signal transmission of a data transmission system in an embodiment of the present invention;

Figure 3 is a block diagram of the power module in Figure 2 from 5V to 3.3V;

Figure 4 is a block diagram of Gigabit Ethernet signal processing;

Fig. 5 is a block diagram of medium 100M Ethernet signal processing;

Fig. 6 is a software functional block diagram;

7 is a schematic diagram of data transmission;

8 is a schematic diagram of clock domain transformation;

9a is a schematic diagram of a scrambling code circuit;

Figure 9b is a schematic diagram of the decoding circuit

Figure 10 is a functional block diagram of a signal acquisition and recovery sub-module;

Figure 11 is a functional block diagram of the link error detection module.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

An embodiment of a data transmission system of the present invention is shown in FIG. 2 to FIG. 11 .

The present invention is based on the Ethernet electrical signal communication network of the existing train. In the present invention, the communication interfaces of the systems that need to transmit signals, such as the entertainment system, health management system, and car control system in each carriage, are aggregated for electrical signals. After being aggregated into one electrical communication interface, the electrical signal is converted into an optical signal for transmission, which can be compatible with the train's 100M and gigabit communication networks, thereby realizing the optical network transmission of the entire vehicle communication link. The entertainment system, health management system, and car control system in the carriage are the source of data generation, and can also be used as the data application terminal.

The system includes a plurality of data transmission units, each car is provided with a data transmission unit, and each data transmission unit includes a switch, an Ethernet signal conversion device, a signal processing module, an optical module, a power module, a clock circuit, and an optical fiber transmission unit. The switch is connected to the entertainment system, health management system, and car control system in the cabin through cables. The Ethernet signal conversion device includes an Ethernet switch chip (ie, the PHY chip in FIG. 4 ), as shown in FIG. 2 . The signal processing unit is used for converting multiple Ethernet signals into one highly differential electrical signal, or converting one high-speed differential signal into multiple Ethernet signals. The function of the optical module is photoelectric conversion or electro-optical conversion. As a photoelectric conversion device, the part that emits an optical signal is the optical signal transmitting end, and the part that receives the optical signal is the optical signal receiving end. The optical fiber transmission unit includes an optical cable assembly and an optical fiber connector, the optical cable assembly is connected to the optical module and the optical fiber connector, and the data transmission units of the adjacent carriages are connected through the optical fiber connector. The clock circuit includes an active crystal oscillator and a clock debounce chip that are connected in series. The active crystal oscillator provides a reference clock for the clock debounce chip, and the clock debounce chip provides a high-speed differential clock for the signal processing module. The data transmission unit combined with the train communication system can form a whole train optical transmission network system, which connects multiple carriages for communication. The data transmission unit also communicates and connects with various systems in the corresponding carriages that need to transmit signals through the switch, and the various systems in each carriage communicate with the Ethernet switch chip through the switch. Figure 2 shows a part of the system, wherein M1, M2, and M3 are three cars, each car is provided with a data transmission unit, and the data transmission units in each car are connected in series through the optical fiber transmission unit.

Taking the car M2 as an example for description, the optical fiber connector of the data transmission unit in the car M2 is connected to the optical fiber connector of the data transmission unit in the upper-level car M1. The optical signal received through the optical fiber connector is transmitted to the optical module through the optical cable assembly, and photoelectric conversion is performed in the optical module, and the optical signal is converted into a high-speed differential electrical signal, and the high-speed differential electrical signal enters the signal processing module. The signal processing module is divided into multiple functional modules according to functions, including framing/de-framing module, clock domain transformation module, scrambling/descrambling module, 64B/66B encoding/decoding module, link error detection module, high-speed serial Transceiver module, serial-parallel/parallel-serial conversion module, link status monitoring module, clock management module. The high-speed differential electrical signal is restored into a multi-channel Ethernet signal through a serial-parallel conversion module, a link error detection module, a 64B/66B decoding module, a descrambling module, a clock domain transformation module, a de-framing module, and a high-speed serial transceiver module. The recovered Ethernet signal is connected to the switch through the Ethernet switch chip as required, multiple Ethernet switch chips are provided, and the Ethernet interface module on the signal processing module is connected to the corresponding Ethernet switch chip. After exchanging information with various systems in this car through the switch, the multi-channel Ethernet signals are input into the optical module in the opposite process, and communicated with the data transmission unit of the next-level car M3 through the optical cable assembly and optical fiber connector. , specifically: the multi-channel Ethernet signal enters the signal processing module through the Ethernet switch and the Ethernet switch chip. In the signal processing module, the Ethernet signal sequentially passes through the framing module, the clock domain transformation module, the scrambling module, 64B/66B The encoding module, link error detection module, parallel-serial conversion module, and high-speed serial transceiver module are aggregated into one electrical signal and enter the optical module, where electrical-optical conversion is performed, and the converted optical signal is passed through the optical cable assembly, optical fiber The connector is communicatively connected to the data transmission unit of the next car M3.

Taking the unidirectional transmission between adjacent data transmission units as an example, the first data transmission unit includes at least one optical signal receiving end, and the second data transmission unit includes at least one optical signal transmitting end, and the optical signal receiving end passes through. The optical fiber receives the optical signal sent by the transmitting end of the optical signal. The second data transmission unit includes a second digital signal receiving part, a second digital signal processing part, a second switch, and a second photoelectric conversion device, and the second digital signal receiving part and the second digital signal processing part are integrated in the second data transmission unit The signal processing module, the second digital signal receiving part is communicatively connected with the N-way cables for receiving the electrical signals of the N-way cables, N≥1, the second digital signal processing part aggregates the received N-way electrical signals to form M circuits of electrical signals, M≤N, the second digital signal processing part is connected to the second photoelectric conversion device, the M circuits of electrical signals are converted into T circuits of optical signals by the second photoelectric conversion device, T≤N, the optical signals are sent by optical signals terminal and transmitted by optical fiber. The N-way cable is connected to the second switch, and a second Ethernet signal conversion device is arranged between the second switch and the second digital signal receiving part, and the electrical signals of the N-way cable are transmitted to the second Ethernet signal conversion device through the second switch. The converted signal is transmitted to the second digital signal receiving part. The second digital signal processing part includes a framing module, a clock domain transformation module, a scrambling module, an encoding module, a link error detection module, a parallel-to-serial conversion module, and a high-speed serial transceiver module. M circuit electrical signal.

The first data transmission unit includes a first digital signal receiving part, a first digital signal processing part, a first switch, a first photoelectric conversion device, and the first digital signal receiving part and the first digital signal processing part are integrated in the first data transmission unit On the signal processing module, the optical signal receiving end is connected to the first photoelectric conversion device, and the first photoelectric conversion device converts the received T-path optical signal into M-path electrical signal, and then transmits it to the first digital signal receiving part, M-path After the electrical signal is processed by the first digital signal processing part, it is restored to N circuits of electrical signals and transmitted to the corresponding N circuits of cables, or the first digital signal receiving part sends the M circuits of electrical signals to another photoelectric conversion device, The converted signal is sent to another data transmission unit, where N≥1, M≤N, T≤N. The first digital signal processing part is connected with the first switch through the first Ethernet signal conversion device, the first switch is connected with the corresponding N-way cables, and the N-way electrical signals are converted by the first Ethernet conversion device and then transmitted to the first switch. Then pass to the N-way cable. The first digital signal processing part includes a serial-to-parallel conversion module, a link error detection module, a decoding module, a descrambling module, a clock domain transformation module, a de-framing module, and a high-speed serial transceiver module. After the M circuit electrical signals are processed by the above modules Restored to N-way electrical signal.

The steps of the N-way data transmission method are summarized as follows:

Step 1. The data generating source sends N electrical signals to the data transmission unit, where N≥1;

Step 2, the data transmission unit receives the N circuits of electrical signals, and aggregates and converts the N circuits of electrical signals to generate M circuits of electrical signals, where M≤N;

Step 3. The M circuits of electrical signals are converted into T circuits of optical signals by the photoelectric conversion device, where T≤N;

Step 4: The T-path optical signal is sent through the optical signal sending end, and is transmitted by the T-path optical fiber.

The steps of the optical signal data receiving method are summarized as follows:

Step 1. The optical signal source sends T optical signals to the data transmission unit, and the T optical signals are transmitted by T optical fibers;

Step 2, the T-path optical signal is converted into the M-path electrical signal through the photoelectric conversion device;

Step 3, the data transmission unit performs a signal separation operation on the M circuits of electrical signals to obtain a target signal, and the target signal is composed of N circuits of sub-signals, and the N circuits of sub-signals are the recovered Ethernet electrical signals;

Step 4, sending the N-way sub-signals to the data application terminal;

Said N≥1, M≤N, T≤N.

As shown in Figure 2, the symbols ① to ⑩ are the schematic diagrams of the signal flow of a signal from the switch of the car M1 to the car M3 and then to the next-level car. The specific implementation functions are as follows:

1) It can realize the combined transmission of multi-channel 100M Ethernet signals and multi-channel Gigabit Ethernet signals;

2) Customize the data frame format, transmit data in the form of data frames, distinguish different types of data frames by data frame identifiers, and realize specific functions;

3) Realize 64B/66B encoding and decoding and other physical layer digital encoding technologies to improve the reliability of data transmission;

4) The communication rate can reach up to 10Gbps;

5) The system can generate pseudo-random sequences by itself to detect the error characteristics of the current link. When the error code exceeds a certain upper limit, an alarm signal will be generated.

The signal processing module includes an FPGA main chip, and each functional module in the signal processing module runs on the FPGA main chip. The FPGA main chip selects the Kintex7 series XC7K325T of Xilnix as the core processing device. The device adopts the 40nm process, which has the advantages of extremely high cost performance, ultra-low power consumption, etc. It also has a variety of advanced functions, especially the extremely strong embedded system processing. Ability and ultimate interconnection capability, can flexibly build high-bandwidth interfaces, and abundant resources ensure design margins and fully meet design requirements.

The input voltage of the power module is 5±0.25V, the core working voltage of the FPGA main chip (model XC7K325T-FFG676) is 3.3V, 1.8V, 1.25V, 1.2V and 1.0V, and the working voltage of the optical module circuit is 3.3V. The power module includes a power filter network and a power conversion module. The power module converts the input voltage 5V to 3.3V, and the system block diagram of 5V to 3.3V is shown in Figure 3. In order to prevent the back end of the circuit from being damaged by reverse connection of the power supply, short circuit of the circuit or excessive input instantaneous voltage, the power input port is designed with interface protection for the protection of reverse connection of the power supply and surge.

Each module of the data transmission unit is integrated on the test backplane, and the 5V voltage on the external input test backplane passes through the power filter network and is converted into 3.3V by the power conversion module. The power conversion module uses TI's PTH05000WAD chip as the 5V to 3.3V DC-DC conversion module. The PTH05000WAD input voltage is 4.5V to 5.5V wide input, and the output current can reach 6A. The 3.3V voltage is used to test the operation of each module circuit on the backplane. The 5V voltage input to the test backplane through the inter-board connector is converted into the working voltage required by each module through the power module.

The composite single-fiber optical transmission of Gigabit Ethernet signals and other signals is usually performed by a wavelength division multiplexer. The present invention uses an FPGA main chip to process multiple Ethernet signals and convert them into one optical signal, and the optical signal is transmitted through a single fiber. Optical transmission eliminates the need for bulky wavelength division multiplexers, which can effectively reduce costs and product volume.

The present invention selects the Ethernet switch chip 88E6321 of Marvell to transmit Gigabit Ethernet signals. The Ethernet switch chip 88E6321 fully supports the IEEE802.3 protocol, and its main performance features include:

1) Integrate 2 10/100/1000 Ethernet transceiver modules (based on PHYs);

2) Integrate 1 (G)MII port;

3) Integrate 2 SERDES ports, support 1000BASE-X, 100BASE-FX;

4) Support RGMII/SGMII interface to connect with external MAC;

5) The RGMII clock mode supports internal or external delay on the RX transmission path;

6) Flexible priority configuration;

7) All ports support 10Mbps and 100Mbps full-duplex or half-duplex mode;

8) All ports support 1000Mbps full-duplex mode;

9) Adaptive speed and duplex communication between PHYs and MACs;

10) It has the function of cable diagnosis and detection;

11) 3.3V single power supply;

12) It has rich status indication functions, with rate and link indication;

13) Support 25M clock source;

14) Low power consumption 0.9W.

The Ethernet switching chip realizes the electrical aggregation and optical fiber transmission of multiple independent Gigabit Ethernet signals. The flow chart of the Ethernet signal is shown in Figure 4. For the multi-channel Gigabit Ethernet signal received from the Ethernet switch, the level conversion of the Ethernet signal is first realized through the network transformer, and then the Ethernet signal is converted into a GMII signal through the Ethernet switching chip (PHY chip), and the GMII signal It is transmitted to the FPGA main chip, and the GMII signal converted by the multi-channel Gigabit Ethernet signal is packaged by the FPGA main chip, and then transmitted to the optical module to realize electro-optical conversion. The converted optical signal is transmitted to the data transmission unit of the next-level car through the optical fiber connector. The optical signal is converted into a high-speed differential electrical signal through the optical module of the next-level car, and then the high-speed differential electrical signal is transmitted to the FPGA main chip for data processing. Analyze, restore the multi-channel Gigabit Ethernet GMII signal, and restore the multi-channel 100-megabit Ethernet and multi-channel Gigabit Ethernet after the Ethernet switching chip and network transformer to realize photoelectric conversion.

The 100M Ethernet circuit is designed with Marvell's chip 88E6061, and the circuit is designed according to the data sheet of 88E61061. The specific functional block diagram is shown in Figure 5. The architecture of the Fast Ethernet processing solution is similar to that of Gigabit. The 10/100Mbps Ethernet PHY chip is used to convert the Ethernet signal into MII signal parallel data and output it to the FPGA for processing.

The software functional block diagram of the data transmission unit is shown in Figure 6. The software functions are integrated on the FPGA main chip. The main functional modules include an Ethernet interface module connected to the Ethernet switching chip, a high-speed serial transceiver module, and a link error detection module. , 64B/66B encoding/decoding module, parallel-serial/serial-parallel conversion module, scrambling/descrambling module, clock domain conversion module, clock management module, data framing/de-framing module, link status monitoring module, Ethernet acquisition /Recovery module, wherein the Ethernet acquisition module includes a Gigabit Ethernet acquisition module and a 100M Ethernet acquisition module. The Gigabit Ethernet acquisition module and the 100M Ethernet acquisition module are respectively used to collect the data transmitted by the corresponding Ethernet interface module. . This software function can realize the combined transmission of multiple Ethernet signals.

After the Ethernet signal is combined, it is transmitted through the optical fiber, and the transmission rate can be adjusted according to the number of aggregated Ethernet channels. The data framing module assembles the received data according to the set frame format, and then outputs the high-speed serial modulation signal through the 64B/66B encoding module and the parallel-serial conversion module. After receiving the signal, the receiving end restores the data frame form through the serial-parallel conversion module and the 64B/66B decoding module, and outputs the gigabit network signal through the data de-framing module. At the same time, the link status monitoring module detects the current link status in real time. The format of data transmission is shown in Figure 7. The data is transmitted in the form of packets. One clock cycle is 64 bits wide. Each data packet consists of 240 clock cycles. Occupies 10 clock cycles.

Data framing is a function of the data link layer and is a technique used to allocate or label channels within a bit stream. It defines a set of meaningful identifiers at the sender and receiver, and transmits data in segments through these identifiers. The defined identifiers include frame start, frame end, frame type, and so on. Through the identification, the length of the data frame, the type of the data frame, etc. can be judged, and the data can also be checked. When there is no data transmission, idle characters will be transmitted to ensure the continuity of link data transmission.

Multiple clock domain transitions are required to implement an Ethernet signal. The clock domains involved in the system include Ethernet clock domain, framing/de-framing, check processing clock domain, and signal sending and receiving clock domain. In the internal data processing of the FPGA main chip, it involves the conversion between multiple clock domains. The schematic diagram of the clock domain division is shown in Figure 8. The Ethernet clock domain includes the Gigabit Ethernet clock domain, the Fast Ethernet clock domain, the gigabit Ethernet clock domain, and the The Gigabit Ethernet clock domain includes the Gigabit Ethernet acquisition module, the Fast Ethernet clock domain includes the Fast Ethernet acquisition module, the framing/de-framing, verification processing clock domain includes the framing/de-framing module, and the signal sending and receiving clock domain It includes high-speed serial transceiver module, link error detection module, 64B/66B encoding/decoding module, parallel-serial/serial-parallel conversion module, and scrambling/descrambling module. At the same time, each clock domain is isolated by asynchronous FIFO, which can realize efficient and stable data conversion and transmission.

64B/66B coding technology is a coding technology proposed by IEEE802.3 working group for 10Gbps Ethernet, the purpose is to reduce coding overhead and hardware complexity. 64B/66B encoding encodes 64-bit data or control information into 66-bit blocks for transmission. The first two bits of the 66-bit block represent the synchronization header, which is mainly used for data alignment at the receiving end and synchronization of the received data bit stream. There are two kinds of synchronization headers: "01" and "10". "01" indicates that the following 64 bits are data, "10" indicates that the following 64 bits are a mixture of data and control information, and the 8 bits next to the synchronization header are the data type field. , the following 56bit control information or data or a combination of the two.

In addition to the synchronization code, 64bit data must be scrambled before it can be transmitted. The scrambler polynomial used by 64B/66B is: f(x)=x ⁵⁸ +x ³⁹ +1. Scrambling is a distribution method that rearranges or encodes data to optimize it. Its main function is to randomize the distribution of "0" and "1" in digital communication, so that the bit information pattern is randomized. It further reduces jitter and inter-symbol crosstalk and improves the reliability of communication. In essence, scrambling code is the random processing process of the bit layer before the data to be transmitted enters the channel transmission to achieve the above purpose. The de-randomization process corresponding to the scrambling process is called descrambling. . The mathematics of scrambling code uses polynomials, and the choice of polynomial is usually based on the characteristics of the scrambling code, including the randomness of the generated data, and the ability to scramble consecutive 0s and 1s. A simple scrambler consists of an array of flip-flops that shift the data stream. Most flip-flops simply output the next bit stream, but in some complex scrambling circuits, flip-flops need to perform logical operations with each bit in the data stream. The schematic diagrams of scrambling/decoding are shown in Figures 9a and 9b. The coded serial data is input to the scrambling module, and the scrambled data is output after scrambling calculation; after the output scrambled data is transmitted to the data transmission unit of another device, The scrambled data is input into the descrambling module, and after calculation, the descrambled data is output, and then decoded in the decoding module.

The signal processing of the Ethernet physical layer is directly completed by the hardware chip, and the FPGA main chip interacts with the Ethernet switching chip through the GMII/MII interface to realize data transmission. At the sending end of the system, the Ethernet signal first enters the asynchronous FIFO, and is synchronized to the local clock through clock domain conversion for processing. The asynchronous FIFO writing clock of the sending end is provided by the Ethernet switch chip. In the receiving end, the Ethernet signal is first stored in the asynchronous FIFO, and then the Ethernet switching chip is used to receive the clock to read the asynchronous FIFO of the receiving end to complete the Ethernet signal recovery. As shown in Figure 10, the Ethernet signal acquisition/recovery module includes an Ethernet signal acquisition module and an Ethernet signal recovery module. When the data transmission unit is used as the sender, the Ethernet switch chip inputs the clock and GMII/MII to the Ethernet signal acquisition module. At the same time, the module inputs the local clock, and outputs the valid data ID and Ethernet data stream; when the data transmission unit is used as the receiving end, the local clock, valid data ID, and Ethernet data stream are input to the Ethernet signal recovery module, and are input to the Ethernet switch at the same time. Chip clock, output GMII/MII signal.

The link error detection module mainly includes two parts: sending and receiving. Figure 11 shows the functional block diagram of the link error detection module. The test code generator of the transmission part of the link error detection module generates a known test digital sequence, and the M sequence generator as shown in the figure generates 32-bit M sequences; after encoding, it is sent to the input end of the detected system, After being transmitted by the system under test and output, it enters the receiving part of the link error detection module to decode and obtain the synchronization clock from the received signal. The test code generator of the receiving part generates the same and synchronized digital sequence as the transmitting part, and receives the If there is any inconsistency, it is a bit error. Use a counter to count the number of bits in the error code, and then record, store, analyze, and display the test results. The frame synchronization and error detection module as shown in the figure The bit M sequence is decoded, and at the same time, it is compared with the digital sequence generated by the test generator. If it is inconsistent, the error code is output, the error code statistics module counts, and the alarm signal is output to facilitate record storage, analysis, and display of the test structure. .

The system can implement link error detection. When the sender sends an error detection command to the receiver, the receiver loops back the receive link and the sender when the command is detected, and the system enters the link error detection state. Error detection mainly includes the following processes and steps: (1) a pseudo-random sequence generated and transmitted in a certain way, and the local pseudo-random sequence of the same phase is used as the comparison standard; (2) the local pseudo-random sequence is compared with the receiving The pseudo-random sequences are compared one by one, and the error identification signal is output; (3) The error identification signal is counted to calculate the corresponding error rate.

The high-speed serial transceiver module is implemented with Xilinx GTX hard core. Generated by Xilinx core generate, the GTX data transmission and reception rate is 10.3125Gbps in configuration. GTX has a variety of encoding modes available when performing data DC balance, such as: 8B/10B codec, 64B/66B codec and 64B/67B codec, etc. When the serial rate is low, 8B/10B codec technology is commonly used to process data, and when the data rate is high, 64B/66B and 64B/67B codecs are used. This solution will use 64B/66B codec technology to achieve data DC balance. Adopting this coding technology needs to realize multi-clock domain conversion within the system, and has higher requirements on the layout and wiring of the internal clock. When designing code, it is necessary to use internal dedicated clock resources to ensure the achievability of the design. The high-speed serial transceiver module includes two parts: sending and receiving. It cooperates with the serial-parallel/parallel-serial conversion module and the 64B/66B encoding/decoding module. It mainly realizes data encoding and decoding and parallel-serial/serial-parallel conversion, and outputs a reference clock for other module usage. Among them, the GTX sender implements data encoding and parallel-serial conversion. The GTX transceiver module has a built-in phase-locked loop, and the external input clock is output through the phase-locked loop, which can effectively reduce the jitter and frequency deviation of the clock. At the same time, the built-in CDR circuit at the receiving end can recover the data clock for data processing at the receiving end.

In the prior art, the train transmits through Ethernet signals, and each signal is transmitted independently. If the train needs several Ethernet signals, a corresponding number of cable assemblies need to be laid. This solution converts electrical signals into optical signals after multiplexing, and the transmission link is relatively simple. One channel (using wavelength division multiplexing optical module) or two channels of optical fiber can meet the transmission requirements of multi-channel Ethernet signals, while adding Ethernet When the number of transmission channels is increased, only the configuration of the software interface needs to be increased, and there is no need to increase the number of laying fibers.

The system consists of hardware circuit and software program. The hardware circuit mainly includes external signal interface, power supply circuit, Ethernet switching chip, photoelectric/electrical-optical conversion module, and FPGA main chip. The system can use single-fiber bidirectional or dual-fiber bidirectional transmission to complete point-to-point communication.

In a data transmission unit, multi-channel Ethernet signals are combined and transmitted through optical fibers, and the transmission rate is 10Gbps. The data framing/de-framing module assembles the collected data according to the set frame format, and then encodes and de-frames the data. The serial conversion module outputs the 10Gbps modulated signal. After receiving the signal, another data transmission unit restores the data frame form through serial-parallel conversion and decoding, and outputs the Ethernet signal by de-framing. At the same time, the link status monitoring module detects the current link status in real time.

The software adopts a modular design, in which the 10Gbps channel part can provide a 64-bit bit width, and other interface modules, such as Gigabit Ethernet acquisition modules, etc., can send data to the 10Gbps channel according to the control signal and the occupied data bit width to realize data combined transmission. . The 64-bit interface is a data interface. At the same time, it is necessary to provide the back-end module with clocks of various frequencies for use by the back-end module. The back-end frequency division clock needs to be the same source as the GTX user clock, which is convenient for subsequent modules to reuse. It is realized with the help of the DCM module inside the FPGA.

Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principle and spirit of the invention Variations, the scope of the invention is defined by the appended claims and their equivalents.

Claims (17)

1. A data transmission system, characterized in that it comprises at least two data transmission units, wherein the two data transmission units are respectively a first data transmission unit and a second data transmission unit, and the first data transmission unit comprises at least one optical signal The receiving end, the second data transmission unit includes at least one optical signal transmitting end, and the optical signal receiving end receives the optical signal sent by the optical signal transmitting end through the optical fiber. 2 . The data transmission system according to claim 1 , wherein the second data transmission unit comprises a second digital signal receiving part and a second digital signal processing part, and the second digital signal receiving part is connected to N-way cable communication connection is used to receive electrical signals of N-way cables. The second digital signal processing part aggregates the received N-way electrical signals to form M-way electrical signals. The second digital signal processing part and the second photoelectric conversion The device is connected, and the M circuits of electrical signals are converted into T circuits of optical signals through the second photoelectric conversion device, and the optical signals are sent through the optical signal transmitting end and transmitted by the optical fiber, where N≥1, M≤N, T≤N. 3 . The data transmission system according to claim 2 , wherein the second data transmission unit comprises a second switch, the N-way cable is connected to the second switch, and the second switch is connected to the second digital signal. 4 . A second Ethernet signal conversion device is arranged between the receiving parts, the electrical signals of the N cables are transmitted to the second Ethernet signal conversion device through the second switch, and the converted signal is transmitted to the second digital signal receiving part. 4. A data transmission system according to claim 2, characterized in that: the second digital signal processing part comprises a framing module, a clock domain transformation module, a scrambling module, an encoding module, and a link error detection module , a parallel-serial conversion module, a high-speed serial transceiver module, and N circuits of electrical signals are aggregated into M circuits of electrical signals through the above modules. 5 . The data transmission system according to claim 1 , wherein the first data transmission unit comprises a first digital signal receiving part and a first digital signal processing part, and the optical signal receiving end is connected to the first digital signal receiving part. 6 . The photoelectric conversion device is connected, and the first photoelectric conversion device converts the received T-channel optical signal into M-channel electrical signal, and then transmits it to the first digital signal receiving part, and the M-channel electrical signal passes through the first digital signal processing part. After processing, it is restored to N circuits of electrical signals and transmitted to the corresponding N circuits of cables, or, the first digital signal receiving part sends the M circuits of electrical signals to another photoelectric conversion device, and then transmits the converted signals to another. The data transmission unit sends, the N≥1, M≤N, T≤N. 6. A data transmission system according to claim 5, wherein the first digital signal processing part is connected with the first switch through the first Ethernet signal conversion device, and the first switch is connected with the corresponding N-way cables, The N circuits of electrical signals are converted by the first Ethernet converting device and then transmitted to the first switch, and then transmitted to the N circuits of cables. 7. A data transmission system according to claim 5, characterized in that: the first digital signal processing part comprises a serial-to-parallel conversion module, a link error detection module, a decoding module, a descrambling module, and a clock domain transform module, deframing module, high-speed serial transceiver module, M circuit electrical signals are restored to N circuits electrical signals after being processed by the above modules. 8. An N-way data transmission method, characterized in that: the method uses the data transmission system described in any one of claims 1 to 7, and the method comprises the following steps: Step 1. The data generating source sends N electrical signals to the data transmission unit, where N≥1; Step 2, the data transmission unit receives the N circuits of electrical signals, and aggregates and converts the N circuits of electrical signals to generate M circuits of electrical signals, where M≤N; Step 3. The M circuits of electrical signals are converted into T circuits of optical signals by the photoelectric conversion device, where T≤N; Step 4: The T-path optical signal is sent through the optical signal sending end, and is transmitted by the T-path optical fiber. 9. A kind of N-way data transmission method according to claim 8, it is characterized in that: in the data aggregation conversion process, described N-way electrical signal passes through the framing module in the data transmission unit, according to the frame format set Assemble, and output the M circuit electrical signals through the encoding module, the parallel-serial conversion module, and the high-speed serial transceiver module. 10. A kind of N-way data transmission method according to claim 8, it is characterized in that: data transmission unit sets clock domain, comprises Ethernet clock domain, framing/deframe, check processing clock domain, signal sending and receiving clock domain ;Ethernet clock domain includes Gigabit Ethernet clock domain, Fast Ethernet clock domain, Gigabit Ethernet clock domain includes Gigabit Ethernet acquisition module, Fast Ethernet clock domain includes Fast Ethernet acquisition module, framing The clock domain for de-framing and verification processing includes framing/de-framing modules, and the signal transceiver clock domain includes high-speed serial transceiver modules, link error detection modules, 64B/66B encoding/decoding modules, and parallel-serial/serial-parallel conversion modules. , scrambling/descrambling module; each clock domain is isolated by asynchronous FIFO, and in the process of data aggregation conversion, the clock domain transformation module handles the conversion between multiple clock domains. 11. A kind of N-way data transmission method according to claim 8, it is characterized in that: in the data aggregation conversion process, the scrambling code module in the data transmission unit through the coded serial data input, after the scrambling code calculation, output scrambled data. 12. A kind of N-way data transmission method according to claim 8, is characterized in that: in the data aggregation conversion process, in the data transmission unit, the test code generator of the link error code detection module sending part, produces a test number The sequence, after encoding, is sent to the input end of the data transmission unit, and is output after being transmitted by the data transmission unit. 13. A method for receiving optical signal data, using the data transmission system according to any one of claims 1 to 7, the method comprising the following steps: Step 1. The optical signal source sends T optical signals to the data transmission unit, and the T optical signals are transmitted by T optical fibers; Step 2, the T-path optical signal is converted into the M-path electrical signal through the photoelectric conversion device; Step 3, the data transmission unit performs a signal separation operation on the M circuits of electrical signals to obtain a target signal, and the target signal is composed of N circuits of sub-signals; Step 4, sending the N-way sub-signals to the data application terminal; Said N≥1, M≤N, T≤N. 14. A method for receiving optical signal data according to claim 13, characterized in that: in the process of signal separation operation, the M circuits of electrical signals pass through the serial-to-parallel conversion module and the decoding module to recover the data frame form, The module outputs the target signal. 15. A method for receiving optical signal data according to claim 13, characterized in that: the data transmission unit is provided with a plurality of clock domains, including an Ethernet clock domain, a framing/de-framing, a check processing clock domain, a signal transceiving Clock domain; Ethernet clock domain includes Gigabit Ethernet clock domain, Fast Ethernet clock domain, Gigabit Ethernet clock domain includes Gigabit Ethernet acquisition module, Fast Ethernet clock domain includes Fast Ethernet acquisition module, Framing/de-framing, check processing clock domain includes framing/de-framing module, signal transceiver clock domain includes high-speed serial transceiver module, link error detection module, 64B/66B encoding/decoding module, parallel-serial/serial-parallel module Conversion module, scrambling/descrambling module; each clock domain is isolated by asynchronous FIFO. During the signal separation operation, the clock domain transformation module handles the conversion between multiple clock domains. 16. A method for receiving optical signal data according to claim 13, characterized in that: in the process of signal separation operation, the scrambled data is input into the descrambling module, after calculation, the descrambled data is output, and then in the decoding module to decode. 17. A method for receiving optical signal data according to claim 13, characterized in that: in the signal separation operation process, in the data transmission unit, the signal enters the receiving part of the link error detection module for decoding, and deciphers the signal from the signal. To get the synchronization clock, the test code generator of the receiving part generates the same and synchronized digital sequence as the transmitting part, and compares it with the received signal. Record storage, analysis, display test results.

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