CN115206999A - Wiring structure, semiconductor device and electronic equipment - Google Patents

Abstract

The present disclosure provides a routing structure and an electronic device. This walk the line structure and include: the first insulating layer, the first routing layer, the second insulating layer and the second routing layer are sequentially stacked; the first routing layer comprises adjacent first routing wires, a boss protruding towards the second routing layer is formed in an area, opposite to the first routing wires, of the surface of one side, far away from the first routing layer, of the second insulating layer, the second routing layer comprises second routing wires and third routing wires, orthographic projections of the second routing wires and the third routing wires on the first insulating layer are intersected with the orthographic projection of the first routing wires on the first insulating layer, and sections between the second routing wires and the third routing wires in edges of two sides of the first routing wires respectively comprise at least one corner point. The short circuit risk of the second wire and the third wire in the wire structure is reduced.

Description

Trace structures, semiconductor devices and electronic equipment

technical field

The present disclosure belongs to the field of electronic technology, and in particular relates to a wiring structure, a semiconductor device and an electronic device.

Background technique

This section is intended to provide background or context for the embodiments recited in the claims. The descriptions herein are not admitted to be prior art by inclusion in this section.

No matter in semiconductor devices such as display panels, touch panels, display touch panels, integrated circuits, etc., there will be multi-layer wirings. Two adjacent layers of traces are separated by an insulating layer. Two adjacent traces on the same layer should avoid short circuits.

SUMMARY OF THE INVENTION

The present disclosure provides a wiring structure, a semiconductor device and an electronic device.

The present disclosure adopts the following technical solutions: a wiring structure, comprising: a first insulating layer, a first wiring layer, a second insulating layer, and a second wiring layer that are stacked in sequence; the first wiring layer includes a first wiring layer. A trace, a region opposite to the first trace on the surface of the second insulating layer on the side away from the first trace layer forms a boss that protrudes toward the second trace layer, and the The second wiring layer includes adjacent second wirings and third wirings, and the orthographic projections of the second wirings and the third wirings on the first insulating layer are the same as the first wirings The orthographic projections of the first insulating layer intersect, wherein, on both sides of the first trace, the sections between the second trace and the third trace each include at least one corner point.

In some embodiments, at least one side edge of the first trace has: at least one concave segment or at least one protruding segment to form the corner point.

In some embodiments, at least one side edge of the first routing wire has an oval or circular recessed segment recessed toward the opposite side edge, and a straight line segment connected to the recessed segment.

In some embodiments, at least one side edge of the first routing wire has: an oval or circular protruding segment protruding in a direction away from the opposite side edge, and a straight line segment connected to the protruding segment .

In some embodiments, at least one side edge of the first routing wire has: a rectangular or trapezoidal recessed segment recessed toward the opposite side edge, and a straight line segment connected to the recessed segment.

In some embodiments, at least one side edge of the first routing wire has: a rectangular or trapezoidal protruding segment protruding in a direction away from the opposite side edge, and a straight line segment connected to the protruding segment.

In some embodiments, the first wire is bent, so as to form a corner point between the second wire and the third wire at at least one bend of the edges of both sides of the first wire.

In some embodiments, the first wiring is a segment of the touch sensing electrodes, the second wiring is a segment of the touch driving electrodes, and the third wiring is a ground protection line part of the line.

In some embodiments, a surface of the first insulating layer on a side close to the first wiring layer is a flat surface.

The present disclosure adopts the following technical solutions: a semiconductor device, comprising: the aforementioned wiring structure.

The present disclosure adopts the following technical solutions: an electronic device, comprising: the aforementioned semiconductor device.

Description of drawings

FIG. 1 is an effect diagram of poor short circuit between two adjacent traces in the related art.

FIG. 2 to FIG. 6 are schematic diagrams of the formation process of the defective phenomenon shown in FIG. 1 .

FIG. 7 to FIG. 12 are layouts of wiring structures provided by embodiments of the present disclosure.

The reference signs are as follows: 1. The first insulating layer; 2. The first wiring; 3. The second insulating layer; 4. The second wiring; 5. The third wiring; 6. Photoresist; 7. Residual 8. Conductor layer; H, via hole.

Detailed ways

The present disclosure will be further described below with reference to the embodiments shown in the accompanying drawings.

FIG. 1 is an effect diagram of poor wiring short circuit in the related art. Specifically, the wiring structure is integrated in the touch display panel, and a display function layer (not shown) is provided on the side of the first insulating layer 1 away from the first wiring layer. The display functional layer realizes, for example, an organic light emitting diode (OLED) display. The first trace 2 is a section of the touch sensing electrodes, the second trace 4 is a section of the touch drive electrodes, and the third trace 5 is a section of the ground protection line. The first trace 2 and the second trace 4 and the first trace 2 and the third trace 5 are separated by the second insulating layer 3 . In an actual manufacturing process, the first trace 2 is formed before the second trace 4 and the third trace 5 . In order to reduce the resistance of the touch sensing electrodes, the touch driving electrodes and the ground protection lines, some sections of these electrodes or lines are double-layered at the edge area of the touch display panel, and via holes are passed between the double-layered lines. H forms an electrical connection. At the intersections of the touch sensing electrodes and the touch driving electrodes, and at the intersections of the touch sensing electrodes and the ground protection lines, they are all single-layer wiring. The ground protection lines are arranged at intervals on both sides of the touch drive electrodes (only the ground protection lines on one side of the touch drive electrodes are shown in FIG. 1 ) to shield electromagnetic interference.

Referring to FIG. 1 , the inventors of the present disclosure have found that, in the wiring layer (ie, the second wiring layer) where the second wiring 4 (the third wiring 5 ) is located, it is easy to generate an extension along the extending direction of the first wiring 2 . And the remaining traces 7 located on both sides of the first trace 2 . The remaining traces 7 easily lead to a short circuit between the second traces 4 and the third traces 5 , resulting in failure of the display touch panel.

The inventors of the present disclosure have further researched and discovered the formation mechanism of the residual traces 7 . 2 to 6 are schematic views of the formation process of the defect shown in FIG. 1 .

Referring to FIG. 2 , firstly, a first wiring 2 is formed on the first insulating layer 1 . The second insulating layer 3 is then formed. Since the surface on which the second insulating layer 3 is located is not flat, the second insulating layer 3 above the first trace 2 protrudes upward to form a boss having substantially the same position and orientation as the first trace 2 .

Referring to FIG. 3 , an entire conductor layer 8 is formed, and then a layer of photoresist 6 is coated on the conductor layer 8 . Since the top surface of the second insulating layer 3 forms a boss, the conductor layer 8 and the top surface of the photoresist 6 at the position of the boss form a boss. A distinct slope is formed at the edge of the boss.

Referring to FIG. 4 , the photoresist 6 is not sufficiently exposed at the slope position of the photoresist 6 , and the photoresist 6 is likely to remain at the position after exposure and development processes.

Referring to FIG. 5 , the conductor layer 8 is subsequently etched. Due to the influence of the remaining photoresist 6 , the conductor layer 8 under the remaining photoresist 6 will not be removed.

Referring to FIG. 6 in combination with FIG. 1 , after the photoresist 6 is removed, two residual traces 7 are formed on both sides of the first trace 2 . The remaining traces 7 can easily short-circuit the second traces 4 and the third traces 5 .

Based on the above analysis, the inventor of the present disclosure proposes an idea: if there is a break point in the residual trace 7, the short circuit risk of the second trace 4 and the third trace 5 will be reduced.

In order to realize the above concept, referring to FIGS. 7 to 12 , the present disclosure provides a wiring structure including: a first insulating layer 1 , a first wiring layer, a second insulating layer 3 , and a second wiring layer that are stacked in sequence. ; The first wiring layer includes a first wiring 2, and the area opposite to the first wiring 2 in the surface of the second insulating layer 3 on the side away from the first wiring layer forms a raised boss toward the second wiring layer , the second trace layer includes adjacent second traces 4 and third traces 5 , and the orthographic projections of the second traces 4 and the third traces 5 on the first insulating layer 1 are both in the first trace 2 The orthographic projections of the first insulating layer 1 intersect, wherein, on both sides of the first trace 2 , the sections between the second trace 4 and the third trace 5 include at least one corner point.

In the second wiring layer, there is no other wiring between the second wiring 4 and the third wiring 5 .

If one side edge of the first trace 2 is regarded as a continuous line in the plane rectangular coordinate system, the left derivative and right derivative of this line at the corner point are not equal.

In some embodiments, the material of the first insulating layer 1 includes at least one of silicon nitride, silicon oxide, silicon oxynitride, polyimide, and glass.

In some embodiments, the first insulating layer 1 is a substrate in a display panel or a substrate in a touch panel. In other embodiments, the first insulating layer 1 is a display panel, a touch panel or an insulating layer inside the display touch panel. In other embodiments, the first insulating layer 1 is an insulating layer inside the integrated circuit.

In some embodiments, the material of the first trace 2 includes at least one of molybdenum (Mo), titanium (Ti), and copper (Cu). In other embodiments, the first trace 2 is a titanium/aluminum/titanium multi-layer metal structure. In other embodiments, the material of the first trace 2 includes a transparent conductor material such as indium tin oxide.

In some embodiments, the first trace 2 is a section of trace of the touch sensing electrode or the touch driving electrode. In other embodiments, the first trace 2 is a trace of any function in a display panel, a display touch panel, a touch panel or an integrated circuit.

In some embodiments, the material of the second insulating layer 3 includes at least one of silicon nitride, silicon oxide, silicon oxynitride, and polyimide.

In some embodiments, the second insulating layer 3 is a display panel, a display touch panel or an insulating layer inside the touch panel. In other embodiments, the second insulating layer 3 is an insulating layer inside the integrated circuit.

In some embodiments, the material of the second trace 4 includes at least one of molybdenum (Mo), titanium (Ti), and copper (Cu). In other embodiments, the second wiring 4 is a titanium/aluminum/titanium multi-layer metal structure. In other embodiments, the material of the second trace 4 includes a transparent conductor material such as indium tin oxide.

In some embodiments, the second wiring 4 is a segment of the touch driving electrode or the touch sensing electrode. In other embodiments, the second wiring 4 is a wiring of a display panel, a touch panel, a display touch panel, or any function in an integrated circuit.

The edges on both sides of the first trace 2 are neither straight lines nor smooth curves, but have corner points. This causes abrupt changes in the direction of the residual traces 7 at these corner points. When the direction of the residual traces 7 changes greatly, the residual traces 7 are easily disconnected at the corner points. After the residual trace 7 is disconnected into multiple traces, through proper design, both the residual trace 7 connected to the second trace 4 and the residual trace 7 connected to the third trace 5 can also be disconnected It's open. This keeps the disconnected state between the second wiring 4 and the third wiring 5 .

In some embodiments, at least one side edge of the first wiring 2 has: at least one concave segment or at least one protruding segment to form the above-mentioned corner point. The edge of the first trace 2 may form a corner point at the junction of the recessed segment and the non-recessed segment (usually a straight segment). The edge of the first routing line 2 may form a corner point at the junction of the protruding segment and the non-protruding segment (usually a straight segment).

In some embodiments, at least one side edge of the first wiring 2 has: an oval or circular recessed segment recessed toward the opposite side edge, and a straight line segment connected to the recessed segment.

Referring to FIG. 7 , between the second trace 4 and the third trace 5 , two sides of the first trace 2 each have an oval recessed segment, and each oval recessed segment is connected to the first trace. Two corner points are formed where the straight line segments of the 2 edges are connected. The residual traces 7 in the trace layer where the second traces 4 and the third traces 5 are located are easily disconnected at these two corner points, so as to avoid short circuits between the second traces 4 and the third traces 5 .

In some embodiments, at least one side edge of the first wiring 2 has: an oval or circular protruding segment protruding in a direction away from the opposite side edge, and a straight segment connected to the protruding segment.

Referring to FIG. 8 , between the second wiring 4 and the third wiring 5 , the two sides of the first wiring 2 each have an oval protruding segment, and each oval protruding segment is connected to the first wiring Two corner points are formed where the straight line segments on the edge of line 2 are connected. The residual traces 7 in the trace layer where the second traces 4 and the third traces 5 are located are easily disconnected at these two corner points, so as to avoid short circuits between the second traces 4 and the third traces 5 .

In some embodiments, at least one side edge of the first wiring 2 has: a rectangular or trapezoidal recessed segment recessed toward the opposite side edge, and a straight line segment connected to the recessed segment.

Referring to FIG. 9 , between the second trace 4 and the third trace 5 , two sides of the first trace 2 each have a rectangular recessed segment, and each rectangular recessed segment is connected to the edge of the first trace 2 Two corner points are formed at the connecting position of the straight line segments of each rectangle, and there are also two corner points inside the concave segment of each rectangle. The remaining traces 7 in the second trace layer where the second traces 4 and the third traces 5 are located are easily disconnected at these four corner points, so as to avoid short circuits between the second traces 4 and the third traces 5 .

In some embodiments, at least one side edge of the first routing wire 2 has: a rectangular or trapezoidal protruding segment protruding in a direction away from the opposite side edge, and a straight line segment connected to the protruding segment.

Referring to FIG. 10 , between the second wiring 4 and the third wiring 5 , the two sides of the first wiring 2 each have a rectangular protruding segment, and each rectangular protruding segment is connected to the first wiring Two corner points are formed at the position where the straight line segments of the two edges are connected, and each rectangular protruding segment itself also has two corner points. The residual traces 7 in the second trace layer where the second traces 4 and the third traces 5 are located are easily disconnected at these four corner points, so as to avoid short circuits between the second traces 4 and the third traces 5 .

In some embodiments, the first trace 2 is bent, so as to form a corner point between the second trace 4 and the third trace 5 at at least one bend of the two edges thereof.

Referring to FIG. 11 , between the second wiring 4 and the third wiring 5 , the first wiring 2 is bent. Thereby, a corner point between the second trace 4 and the third trace 5 is formed on both sides of the first trace 2 .

The above embodiments of forming a corner point on the edge of the first trace 2 can be used in combination. For example, referring to FIG. 12 , the first wiring 2 is in a bent shape and has a plurality of concave segments formed on the edges of both sides thereof.

In some embodiments, the surface of the first insulating layer 1 on the side close to the first wiring layer is a flat surface. Referring to FIG. 3, when the surface of the first insulating layer 1 close to the first wiring layer is a flat surface, the slope of the photoresist 6 above the first wiring 2 is more obvious. After exposure and development, the photoresist 6 has an obvious slope. residues are also more pronounced.

Of course, in other embodiments, the first trace 2 is semi-embedded in the first insulating layer 1 .

Based on the same inventive concept, embodiments of the present disclosure further provide a semiconductor device, including: the aforementioned wiring structure.

The electronic semiconductor device is, for example, a display panel, a touch panel, a touch display panel, an integrated circuit, or any other device with multi-layer wirings.

Based on the same inventive concept, embodiments of the present disclosure also provide an electronic device including the aforementioned semiconductor device.

Examples of electronic devices are: display modules, display touch modules, mobile phones, tablet computers, navigators, vehicle display screens, monitors, wearable electronic products, etc.

The various embodiments in the present disclosure are described in a progressive manner, and the same and similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments.

The protection scope of the present disclosure is not limited to the above-mentioned embodiments. Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the scope and spirit of the present disclosure. Provided that these changes and modifications fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these changes and modifications.

Claims (10)

1. A trace structure, comprising: the first insulating layer, the first routing layer, the second insulating layer and the second routing layer are sequentially stacked; the first routing layer comprises a first routing line, a boss protruding towards the second routing layer is formed in an area, opposite to the first routing line, of the surface of one side, far away from the first routing layer, of the second insulating layer, the second routing layer comprises a second routing line and a third routing line which are adjacent, orthographic projections of the second routing line and the third routing line on the first insulating layer are intersected with the orthographic projection of the first routing line on the first insulating layer, and sections between the second routing line and the third routing line in edges of two sides of the first routing line respectively comprise at least one corner point.

2. The trace structure according to claim 1, wherein at least one side edge of the first trace has: at least one concave section or at least one convex section to form the corner points.

3. The trace structure according to claim 2, wherein at least one side edge of the first trace has: an oval or circular recessed section recessed toward the opposite side edge, and a straight line section connected to the recessed section.

4. The trace structure according to claim 2, wherein at least one side edge of the first trace has: an oval or circular protruding section protruding in a direction away from the opposite side edge, and a straight line section connected to the protruding section.

5. The trace structure according to claim 2, wherein at least one side edge of the first trace has: a rectangular or trapezoidal concave section concave towards the opposite side edge, and a straight line section connected with the concave section.

6. The trace structure according to claim 2, wherein at least one side edge of the first trace has: a rectangular or trapezoidal projecting section projecting in a direction away from the opposite side edge, and a straight line section connected to the projecting section.

7. The trace structure according to claim 1, wherein the first trace is bent to form corner points between the second trace and the third trace at least one bend at two side edges thereof.

8. The trace structure according to claim 1, wherein the first trace is a segment of trace in the touch sensing electrode, the second trace is a segment of trace in the touch driving electrode, and the third trace is a segment of trace in the ground protection line.

9. A semiconductor device, comprising: a trace arrangement according to any one of claims 1 to 8.

10. An electronic device, comprising: the semiconductor device of claim 9.

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