CN115148782A - Method of forming a semiconductor structure - Google Patents
Method of forming a semiconductor structure Download PDFInfo
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- CN115148782A CN115148782A CN202110344769.5A CN202110344769A CN115148782A CN 115148782 A CN115148782 A CN 115148782A CN 202110344769 A CN202110344769 A CN 202110344769A CN 115148782 A CN115148782 A CN 115148782A
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- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
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- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
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Abstract
一种半导体结构的形成方法，方法包括：提供基底，所述基底包括衬底以及位于所述衬底上分立的鳍部；在鳍部露出的衬底上形成隔离结构，隔离结构覆盖鳍部的侧壁；形成隔离结构后，对鳍部进行阱区注入；进行阱区注入后，回刻蚀部分厚度的隔离结构，露出鳍部的部分侧壁；回刻蚀部分厚度的所述隔离结构之后，对鳍部进行阱区注入后的退火工艺。降低了晶格损伤在退火工艺中形成位错缺陷的概率，从而有利于提高半导体结构的电学性能。
A method for forming a semiconductor structure, the method comprising: providing a base, the base comprising a substrate and discrete fins on the substrate; forming an isolation structure on the exposed substrate of the fin, the isolation structure covering the fins sidewalls; after the isolation structure is formed, the fin is implanted into the well region; after the well region implantation, the isolation structure with a partial thickness is etched back to expose part of the sidewall of the fin; after the isolation structure with a partial thickness is etched back , and perform the annealing process after the implantation of the well region on the fin. The probability of lattice damage to form dislocation defects in the annealing process is reduced, thereby facilitating the improvement of the electrical properties of the semiconductor structure.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
In Semiconductor manufacturing, with the trend of ultra-large scale integrated circuits, feature sizes of integrated circuits are continuously decreasing, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-Semiconductor Field-Effect transistors (MOSFETs) is also continuously decreasing. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the control capability of the gate structure to the channel is deteriorated, the difficulty of the gate voltage to pinch off the channel is increased, and the sub-threshold leakage (SCE) phenomenon, i.e. the so-called short-channel effect (SCE), is easier to occur.
Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.
Disclosure of Invention
The embodiment of the invention provides a method for forming a semiconductor structure, which is beneficial to improving the electrical property of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate and a discrete fin part positioned on the substrate; forming an isolation structure on the substrate exposed out of the fin portion, wherein the isolation structure covers the side wall of the fin portion; after the isolation structure is formed, well region injection is carried out on the fin part; after the well region is injected, the isolation structure with partial thickness is etched back, and partial side walls of the fin portion are exposed; and after the isolation structure with partial thickness is etched back, carrying out annealing process after well region injection on the fin part.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of forming an isolation structure on a substrate with exposed fin parts, wherein the isolation structure covers the side walls of the fin parts; after the isolation structure is formed, well region injection is carried out on the fin part; after the well region is injected, the isolation structure with partial thickness is etched back, and partial side walls of the fin portion are exposed; and after the isolation structure with partial thickness is etched back, carrying out annealing process after well region injection on the fin part. The fin part is easy to be damaged by crystal lattices in the well region injection process, in the process of forming the isolation structure, larger stress is usually generated on the fin part, under the condition that internal stress exists, the crystal lattices in the fin part are easy to form dislocation defects in the subsequent annealing process after the well region injection, and the size of the stress generated by the isolation structure is positively correlated with the size of the stress.
In an alternative, the well region implant has predetermined conditions including one or both of heating the substrate during the implant and a low ion beam current, the low ion beam current being less than or equal to 200 μ Α. In the process of well region injection under the preset condition, kinetic energy of injected ions and atoms (for example, silicon atoms) in the fin portion material can be increased, so that attractive force or repulsive force is generated between the injected ions and the atoms in the fin portion material, and the atoms in crystal lattices can be arrayed in order again, accordingly, probability of crystal lattice damage caused in the well region injection process is reduced, and subsequently, after the isolation structure with partial thickness is etched back, when the fin portion is subjected to an annealing process after well region injection, probability of dislocation defects formed in the annealing process due to crystal lattice damage of the fin portion is reduced, and therefore electrical performance of the semiconductor structure is improved.
Drawings
Fig. 1to 7 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
At present, the electrical performance of the semiconductor device is still to be improved. The reason why the electrical properties of the semiconductor structure still need to be improved is analyzed by combining with a forming method of the semiconductor structure.
The forming method of the semiconductor structure comprises the following steps: providing a base, wherein the base comprises a substrate and a discrete fin part positioned on the substrate; forming an isolation structure on the substrate with the exposed fin part, wherein the isolation structure covers the side wall of the fin part; after the isolation structure is formed, well region injection is carried out on the fin part; after the well region injection is carried out, forming an annealing process after the well region injection on the fin part; and after the annealing process is carried out, etching back the isolation structure with partial thickness to expose partial side walls of the fin part.
Specifically, the fin portion is easily subjected to lattice damage in the well region injection process, in the process of forming the isolation structure, the isolation structure covers the whole side wall of the fin portion, the isolation structure usually generates large stress on the fin portion, and under the condition that the internal stress exists, the lattice damage in the fin portion is easily subjected to dislocation defect formation in the subsequent annealing process after the well region injection, so that the electrical performance of the semiconductor device is reduced.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate and a discrete fin part positioned on the substrate; forming an isolation structure on the substrate with the exposed fin part, wherein the isolation structure covers the side wall of the fin part; after the isolation structure is formed, well region injection is carried out on the fin part; after the well region is injected, the isolation structure with partial thickness is etched back, and partial side walls of the fin portion are exposed; and after the isolation structure with partial thickness is etched back, carrying out annealing process after well region injection on the fin part.
In the forming method provided by the embodiment of the invention, an isolation structure is formed on a substrate with exposed fin parts, and the isolation structure covers the side walls of the fin parts; after the isolation structure is formed, well region injection is carried out on the fin part; after the well region is injected, etching back the isolation structure with partial thickness to expose partial side walls of the fin part; and after the isolation structure with partial thickness is etched back, carrying out annealing process after well region injection on the fin part. The fin part is easy to be damaged by crystal lattices in the process of well region injection, in the process of forming the isolation structure, the fin part is usually subjected to larger stress, under the condition that internal stress exists, dislocation defects are easy to form in the subsequent annealing process after the well region injection, and the size of the stress generated by the isolation structure is positively correlated with the size of the stress, so that the isolation structure with partial thickness is etched back firstly after the fin part is subjected to the well region injection by exchanging the sequence of process steps, the effect of reducing the size of the isolation structure is achieved, the influence of the internal stress of the isolation structure on the exposed fin part is reduced or eliminated, and when the annealing process after the fin part is subjected to the well region injection is carried out, the probability of forming the dislocation defects in the fin part is greatly reduced, and the electrical performance of the semiconductor structure is improved.
In an alternative, the well region implant has predetermined conditions including one or both of heating the substrate during the implant and a low ion beam current, the low ion beam current being less than or equal to 200 μ Α. In the process of well region injection under the preset condition, kinetic energy of injected ions and atoms (for example, silicon atoms) in the fin portion material can be increased, so that attractive force or repulsive force is generated between the injected ions and the atoms in the fin portion material, and the atoms in crystal lattices can be arrayed in order again, accordingly, probability of crystal lattice damage caused in the well region injection process is reduced, and subsequently, after the isolation structure with partial thickness is etched back, when the fin portion is subjected to an annealing process after well region injection, probability of dislocation defects formed in the annealing process due to crystal lattice damage of the fin portion is reduced, and therefore electrical performance of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 1to 7 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 1, a base is provided, which includes a substrate 100 and a discrete fin 101 on the substrate 100.
The substrate is used for providing a process platform for subsequent process procedures.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the semiconductor structure is a fin field effect transistor, and the discrete fin 101 on the substrate 100 is used to provide a channel of the fin field effect transistor.
In this embodiment, the fin 101 and the substrate 100 are an integral structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate.
Therefore, in this embodiment, the material of the fin 101 is the same as that of the substrate 100, and the material of the fin 101 is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming a fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the fin may also be different from that of the substrate.
In this embodiment, the steps of forming the substrate 100 and the fin portion 101 include: providing an initial substrate (not shown); forming a fin mask layer 102 on the initial substrate; and etching the initial base by taking the fin part mask layer 102 as a mask, wherein the etched residual initial base is taken as the substrate 100, and the protrusion on the substrate 100 is taken as the fin part 101.
It should be noted that, after the fin portion 101 is formed, the fin portion mask layer 102 on the top of the fin portion 101 is retained, the fin portion mask layer 102 is made of silicon nitride, in a subsequent process of forming the isolation structure, the top surface of the fin portion mask layer 102 can be used for defining a stop position of a planarization process, and the fin portion mask layer 102 can also play a role in protecting the top of the fin portion 101. In other embodiments, the fin mask layer may be further made of silicon oxynitride.
In this embodiment, the fin mask layer 102 is formed by deposition, photolithography, and etching processes. In other embodiments, in order to reduce the feature size of the fin, the pitch (pitch) between adjacent fins may be reduced, and the fin mask layer may be formed by a multiple patterning process. The multiple patterning mask process comprises the following steps: a Self-Aligned Double patterning (SADP) process, a Self-Aligned Triple patterning (SATP) process, a Self-Aligned Double patterning (SADDP) process, a Double photolithography and etching (LELE) process, etc.
Referring to fig. 2, an isolation structure 104 is formed on the substrate 100 where the fin 101 is exposed, and the isolation structure 104 covers a sidewall of the fin 101.
The isolation structure 104 is used to isolate neighboring devices. The material of the isolation structure 104 may be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the isolation structure 104 is made of silicon oxide.
In this embodiment, the step of forming the isolation structure 104 includes: forming an isolation material layer (not shown) on the substrate 100 exposed by the fin 101, wherein the isolation material layer also covers the top surface of the fin mask layer 102; with the top surface of the fin portion mask layer 102 as a stop position, performing planarization processing on the isolation material layer; the remaining layer of isolation material serves as isolation structures 104. Thus, at this time, the isolation structure 104 covers the entire sidewall of the fin 101.
In this embodiment, the process of forming the isolation structure 104 includes fluid chemical vapor deposition.
The fluid chemical vapor deposition process has the characteristics of good deposition uniformity, good compactness and high coverage rate, and is more suitable for filling gaps with high aspect ratios. In this embodiment, the flowable medium fills the trenches between adjacent fins, and the isolation structures 104 are formed between adjacent fins 101.
Referring to fig. 3, the fin mask layer 102 on top of the fin 101 is removed.
The top of the fin portion 101 is exposed by removing the fin portion mask layer 102 on the top of the fin portion 101, so that a process basis is provided for performing well region injection on the fin portion 101 subsequently.
Specifically, the step of removing the fin mask layer 102 on the top of the fin 101 includes: and etching and removing the fin part mask layer 102 by taking the isolation structure 104 as a mask.
In this embodiment, the fin mask layer 102 is removed by etching using a wet etching process.
The wet etching process has an isotropic etching characteristic, and thus, the etching rate of the fin mask layer 102 is improved, and the fin mask layer 102 embedded in the isolation structure 104 is removed cleanly. In addition, through the wet etching process, the etching selectivity of the etching process is easy to realize, and the process controllability is good.
In this embodiment, the fin mask layer 102 is made of silicon nitride, and thus, an etching solution of the wet etching process is a hot phosphoric acid solution.
Referring to fig. 4, after the isolation structure 104 is formed, well region implantation is performed on the fin 101.
It should be noted that the fin 101 is easily damaged by crystal lattices during the well region injection process, a large stress is usually generated on the fin 101 during the formation of the isolation structure 104, and then an annealing process after the well region injection is further performed, and in the presence of an internal stress, dislocation defects are easily formed in the crystal lattice damage in the fin 101 in the subsequent annealing process after the well region injection.
It is further noted that in other embodiments, the well region implant has predetermined conditions including one or both of heating the substrate during the implant and a low ion beam current, the low ion beam current being less than or equal to 200 μ Α.
In the process of well region injection under the preset condition, the kinetic energy of injected ions and silicon atoms can be increased, so that attractive force or repulsive force is generated between the injected ions and the silicon atoms, atoms in crystal lattices can be arrayed orderly again, correspondingly, the probability of crystal lattice damage caused in the well region injection process is reduced, and when the fin part is subjected to the annealing process after the fin part is subjected to the well region injection after the isolation structure with partial thickness is etched back, the probability of the crystal lattice damage on the fin part is reduced, so that the probability of dislocation defects formed by the crystal lattice damage in the subsequent annealing process is also greatly reduced, and the electrical property of the semiconductor structure is improved.
When the semiconductor structure is an N-type transistor, in the process of carrying out well region injection on the fin portion, the type of injected ions is P type. In other embodiments, when the semiconductor structure is a P-type transistor, the implanted ion type is N-type during the well region implantation of the fin portion.
It should be noted that, the sidewall of the adjacent fin portion is covered with an isolation structure, and in the process of performing well region injection on the fin portion, the isolation structure can protect the top of the substrate, and reduce the probability of generating lattice damage to the substrate.
It should be further noted that, during the implantation of the well region into the fin portion, the implantation of the well region has a predetermined condition, and the predetermined condition includes one or both of heating the substrate and a low ion beam current during the implantation.
Taking heating the substrate as an example of the preset condition for the well region implantation, that is, the process adopted by the well region implantation is a hot ion implantation (hot implant) process.
By heating the substrate in the injection process, the kinetic energy of injected ions and silicon atoms can be increased, so that attractive force or repulsive force is generated between the injected ions and the silicon atoms, the atoms in the crystal lattice can be arrayed regularly again, the probability of crystal lattice damage caused in the well region injection process is further reduced, and the probability of dislocation defects formed in the subsequent annealing process is also greatly reduced.
The substrate is heated at a temperature of 50 ℃ to 500 ℃.
It should be noted that the temperature at which the substrate is heated is not too high nor too low. If the temperature value for heating the substrate is too large, the diffusion area of the implanted ions in the substrate is easily too large, and the process requirements cannot be met; if the temperature value for heating the substrate is too low, the repairing effect of the crystal lattice damage generated on the fin portion is poor in the well region injection process, and the probability of generating dislocation defects is increased in the subsequent annealing process. For this purpose, the substrate is heated at a temperature of 50 ℃ to 500 ℃. For example, the substrate is heated at a temperature of 100 ℃, 200 ℃, or 300 ℃.
In some other embodiments, the well region implantation of the fin portion may further include performing the well region implantation with a low ion beam current, wherein the low ion beam current is less than or equal to 200 μ Α.
The well region injection is carried out by adopting low ion beam current, so that the kinetic energy of injected ions and silicon atoms can be increased, and the injected ions and the silicon atoms generate attraction force or repulsion force mutually, so that the atoms in crystal lattices can be arrayed orderly again, the probability of crystal lattice damage caused in the well region injection process is reduced, and the probability of forming dislocation defects in the subsequent annealing process is also greatly reduced.
The current value of the low ion beam current is not too large nor too small. If the current value of the low ion beam current is too large, the probability of crystal lattice damage to the fin part is easily increased; if the current value of the low ion beam current is too small, the efficiency of the well region injection process is too low, the effect of repairing the crystal lattice damage cannot be well realized, and meanwhile, the process time and the cost are increased. For this reason, in the present embodiment, the current value of the ion beam current is 20 μ a to 200 μ a.
Referring to fig. 5, after the well region implantation, the isolation structure 104 is etched back by a portion of the thickness, exposing a portion of the sidewall of the fin 101.
Specifically, the fin 101 is easily subjected to lattice damage in the well region injection process, in the process of forming the isolation structure 104, a large stress is usually generated on the fin 101, under the condition that an internal stress exists, the lattice damage in the fin 101 is easily subjected to dislocation defects in a subsequent annealing process after the well region injection, and the magnitude of the stress generated by the isolation structure 104 is positively correlated with the volume of the isolation structure, so that the isolation structure 104 with a part of thickness is etched back first by exchanging the sequence of process steps in the embodiment, so that the effect of reducing the volume of the isolation structure 104 is achieved, the influence of the internal stress of the isolation structure 104 on the exposed fin 101 is reduced or eliminated, and the probability of forming the dislocation defects in the fin 101 is greatly reduced during the subsequent annealing process after the well region injection on the fin 101, thereby being beneficial to improving the electrical performance of the semiconductor structure.
In this embodiment, the process of etching back the isolation structure 104 with a partial thickness includes a dry etching process.
The dry etching process is an anisotropic dry etching process, and the anisotropic dry etching process has the characteristic of anisotropic dry etching, so that the longitudinal etching rate of the dry etching process is far greater than the transverse etching rate, the thickness reduction of the isolation structure 104 is favorably and accurately controlled, the top appearance of the residual isolation structure 104 is favorably improved, and the damage to the side wall of the fin part 101 is small.
Referring to fig. 6 to 7, the fin 101 is subjected to an annealing process 200 after well implantation.
After the fin portion 101 is implanted in the well region, the implanted ions are likely to damage the fin portion 101, and most of the implanted ions are not in the lattice position in an alternative form. Therefore, by performing the annealing process 200 at an appropriate temperature, the annealing process 200 can repair the lattice damage in the fin 101 and also move the implanted ions to the lattice points, thereby increasing the activity of the implanted ions and activating the ions.
In this embodiment, after etching back a portion of the thickness of the isolation structure 104, the annealing process 200 after the well region implantation is performed.
Because the magnitude of the stress generated by the isolation structure 104 is positively correlated with the volume thereof, the isolation structure 104 with partial thickness is etched back first to achieve the effect of reducing the volume of the isolation structure 104, so as to reduce or eliminate the influence of the internal stress of the isolation structure 104 on the exposed fin portion 101, and when the fin portion 101 is subjected to the annealing process 200 after well region injection, the probability of forming dislocation defects in the fin portion 101 is also greatly reduced.
The annealing process 200 after the well region implantation includes one or more of a temperature equalization annealing process, a spike annealing process, a millisecond annealing process, and a rapid thermal annealing process.
The Rapid Thermal Annealing (RTA) process refers to a process of rapidly increasing a temperature to a target temperature and then annealing the temperature in a short time. The rapid thermal annealing has a minimized diffusion effect, and the size of an ion implantation diffusion region can be well controlled. As an example, the annealing process 200 after the well region implantation is a rapid thermal annealing process.
In this embodiment, the parameters of the annealing process 200 after the well region implantation include: the reaction gas comprises N 2 、H 2 、NH 3 、O 2 And Ar; the process temperature is 500 ℃ to 1400 ℃; the process time is 0.1us to 60s; the chamber pressure is between 0.001torr and 780torr.
It should be noted that the process temperature should not be too high or too low. If the process temperature is too high, the depth of longitudinal diffusion of implanted ions is increased, and accordingly, the well region implantation area is easy to be out of line with the process requirement, and the electrical performance of the semiconductor is further influenced; if the process temperature is too low, the diffusion area of the implanted ions in the fin part is easily too small, correspondingly, the well region implanted area is easily not in line with the process requirement, and meanwhile, the effect of repairing the crystal lattice damage of the fin part is easily poor, so that the electrical performance of the semiconductor is affected. For this reason, in this embodiment, the process temperature is 500 ℃ to 1400 ℃.
It should be noted that the process time is not too long nor too short. If the process time is too long, the diffusion area of the doped ions injected into the well region is too large, so that the process requirement cannot be met, and the performance of the device is influenced; if the process time is too short, the activation efficiency of the doped ions is easily too low, and the process time and the process efficiency are influenced, so that the production cost of the process is increased. For this reason, in this embodiment, the process time is 0.1us to 60s.
It should be noted that the chamber pressure should not be too high or too low. If the pressure of the chamber is too high, a certain safety problem is easily caused to the machine in the annealing process; if the pressure of the chamber is too low, the activation efficiency of the doped ions is too low, which affects the process time and the process efficiency, thereby increasing the production cost of the process. For this purpose, the chamber pressure is 0.001to 780torr in this embodiment.
Referring to fig. 6, after etching back a portion of the thickness of the isolation structure 104, before performing the annealing process 200 after the well implantation, the method further includes: a protection layer 105 is formed on the sidewalls and the top of the fin 101 exposed by the remaining isolation structures 104.
In the annealing process 200 after well region injection, the probability that the material on the surface of the fin portion 101 is oxidized is higher, for example, because the fin portion 101 contains silicon atoms, the material on the surface of the fin portion 101 is easily oxidized into silicon oxide, so that the volume of the fin portion 101 is reduced, the structural strength and reliability of the fin portion 101 are affected, for this reason, before the annealing process 200 after well region injection is performed, a deposition process is utilized, a protective layer 105 is formed on the side wall and the top of the fin portion 101 exposed by the isolation structure 104, and the protective layer 105 plays a role in protecting the fin portion 101 exposed on the substrate 100 in the annealing process 200, so that the probability that the fin portion is damaged is reduced. Moreover, the protection layer 105 is formed by a deposition process, so that the consumption of the material of the fin portion 101 is low, and the influence on the line width size and the volume of the fin portion 101 is favorably reduced.
In this embodiment, the deposition process for forming the protection layer 105 includes an atomic layer deposition process.
The atomic layer deposition process includes performing multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the protection layer 105, and enabling the protection layer 105 to cover the sidewall of the fin portion 101. In other embodiments, the protective layer may also be formed by a Chemical Vapor Deposition (CVD) process.
In other embodiments, instead of forming the protection layer, a passivation gas may be used to perform a surface passivation on the fin portions exposed by the remaining isolation structures, so as to form the protection layer on the sidewalls and the top of the fin portions exposed by the remaining isolation structures.
And performing surface passivation treatment on the fin parts exposed by the residual isolation structures to form a protective layer on the surfaces of the fin parts, so that the fin parts exposed out of the substrate are protected in the annealing process after well region injection, and the probability of damage to the fin parts is reduced.
Specifically, in this embodiment, the passivation gas is an oxygen-containing gas, the surface passivation treatment is an oxidation treatment, and the protective layer formed after the surface passivation treatment is an oxide layer. That is, the fin portion exposed by the remaining isolation structure is subjected to surface passivation, so that the passivation gas and the material of the fin portion are subjected to oxidation reaction, an oxide layer (for example, a silicon oxide layer) conformally covering the fin portion is formed on the surface of the fin portion, and the fin portion is protected in a subsequent related process.
The passivating gas comprises O 2 、N 2 O and H 2 One or more of O.
Specifically, O 2 、N 2 O and H 2 And in the process of carrying out the annealing process, oxygen atoms react with silicon atoms in the fin part under a high-temperature environment to form silicon oxide on the surface of the fin part, so that the fin part is protected.
And in the step of performing the surface passivation treatment on the fin part exposed by the residual isolation structure, the temperature of the surface passivation treatment is 500-1200 ℃.
The temperature of the surface passivation treatment is not too high or too low. If the temperature of the surface passivation treatment is too high, the thickness of an oxide layer formed on the surface of the fin part is easily too large, and the subsequent manufacturing process of the metal gate structure is influenced; if the temperature of the surface passivation treatment is too low, the thickness of an oxide layer formed on the surface of the fin portion is too thin, the protection effect on the fin portion is reduced, and the performance of the semiconductor structure is affected. For this reason, in the step of performing the surface passivation treatment on the fin portion exposed by the remaining isolation structure, the temperature of the surface passivation treatment is 500 ℃ to 1200 ℃.
And in the step of performing the surface passivation treatment on the fin parts exposed by the residual isolation structures, the content of the passivation gas adopted is more than 10ppm.
The content of the passivation gas is not suitable to be too small, and if the content of the oxygen-containing gas is too small, the thickness of an oxide layer formed on the surface of the fin portion is too thin, so that the probability of silicon atom migration in the fin portion is increased in the subsequent process, and therefore defects are generated in the fin portion, and the performance of the semiconductor structure is affected.
It should be noted that, in this embodiment, a scheme of changing a process sequence between the etch-back isolation structure and the annealing process after the well region is implanted is adopted.
The scheme adopted by the embodiment can obviously reduce the probability of dislocation defects formed by the semiconductor device and improve the electrical performance of the semiconductor device.
In other embodiments, the following may be also possible: after the isolation structure is formed, performing well region injection on the fin part, wherein the well region injection has preset conditions; after the well region is injected, etching back the isolation structure with partial thickness to expose partial side walls of the fin part; and after the isolation structure with partial thickness is etched back, carrying out annealing process after the well region is injected. The fin portion receives the crystal lattice damage easily in well region injection process, at the in-process that forms isolation structure, can produce great stress to the fin portion usually, under the condition that internal stress exists, the crystal lattice damage in the fin portion forms the dislocation defect easily in the annealing process after the well region that follow-up goes on pours into, because the stress size that isolation structure produced is positive correlation rather than the volume, consequently, through the change that carries out the technology step order, carry out well region injection back to the fin portion, the first back etching part thickness isolation structure to play the effect that reduces isolation structure's volume, in order to reduce or eliminate the exposure the fin portion receives the influence of isolation structure internal stress, then when carrying out the annealing process after well region injection to the fin portion again, the probability that forms the dislocation defect in the fin portion also can reduce.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (15)
1. A method of forming a semiconductor structure, comprising:
providing a base, wherein the base comprises a substrate and a discrete fin part positioned on the substrate;
forming an isolation structure on the substrate exposed out of the fin portion, wherein the isolation structure covers the side wall of the fin portion;
after the isolation structure is formed, well region injection is carried out on the fin part;
after the well region is injected, the isolation structure with partial thickness is etched back, and partial side walls of the fin portion are exposed;
and after the isolation structure with partial thickness is etched back, carrying out annealing process after well region injection on the fin part.
2. The method of claim 1, wherein the well region implant has predetermined conditions including one or both of heating the substrate during the implant and a low ion beam current, the low ion beam current being less than or equal to 200 μ Α.
3. The method of claim 1, wherein after etching back a portion of the thickness of the isolation structure and before performing an annealing process after the well implant, the method further comprises: and forming a protective layer on the side wall and the top of the fin part exposed by the residual isolation structure by using a deposition process.
4. The method of forming a semiconductor structure of claim 1, wherein after etching back a portion of the thickness of the isolation structure and before performing an annealing process after the well implant, the method further comprises: and performing surface passivation treatment on the fin parts exposed by the residual isolation structures by using passivation gas, and forming protective layers on the side walls and the tops of the fin parts exposed by the residual isolation structures.
5. The method of claim 1, wherein the annealing process after the well implant comprises one or more of an isothermal annealing process, a spike annealing process, a millisecond annealing process, and a rapid thermal annealing process.
6. The method of forming a semiconductor structure of claim 1,the parameters of the annealing process after the well region injection comprise: the reaction gas includes: n is a radical of 2 、H 2 、NH 3 、O 2 And Ar; the process temperature is 500 ℃ to 1400 ℃; the process time is 0.1us to 60s; the chamber pressure is between 0.001torr and 780torr.
7. The method of forming a semiconductor structure of claim 3, wherein the deposition process to form the protective layer comprises an atomic layer deposition process.
8. The method of forming a semiconductor structure of claim 4, wherein the passivation gas is an oxygen-containing gas.
9. The method of forming a semiconductor structure of claim 4 or 8, wherein the passivating gas comprises O 2 、N 2 O and H 2 One or more of O.
10. The method of claim 4, wherein the step of performing the surface passivation on the exposed fin portions of the remaining isolation structures is performed at a temperature of 600 ℃ to 1200 ℃.
11. The method as claimed in claim 4, wherein the step of performing the surface passivation on the fin portion exposed by the remaining isolation structure uses a passivation gas in an amount greater than 10ppm.
12. The method of claim 2, wherein the substrate is heated at a temperature of 50 ℃ to 500 ℃.
13. The method according to claim 2, wherein the low ion beam current has a current value of 20 μ a to 200 μ a.
14. The method of claim 1, wherein the process of forming the isolation structure comprises fluid chemical vapor deposition.
15. The method of claim 1, wherein the process of etching back a portion of the thickness of the isolation structure comprises a dry etch process.
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| CN103426882A (en) * | 2012-05-16 | 2013-12-04 | 台湾积体电路制造股份有限公司 | CMOS device and method for forming the same |
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| US20160064377A1 (en) * | 2014-08-29 | 2016-03-03 | Taiwan Semiconductor Manufacturing Co., Ltd | Fin field effect transistor (finfet) device with protection layer |
| CN114446787A (en) * | 2020-10-30 | 2022-05-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and method of forming the same |
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| CN103426882A (en) * | 2012-05-16 | 2013-12-04 | 台湾积体电路制造股份有限公司 | CMOS device and method for forming the same |
| CN104752214A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Fin type field-effect transistor forming method |
| US20160064377A1 (en) * | 2014-08-29 | 2016-03-03 | Taiwan Semiconductor Manufacturing Co., Ltd | Fin field effect transistor (finfet) device with protection layer |
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