CN115130409B - FPGA timing model verification method and system - Google Patents
FPGA timing model verification method and system Download PDFInfo
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Abstract
The invention provides an FPGA time sequence model verification method, which comprises the steps of carrying out time sequence analysis on a time sequence model to generate a time sequence diagram, checking the time sequence diagram, correcting the time sequence model according to the checking result until the checking result of the time sequence diagram is correct, and more accurately and comprehensively reflecting the time sequence model, wherein any time sequence model variation is reflected on the time sequence diagram variation, so that the time sequence diagram is used as the calibration of the time sequence model, the accuracy can be ensured, the error introduction of the time sequence model is avoided, the time sequence arcs in the corrected time sequence model are matched with the time sequence arcs in a time sequence library, the time sequence model is corrected until the time sequence arcs in the time sequence model are all matched with the time sequence arcs in the time sequence library, the proportion of the number of the time sequence arcs in the corrected time sequence model to the number of the time sequence arcs in the time sequence library is calculated as coverage rate, the corrected time sequence model is corrected until the coverage rate is 100%, and the error introduction of the time sequence model is further ensured to be avoided through the coverage rate. The invention also discloses an FPGA time sequence model verification system.
Description
Technical Field
The invention relates to the technical field of FPGA (field programmable gate array), in particular to a verification method and a verification system for an FPGA time sequence model.
Background
Static timing analysis is an important analysis method for performance evaluation of field programmable gate array (Field Programmable GATE ARRAY, FPGA) chips. Along with the increasing functions of the FPGA chip, the chip integrates more and more functional modules, each functional module can work in a plurality of functional modes, the time sequence information of the chip can be influenced by the characteristics of the FPGA chip, and higher requirements are also put forward for static time sequence analysis.
In the existing FPGA chip computer aided design software technology, time sequence information consists of a time sequence model and a time sequence library. The time sequence model is generated by chip design software in hierarchical design, is abstract, and how to convert the abstract time sequence model into readable test calibration is the primary problem solved by a test system. The time sequence library is a file describing the time sequence information of the chip, and records all the time sequence information of the chip in the form of time sequence arcs. The timing sequence library is usually provided by a hardware design engineer, and is repeatedly checked by a software and hardware engineer to ensure the accuracy of information in the timing sequence library. The FPGA timing model is typically provided by a hardware designer separately by module, associating FPGA software with a timing library. The software and hardware engineers will inevitably introduce errors into the timing model in understanding the deviation of the hardware design.
Therefore, it is necessary to provide a new method and system for verifying FPGA timing model to solve the above-mentioned problems in the prior art.
Disclosure of Invention
The invention aims to provide a verification method and a verification system for an FPGA time sequence model, which can reduce the introduction error of the time sequence model.
In order to achieve the above object, the method for verifying the FPGA timing model of the present invention includes:
Performing timing analysis on the timing model to generate a timing diagram;
Checking the time sequence diagram, and correcting the time sequence model according to the checking result until the checking result of the time sequence diagram is correct;
Marking the corrected time sequence arcs in the time sequence model, matching the corrected time sequence arcs in the time sequence model with the time sequence arcs in the time sequence library, and if the corrected time sequence arcs in the time sequence model are not matched with the time sequence arcs in the time sequence library, correcting the time sequence model according to the matching result until all the corrected time sequence arcs in the time sequence model are matched with the time sequence arcs in the time sequence library;
And calculating the proportion of the number of the time sequence arcs in the corrected time sequence model to the number of the time sequence arcs in the time sequence library as coverage rate, and correcting the time sequence model according to the uncovered time sequence arcs in the time sequence library until the coverage rate is 100% if the coverage rate is smaller than 100%.
The FPGA timing model verification method has the advantages that timing analysis is conducted on a timing model to generate a timing diagram, the timing diagram is checked, the timing model is corrected according to the checking result until the checking result of the timing diagram is correct, the timing diagram can more accurately and comprehensively represent the timing model, any variation of the timing model is represented on the variation of the timing diagram, therefore, the timing diagram is used as calibration of the timing model, accuracy can be guaranteed, error introduction of the timing model is avoided, the timing arcs in the timing model after correction are marked, the timing arcs in the timing model after correction are matched with the timing arcs in a timing base, if the timing arcs in the timing model after correction are not matched with the timing arcs in the timing base, the timing model is corrected according to the matching result until all the timing arcs in the timing model after correction are matched with the timing arcs in the timing base, the proportion of the number of the timing arcs in the timing base after correction is calculated, if the coverage rate is smaller than 100%, and the error introduction of the timing model into the timing base can be avoided.
Optionally, the performing a timing analysis on the timing model to generate a timing diagram includes:
Obtaining a circuit netlist of the time sequence model;
marking a timing node in the circuit netlist;
And generating the time sequence diagram according to the interconnection relation of the time sequence nodes and the time sequence arc.
Optionally, before the performing the timing analysis on the timing model to generate the timing diagram, the method includes:
And carrying out time sequence analysis on the time sequence model according to the working mode so as to generate a time sequence diagram.
Optionally, before the performing the timing analysis on the timing model to generate the timing diagram, the method includes:
and carrying out time sequence analysis on the time sequence model according to the full connection mode so as to generate a time sequence diagram.
Optionally, the calculating, as the coverage rate, a ratio of the number of timing arcs in the timing model after correction to the number of timing arcs in the timing library includes:
Counting the number of timing arcs in the timing sequence library as a complete set;
marking time sequence arcs existing in the time sequence model, and then counting the number of the time sequence arcs existing in the time sequence model as a collection;
And solving the proportion of the whole set and the integrated set to obtain the coverage rate.
Optionally, the FPGA timing model verification method further includes a timing model acquisition step, where the timing model acquisition step includes:
The timing model is read from a fixed database.
Optionally, the FPGA timing model verification method further includes a fixed database generation step, and the fixed database generation step includes:
And saving the data of any finishing stage in the circuit implementation flow as a fixed database.
Optionally, the storing the data at any stage of completion in the circuit implementation flow as a fixed database includes:
and the data after the winding is completed in the realization flow of the storage circuit is used as a fixed database.
Optionally, before executing the time sequence analysis on the time sequence model to generate a time sequence diagram, the method further includes a module dividing step, where the module dividing step includes:
the circuit to be tested is divided into different functional modules according to the functions, and the different functional modules are respectively subjected to time sequence test.
The invention also discloses an FPGA time sequence model verification system which is used for realizing the FPGA time sequence model verification method, the time sequence test system comprises a test module and a test evaluation module, the test module is used for carrying out time sequence analysis on the time sequence model to generate a time sequence diagram, then checking the time sequence diagram and correcting the time sequence model according to the checking result until the checking result of the time sequence diagram is correct, the test evaluation module is used for marking the corrected time sequence arcs in the time sequence model and matching the corrected time sequence arcs with the time sequence arcs in a time sequence library, if the corrected time sequence arcs in the time sequence model are not matched with the time sequence arcs in the time sequence library, the time sequence model is corrected according to the matching result until all the corrected time sequence arcs in the time sequence model are matched with the time sequence arcs in the time sequence library, and the proportion of the number of the time sequence arcs in the time sequence model after correction to the number of the time sequence arcs in the time sequence library is calculated to be used as the coverage rate, if the coverage rate is less than 100%, and the coverage rate is corrected according to the uncovered time sequence arcs in the time sequence library to be 100%.
Drawings
FIG. 1 is a flow chart of the FPGA timing model verification method of the present invention;
FIG. 2 is a schematic diagram of a circuit netlist in accordance with some embodiments of the invention;
FIG. 3 is a schematic diagram of a circuit netlist after marking of timing nodes in some embodiments of the invention;
FIG. 4 is a schematic diagram of a timing diagram according to some embodiments of the invention;
FIG. 5 is a schematic diagram of a circuit netlist illustrating a first mode of operation according to some embodiments of the invention;
FIG. 6 is a schematic diagram of a circuit netlist in a second mode of operation according to some embodiments of the invention;
FIG. 7 is a schematic diagram of a circuit netlist with full connectivity in some embodiments of the invention;
FIG. 8 is a block diagram of the mode of operation of a module in some embodiments of the invention;
FIG. 9 is a schematic diagram of a fully connected circuit netlist in accordance with still other embodiments of the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. Unless otherwise defined, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and the like means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof without precluding other elements or items.
Aiming at the problems existing in the prior art, the embodiment of the invention provides an FPGA time sequence model verification method. Referring to fig. 1, the FPGA timing model verification method includes the steps of:
s1, carrying out time sequence analysis on a time sequence model to generate a time sequence diagram;
S2, checking the time sequence diagram, and correcting the time sequence model according to the checking result until the checking result of the time sequence diagram is correct;
S3, marking the corrected time sequence arcs in the time sequence model, matching the corrected time sequence arcs in the time sequence model with the time sequence arcs in the time sequence library, and if the corrected time sequence arcs in the time sequence model are not matched with the time sequence arcs in the time sequence library, correcting the time sequence model according to the matching result until all the corrected time sequence arcs in the time sequence model are matched with the time sequence arcs in the time sequence library;
And S4, calculating the proportion of the number of the time sequence arcs in the corrected time sequence model to the number of the time sequence arcs in the time sequence library as coverage rate, and correcting the time sequence model according to the uncovered time sequence arcs in the time sequence library until the coverage rate is 100% if the coverage rate is smaller than 100%. When the time sequence arcs in the time sequence model are matched with a plurality of time sequence arcs in the time sequence library, judging that the time sequence arcs in the time sequence model are not matched with the time sequence arcs in the time sequence library, wherein the time sequence arcs which are not covered in the time sequence library, namely the time sequence arcs existing in the time sequence library, are not appeared in the time sequence model.
In some embodiments, the timing model in the step S3 is a timing model of a correct timing diagram obtained after the step S2 is executed, if the corrected timing arcs in the timing model are not matched with the timing arcs in the timing library, then the unmatched timing arcs are output, the corresponding parts of the timing model are corrected, then the step S1 to the step S3 are re-executed, and when the step S4 is executed, if the coverage rate is less than 100%, the timing arcs which are not present in the timing library, namely the timing arcs which are not covered by the timing library, are output, the corresponding parts of the timing model are corrected, and then the step S1 to the step S4 are re-executed.
In some embodiments, the timing diagram may be checked manually or may be compared to a timing diagram generated from data in a timing library to effect the check.
In some embodiments, the performing a timing analysis on the timing model to generate a timing diagram includes:
Obtaining a circuit netlist of the time sequence model;
marking a timing node in the circuit netlist;
And generating the time sequence diagram according to the interconnection relation of the time sequence nodes and the time sequence arc.
In some embodiments, the timing diagram is generated according to the interconnection relation of the timing nodes and the timing arc when static analysis is performed, and contains a large amount of timing information, so that the structure and the timing model of the circuit netlist can be accurately reflected.
FIG. 2 is a schematic diagram of a circuit netlist in some embodiments of the invention. Referring to fig. 2, the top-level port in1, the data port dia, the top-level port clk1, the clock port clka, the top-level port out1, and the data output port qa are included.
FIG. 3 is a schematic diagram of a circuit netlist after marking timing nodes according to some embodiments of the present invention. Referring to fig. 3, top level port in1 is labeled as a timing node ①, data port dia is labeled as a timing node ②, top level port clk1 is labeled as a timing node ③, clock port clka is labeled as a timing node ④, data output port aq is labeled as a timing node ⑤, and top level port out1 is labeled as a timing node ⑥.
Fig. 4 is a schematic diagram of a timing diagram according to some embodiments of the invention. Referring to fig. 4, timing node ① and timing node ② are one timing path, and timing node ③, timing node ④, timing node ⑤, and timing node ⑥ are one timing path.
In some embodiments, before the timing model performs timing analysis to generate the timing diagram, the timing analysis is performed on the timing model according to the working mode to generate the timing diagram.
FIG. 5 is a schematic diagram of a circuit netlist according to a first mode of operation of some embodiments of the invention. Referring to fig. 5, ports dia, qa are related to port clka, and ports dib, qb are related to port clkb.
FIG. 6 is a schematic diagram of a circuit netlist according to a second mode of operation of some embodiments of the invention. Referring to fig. 6, port dia, port dib, and port clka are related, and port qa, port qb, and port clkb are related.
In some embodiments, before the timing model performs timing analysis to generate the timing diagram, the timing analysis is performed on the timing model according to a full connection mode to generate the timing diagram.
FIG. 7 is a schematic diagram of a fully connected circuit netlist according to some embodiments of the invention. When a certain time sequence arc exists objectively in the module, but the function deficiency is not yet opened, and a time sequence diagram is generated when the time sequence model is subjected to time sequence analysis according to the working mode, the subsequent coverage rate cannot reach 100%, and at the moment, the time sequence arc which is not yet opened can be tested by using a full connection mode. Referring to fig. 7, the module has a port dia connected to the top module port in1, a port clka connected to the top module port clk1, and a port qa connected to the top module port out1.
Fig. 8 is a block diagram of modes of operation of modules in some embodiments of the invention. Referring to fig. 8, a module HRIO includes a BYPASS operation mode, an SDR operation mode, a DDRX1 operation mode, a DDRX1_pipe operation mode, a DDRX2 operation mode, and a DDRX2L operation mode, and performs timing analysis on the timing model according to the BYPASS operation mode, the SDR operation mode, the DDRX1 operation mode, the DDRX1_pipe operation mode, the DDRX2 operation mode, and the DDRX2L operation mode, respectively, to generate six timing diagrams.
FIG. 9 is a schematic diagram of a fully connected circuit netlist in accordance with still other embodiments of the invention. Referring to fig. 9, the number of ports HRIO is 13, and 13 ports are respectively port ce, port ts, port ipad, port doq, port rst, port ipclk, port opclk, port isclk, port osclk, port opad, port bpad, port dip and port di, port ce is connected to upper port in1, port ts is connected to upper port in2, port ipad is connected to upper port in3, port doq is connected to upper port in4, port rst is connected to upper port in5, port ipclk is connected to upper port clk1, port opclk is connected to upper port clk2, port isclk is connected to upper port clk3, port osclk is connected to upper port clk4, port opad is connected to upper port out1, port bpad is connected to upper port out2, port dip is connected to upper port out3, and port di is connected to upper port out4.
In some embodiments, the time sequence model is subjected to time sequence analysis according to the working modes to generate a time sequence diagram, or the time sequence model is subjected to time sequence analysis according to the full connection mode to generate the time sequence diagram, so that accuracy of the time sequence model of the module in each working mode can be guaranteed in two modes, and coverage rate can be effectively improved by combining the full connection mode.
In some embodiments, the calculating the ratio of the number of timing arcs in the corrected timing model to the number of timing arcs in the timing library as the coverage includes:
Counting the number of timing arcs in the timing sequence library as a complete set;
marking time sequence arcs existing in the time sequence model, and then counting the number of the time sequence arcs existing in the time sequence model as a collection;
and solving the proportion of the whole set and the integrated set to obtain the coverage rate. The time sequence arcs in the time sequence library are all ensured to appear in the time sequence model.
In some embodiments, the FPGA timing model verification method further comprises a timing model acquisition step, wherein the timing model acquisition step comprises reading the timing model from a fixed database.
In some embodiments, the FPGA time sequence model verification method further comprises a fixed database generation step, wherein the fixed database generation step comprises the step of saving data of any finishing stage in a circuit implementation flow as a fixed database. Preferably, the data after the winding is completed in the circuit implementation process is saved as a fixed database.
In some embodiments, before the time sequence analysis is performed on the time sequence model to generate the time sequence diagram, the method further comprises a module dividing step, wherein the module dividing step comprises dividing the circuit to be tested into different functional modules according to functions, and respectively performing time sequence test on the different functional modules. The FPGA chip comprises a plurality of functional modules, the time sequence models of the functional modules in different working modes are different, and the modules and the working modes are diversified to cause difficulty for the coverage test of the time sequence models. After the modules are divided, testing is carried out according to the modules, so that engineers can conveniently track the testing progress, and the aim of fully covering each module time sequence model is fulfilled. In addition, the method for testing by the sub-modules is also beneficial to the problem of rapid positioning of the time sequence model in the regression testing process. When in regression test, a regression problem generated by a certain module often affects the test of the certain module, and the time sequence information of other modules is kept unchanged, so that engineers can quickly estimate the position of the problem through the change of the tested module, thereby shortening the time sequence repair period of the module.
The invention also discloses an FPGA time sequence model verification system which is used for realizing the FPGA time sequence model verification method, the time sequence test system comprises a test module and a test evaluation module, the test module is used for carrying out time sequence analysis on the time sequence model to generate a time sequence diagram, then checking the time sequence diagram and correcting the time sequence model according to the checking result until the checking result of the time sequence diagram is correct, the test evaluation module is used for marking the corrected time sequence arcs in the time sequence model and matching the corrected time sequence arcs with the time sequence arcs in a time sequence library, if the corrected time sequence arcs in the time sequence model are not matched with the time sequence arcs in the time sequence library, the time sequence model is corrected according to the matching result until all the corrected time sequence arcs in the time sequence model are matched with the time sequence arcs in the time sequence library, and the proportion of the number of the time sequence arcs in the time sequence model after correction to the number of the time sequence arcs in the time sequence library is calculated to be used as the coverage rate, if the coverage rate is less than 100%, and the coverage rate is corrected according to the uncovered time sequence arcs in the time sequence library to be 100%.
While embodiments of the present invention have been described in detail hereinabove, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. It is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
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