CN114021514B - Method for simulating and screening bottleneck units through SPICE voltage or temperature scanning - Google Patents
Method for simulating and screening bottleneck units through SPICE voltage or temperature scanning Download PDFInfo
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Abstract
A method for simulating and screening bottleneck units by SPICE voltage or temperature scanning comprises the following steps: 1) Screening a timing path data subset of the STA timing violation from the original timing path data set; 2) SPICE simulation is carried out on each path of the time sequence path data subset, and a key path set is screened out; 3) The elements of the critical path set are arranged in a descending order; 4) Acquiring a time sequence analysis object set from a key path set in which elements are arranged in a descending order; 5) Acquiring an instance unit set from the time sequence analysis object set; 6) Acquiring INSTANCE CELLS trend characteristic comprehensive indexes; 7) And constructing a time sequence unit set sensitive to time sequence according to the trend characteristic comprehensive index. The method combines STA and SPICE simulation, screens out more sensitive time sequence units along with the actual voltage or temperature working condition change in the critical path, and effectively shortens the ASIC design period.
Description
Technical Field
The invention relates to the technical field of EDA simulation tools, in particular to a method for screening bottleneck units by SPICE voltage or temperature scanning simulation.
Background
Timing analysis is a key problem in ASIC design flow, in the prior art, a traditional and simple way is to perform timing inspection (slot, delay, etc.) on a timing path or a timing unit based on STA table look-up calculation, and complete timing acceptance without performing circuit function verification; in another way, SPICE Voltage or Temperature (V/T) scan simulation can be used to further study the trend and sensitivity of circuit timing variation with V/T variation, and study the actual operation performance of the whole IC design circuit.
The timing cell libraries required by STA are usually built based on fixed Process and fixed voltage and temperature conditions (Process, voltage and Temperature, PVT), which has the advantage that the timing analysis can be done quickly without external stimulus and the coverage of the timing path analysis can reach almost 100%, but the disadvantage that the time and capital costs required for building these cell libraries are huge, which is difficult to keep up with the requirements of new Process development for IC design. Therefore, with the continuous progress of the IC process, compared with STA, the SPICE simulation-based time sequence analysis method can finish high-precision solution of the time sequence parameters of the gate level or the transistor level and effective estimation of the time sequence parameters of the critical path, and device time sequence data which is more suitable for the actual situation and changes along with the V/T condition can be obtained through SPICE simulation by modifying the parameters in the SPICE simulation netlist file for multiple times, but the SPICE dynamic time sequence simulation has the defects of long time consumption and high resource consumption.
Disclosure of Invention
In order to solve the defects existing in the prior art, the invention aims to provide a method for screening bottleneck units by SPICE voltage or temperature scanning simulation, which is characterized by full coverage and high speed by firstly setting key parameter slot threshold values to select key paths, then carrying out SPICE V/T scanning simulation on the key paths to obtain changed circuit time sequence data, and screening more sensitive time sequence units by establishing a mapping relation between the paths and units and analyzing trend and sensitivity of each time sequence change, and feeding back the more sensitive time sequence units to work such as time sequence report or time sequence repair, thereby shortening ASIC design period and enabling the design to be more in line with actual working conditions.
In order to achieve the above purpose, the method for simulating and screening bottleneck units by SPICE voltage or temperature scanning provided by the invention comprises the following steps:
1) Screening a timing path data subset of the STA timing violation from the original timing path data set;
2) SPICE simulation is carried out on each path of the time sequence path data subset, and a key path set is screened out;
3) The elements of the critical path set are arranged in a descending order;
4) Acquiring a time sequence analysis object set from a key path set in which elements are arranged in a descending order;
5) Acquiring an instance unit set from the time sequence analysis object set;
6) Acquiring INSTANCE CELLS trend characteristic comprehensive indexes;
7) And constructing a time sequence unit set sensitive to time sequence according to the trend characteristic comprehensive index.
Further, the subset of timing path data, each element of which satisfies the following condition:
wherein, the slot is a timing margin calculated by Setup or Hold timing check, The method is used for indicating the slot value calculated by the STA method of the critical path, and T slack is used for indicating the slot empirical value of the STA timing analysis critical parameter.
Further, the step 2) further comprises,
SPICE simulation is carried out on each path element in the time sequence path subset to obtain a slot time sequence simulation value thereof;
screening out a subset of the time sequence path subsets as a critical path set according to a time sequence violation judgment standard;
each element in the critical path set satisfies the following condition:
Wherein, And (3) representing a slot value calculated by SPICE simulation timing results, wherein slot is a timing margin calculated by Setup or Hold timing inspection.
Further, the step 3) further comprises,
SPICE V/T simulation is carried out on all the critical paths in the critical path set, and more than 5 scanning points are set to obtain data with obvious trend change;
Organizing time sequence data of each time sequence path, and calculating trend sensitivity factors;
the elements in the set of critical paths are arranged in descending order based on the absolute value of the trend sensitivity factor.
Further, the step 4) further comprises,
Selecting a non-common path from a key path set in which elements are arranged in a descending order, wherein a unit point set of non-defect points is used as a time sequence analysis object set;
The non-common path is a non-common part of a transmit clock path and a capture clock path;
the non-defect point is not participated in SPICE simulation, and STA time sequence values are obtained directly.
Further, the step 5) further comprises,
Establishing a forward mapping relation between the critical path set and the library reference unit set;
traversing all instance unit sets to find all referenced library reference unit sets;
Establishing a reverse mapping relation between a library reference unit set and a critical path set;
Traversing the sequence analysis object set, and finding all instance unit sets of each reference unit in the sequence analysis object set as instance unit sets.
Further, the step 6) further comprises,
Organizing time sequence trend data of input conversion and unit delay of each unit point in an example unit set, and respectively calculating trend sensitivity factors of the time sequence trend data;
Statistical calculation to obtain And
Wherein,An arithmetic average representing the transition time variation trend sensitivity factors of all the cells after instantiation of the library timing unit; An arithmetic average of delay time variation trend sensitivity factors representing all units after instantiation of the library timing unit;
Taking out AndIs used as the trend characteristic comprehensive index of the example unit set.
Still further, the step 7) further includes,
Arranging all the calculated trend characteristic comprehensive indexes according to a descending order, and taking N corresponding time sequence units before arrangement to construct a time sequence sensitive time sequence unit set;
checking coverage rate of critical paths of the time sequence unit set in reverse mapping relation between the library reference unit set and the critical path set;
iterating by increasing the previous N values, stopping when the path coverage rate detection reaches 100%, and determining the final previous N value;
taking the time sequence unit set determined after the iteration is stopped as a key time sequence unit concerned in time sequence report and time sequence repair;
wherein N is a positive integer greater than 1.
To achieve the above object, the present invention further provides an electronic device including a memory and a processor, wherein the memory stores a computer program running on the processor, and the processor executes the steps of the SPICE voltage or temperature scanning simulation bottleneck unit screening method as described above when running the computer program.
To achieve the above object, the present invention also provides a computer readable storage medium having stored thereon a computer program which, when run, performs the steps of the SPICE voltage or temperature scanning simulation bottleneck unit screening method as described above.
The SPICE voltage or temperature scanning simulation bottleneck unit screening method, the electronic equipment and the computer readable storage medium have the following beneficial effects:
1) When the critical path set is screened, the respective advantages of STA and SPICE simulation are combined, in general, margin reserved by the value can be designed based on ASIC design experience, or descending order is carried out through the STA value, and STA+SPICE cross verification is adopted sequentially according to the arrangement order, so that the sequential simulation calculation can be stopped after positive values (i.e. paths without timing violations) appear continuously, and further, an effective critical path screening threshold value is determined under the condition without any experience;
2) When the trend sensitivity factor is calculated based on the circuit time sequence change data, the data increment is adopted for calculation, so that the difference between different types of time sequence parameters can be eliminated, the calculated factor result has comparability, and the secondary calculation can be performed. The absolute value of the sensitivity factor obtained by the calculation mode represents the concave-convex degree of trend change, the positive and negative signs represent the increasing and decreasing directions of trend change, and the sensitivity factor has the characteristic of standardization and unification, but the number of V/T scanning points required by calculation is generally not less than 5, otherwise, the trend characteristic representation capability is greatly weakened;
3) When the time sequence characteristic index of the time sequence unit is calculated, some actual conditions existing in the ASIC design are fully considered, redundant time sequence objects such as Common Path and DEFECTIVE PIN are eliminated, and the data volume is effectively reduced; taking multiplexing conditions from the time sequence unit to the design circuit instance unit into consideration, the time sequence unit object is organized and calculated rapidly and effectively by establishing a reverse mapping relation between the time sequence unit and the time sequence path; when the bottleneck time sequence units are screened, the standard unified time sequence trend characteristic comprehensive index can be obtained through reasonable assumption and calculation such as simple averaging, ratio solving and the like, and the method is also suitable for ASIC design with increased time sequence units.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, and do not limit the invention. In the drawings:
FIG. 1 is a flow chart of a method for SPICE voltage or temperature sweep simulation screening of bottleneck cells in accordance with the present invention;
FIG. 2 is a flow chart of a STA collaborative SPICE screening critical paths according to the present invention;
FIG. 3 is a schematic diagram of a time series object data organization according to the present invention;
FIG. 4 is a flow chart of a bottleneck timing unit for V/T scan timing trend data filtering according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present invention only, and are not intended to limit the present invention.
In the embodiment of the invention, by combining STA and SPICE simulation, a time sequence unit which is more sensitive along with the change of the actual voltage or temperature working condition in a critical path is realized, and the time sequence unit is also an object which needs to be focused during time sequence report and time sequence repair. The advantages of high STA time sequence analysis speed, high coverage rate, high SPICE simulation solving circuit time sequence precision and the like are fully utilized, and the ASIC design period is effectively shortened by assisting the working flows of time sequence report, time sequence repair and the like through the characteristic calculation and analysis of time sequence trend.
Example 1
FIG. 1 is a flowchart of a method for SPICE voltage or temperature scan simulation screening of bottleneck cells according to the present invention, and a detailed description of the method for SPICE voltage or temperature scan simulation screening of bottleneck cells according to the present invention will be given with reference to FIG. 1.
First, in step 101, a timing path dataset of STA timing violations is screened from the original timing path dataset using STA.
In the embodiment of the invention, a subset Q is preliminarily screened in an original time sequence path data set U by utilizing the advantages of high calculation speed and high path coverage rate of the STA, so that each element path (i) in the Q meets the following conditions:
wherein, the slot is a timing margin calculated by Setup or Hold timing check, The method comprises the steps that a slot value obtained by calculating a key path by adopting an STA method is represented, T slack represents an empirical value of a key parameter slot of STA timing analysis, and the default value of the empirical value is 0, so that a timing path dataset of STA timing violations is obtained; when T slack takes a positive number and maintains a certain boundary (Margin), then a portion of the timing path data subset Q of the STA slot that is more optimistic (actually there may be timing violations) is screened out.
At step 102, SPICE simulation is performed on each path of the sequence path data subset Q, and a critical path set is screened out.
In the embodiment of the invention, SPICE simulation is performed on each path (i) in the time sequence path subset Q to obtain a slot time sequence simulation value thereof, and similar to the process in the step 101, a subset Q 'of Q is screened out as a critical path set (CRITICAL PATHS) according to a time sequence violation judgment standard slot <0, so that each element path (j) in Q' meets the following conditions:
Wherein, Representing the calculated slot values from SPICE simulation timing results.
Fig. 2 is a flow chart of a STA collaborative SPICE screening critical path according to the present invention, as shown in fig. 2, a reasonable slot threshold T (T > 0) is set, and then the threshold is confirmed through simulation iteration until a slot is no longer present and is negative. Although the STA has the characteristics of high path coverage rate and high speed, with the progress of the process and the change of the working environment, the STA result may deviate, some errors are reported, and the STA result with OCV and POCV is sometimes too pessimistic, so that the time can be effectively shortened by adopting the mode of cross-validation of the STA and SPICE structures, and an accurate critical path set Q' with timing violations can be screened out.
In step 103, elements of the critical path set are arranged in descending order.
In the embodiment of the invention, SPICE V/T simulation is performed on all CRITICAL PATH (critical paths) in a critical path set Q '(at this time, more than 5 scanning points are set to obtain data with obvious trend change), time sequence data (slot or Arrival) of each time sequence path are organized, trend sensitivity factors are calculated (differences among data amounts are eliminated in a data increment mode, effective trend sensitivity factors are obtained under a unified calculation standard), and elements in Q' are arranged in descending order based on absolute values of the factors, namely, the time sequence trend change degree is more remarkable when the time sequence paths are located ahead.
In step 104, a unit point that is not a normal path and is not a defective point is selected from the critical path set in which elements are arranged in descending order as a time series analysis object set.
In the embodiment of the present invention, since the time sequence (delay/Data/Capture) of each segment of the time sequence Path is the time sequence accumulated result of each time sequence Point (Cell/Net Point) inside the time sequence Path, wherein the time sequence contribution of the Cell Point (unit Point) is more remarkable than that of the Net Point (Net Point), non-Common paths (non-Common portions of the transmit clock Path Launch Clock Path and the Capture clock Path Capture Clock Path) are further selected, and the non-Common paths are not defect Points DEFECTIVE PIN (actually expressed as Cell Points (unit Point sets) which do not participate in SPICE simulation and directly take STA time sequence values) as the time sequence analysis object set C j (where j is the id identifier of each element in the critical Path set Q').
At step 105, all instantiated INSTANCE CELLS sets for each REFERENCE CELL in the set of time series analysis objects are obtained.
In the embodiment of the present invention, because the sequential units (REFERENCE CELL, master) in the sequential library have multiplexing in the actual ASIC design, that is, may be instantiated (INSTANCE CELL) multiple times in one or more sequential paths, first, a Forward Mapping relationship (Forward Mapping) between the critical path set CRITICAL PATHS and the library sequential unit set REFERENCE CELLS is established, and all the library sequential unit sets (REFERENCE CELLS) referenced are found by traversing all the example unit sets C j; then, a reverse Mapping relationship (Backward Mapping) between REFERENCE CELLS and CRITICAL PATHS is established, and all instance unit (INSTANCE CELLS) sets of each REFERENCE CELL in all time sequence analysis object sets C j are traversed and found as instance unit sets C k (in the same manner, k is an id identifier of each time sequence unit in the time sequence library).
FIG. 3 is a schematic diagram of a timing object data organization according to the present invention, as shown in FIG. 3, in a specific ASIC design, the timing objects included in the ASIC design are reasonably organized and cleaned, so that the interference of redundant data can be effectively avoided, and in the critical path set (CRITICAL PATHS), common path timing points (Common Path Points) and timing points (DEFECTIVE PINS) with defects and non-simulation on internal timing path segments are not single, such as added abstract but not actually existing connection points, or timing units which cannot be analyzed by the SPICE simulator, etc., all have little calculation contribution to path delay, can be directly removed, and only example units (INSTANCE CELLS) participating in simulation and success on non-common paths are reserved. Through the data mapping relation between the time sequence unit set (Library REFERENCE CELLS) and the critical path set (CRITICAL PATHS), all the instantiated unit sets of each time sequence unit (REFERENCE CELL) in the time sequence violation paths can be traversed and found.
In step 106, a trend feature integrated index is obtained INSTANCE CELLS.
In the embodiment of the present invention, as a simplification, it is assumed that the cell delay (CELL DELAY) of an instance cell has no relation with the depth of its bit column in the timing path, but only has a strong correlation with the Input transition (Input Slew) and the Output Load (Output Load) of the instance cell. In a specific ASIC design, the Load (Output Load) of the instance cell does not change significantly during the V/T condition change, but the Input Slew changes significantly, resulting in CELL DELAY also changing significantly. So, the Input slot and CELL DELAY time sequence trend data of each Cell Point are organized in the example unit set C k, the trend sensitivity factors are calculated respectively, and the statistical calculation is performed to obtainAndThat is, the arithmetic average value of all factors is taken as a representative, as shown in formula 3, and the absolute value ratio r k (considering only the relative degree of trend change) of the two is taken as the trend characteristic comprehensive index of C k, as follows:
Wherein, An arithmetic average representing the transition time variation trend sensitivity factors of all the cells after instantiation of the library timing unit; An arithmetic average of delay time variation trend sensitivity factors of all cells after the instantiation of the library timing unit is represented.
In step 107, a time sequence unit set sensitive to time sequence is constructed according to the trend characteristic comprehensive index, and key time sequence units focused in time sequence report and time sequence repair are determined.
In the embodiment of the present invention, each cited REFERENCE CELL instantiated instance unit set C k in step 106 may calculate a corresponding trend feature comprehensive index r k (a plurality of effective numbers may be reserved appropriately to improve the characterizability of the data indexes), arrange all the calculated comprehensive indexes r k in descending order, construct a time-sequence-sensitive time sequence unit set by taking Top N corresponding time sequence units before arrangement, check the coverage rate of the critical path in the Backward Mapping data Mapping relation, iterate by increasing the value of Top N, stop when the path coverage rate detection reaches 100%, and determine the final Top N value. And taking the time sequence unit set determined after the iteration is stopped as the key time sequence unit concerned in the time sequence report and the time sequence repair, thereby shortening the ASIC design period.
FIG. 4 is a flow chart of a bottleneck timing unit for V/T scanning timing trend data screening according to the present invention, as shown in FIG. 4, the sensitivity factor is calculated by typical timing data such as Input Slew and CELL DELAY of the example unit (INSTANCE CELLS), and then the trend feature integrated index is calculated to represent the sensitivity of the corresponding Library timing unit (Library REFERENCE CELL) after the voltage or temperature operating condition is changed. And (3) sorting in a descending order through comprehensive indexes, iterating by taking the increasing Top N value, and taking the library time sequence unit of the current Top N arrangement as a bottleneck unit set with higher trend sensitivity as an object needing to be focused in the subsequent time sequence report and time sequence repair stage when the coverage rate of the key path reaches 100% (the coverage meaning that the time sequence unit at least appears once in one or more key paths).
The method for screening bottleneck units by SPICE voltage or temperature scanning simulation provided by the invention effectively screens time sequence objects (including paths, units and the like) based on the time sequence analysis requirements of specific ASIC design and the characteristics of STA and SPICE simulation time sequence analysis methods, eliminates redundant data and reduces data volume, so that initially screened instance units (INSTANCE CELLS) can cover all critical paths (CRITICAL PATHS), and meanwhile, the instance units also play a decisive role in time sequence calculation of the critical paths;
The method has the advantages that various data are reasonably and effectively organized, including a forward and reverse data mapping relation between CRITICAL PATHS and REFERENCE CELLS (INSTANCE CELLS) and a one-to-many unit instantiation relation between REFERENCE CELLS and INSTANCE CELLS, and a proper data structure is constructed in a specific engineering function module to characterize the relations, so that the workflow of iteratively screening bottleneck units sensitive to time sequence trends is facilitated.
By selecting a proper trend sensitivity factor calculation method, since the time series data after SPICE simulation is not single, as in Input Slew and CELL DELAY of the example unit adopted in the invention, when comparison or secondary calculation between multiple types of data is needed, the difference of the data itself needs to be eliminated first. The method adopts a calculation method based on data increment, and adopts a standard and unified calculation standard to obtain a sensitivity factor, wherein the absolute value of the factor represents the concave-convex degree of trend change, and the positive and negative signs of the factor represent the increasing and decreasing directions of the trend change;
The complete and convergent iterative mechanism for critical path coverage detection can be known from the data mapping relationships CRITICAL PATHS and REFERENCE CELLS, and REFERENCE CELLS can completely cover all CRITICAL PATHS. In the iterative process, when Top N increases, if the path coverage rate increases, it means that the current REFERENCE CELL is covered to the new CRITICAL PATH, and meanwhile, the trend sensitivity is highest in the subsequent time sequence unit sequence, so that it is directly used as the element of the main and key bottleneck unit set; otherwise, when the critical path coverage rate is kept unchanged at this time, the critical path coverage rate is taken as an element of a secondary and standby bottleneck unit set, and identification is added for distinguishing.
In one embodiment of the invention, there is also provided an electronic device including a memory and a processor having stored thereon a computer program running on the processor, the processor executing the steps of the SPICE voltage or temperature scan emulation screening bottleneck unit method as described above when running the computer program.
In one embodiment of the present invention, there is also provided a computer readable storage medium having stored thereon a computer program that, when run, performs the steps of the SPICE voltage or temperature scan simulation bottleneck unit screening method as described above.
Those of ordinary skill in the art will appreciate that: the foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A method for simulating and screening bottleneck units by SPICE voltage or temperature scanning comprises the following steps:
1) Screening a timing path data subset of the STA timing violation from the original timing path data set;
2) SPICE simulation is carried out on each path of the time sequence path data subset, and a key path set is screened out;
3) The elements of the critical path set are arranged in a descending order;
4) Acquiring a time sequence analysis object set from a key path set in which elements are arranged in a descending order;
5) Acquiring an instance unit set from the time sequence analysis object set;
6) Acquiring INSTANCE CELLS trend characteristic comprehensive indexes;
7) Constructing a time sequence unit set sensitive to time sequence according to the trend characteristic comprehensive index;
The step 3) further comprises the steps of,
SPICE V/T simulation is carried out on all the critical paths in the critical path set, and more than 5 scanning points are set to obtain data with obvious trend change;
Organizing time sequence data of each time sequence path, and calculating trend sensitivity factors;
Arranging elements in the critical path set in descending order based on the absolute value of the trend sensitivity factor;
the step 5) further comprises the steps of,
Establishing a forward mapping relation between the critical path set and the library reference unit set;
traversing all instance unit sets to find all referenced library reference unit sets;
Establishing a reverse mapping relation between a library reference unit set and a critical path set;
traversing the sequence analysis object set, and finding all instance unit sets of each reference unit in the sequence analysis object set to be used as instance unit sets;
The step 6) further comprises the steps of,
Organizing time sequence trend data of input conversion and unit delay of each unit point in an example unit set, and respectively calculating trend sensitivity factors of the time sequence trend data;
Statistical calculation to obtain And
Wherein,An arithmetic average representing the transition time variation trend sensitivity factors of all the cells after instantiation of the library timing unit; An arithmetic average of delay time variation trend sensitivity factors representing all units after instantiation of the library timing unit;
Taking out AndIs used as the trend characteristic comprehensive index of the example unit set.
2. The SPICE voltage or temperature scan simulation bottleneck unit screening method of claim 1, wherein each element of the subset of timing path data satisfies the following condition:
wherein, the slot is a timing margin calculated by Setup or Hold timing check, The method is used for indicating the slot value calculated by the STA method of the critical path, and T slack is used for indicating the slot empirical value of the STA timing analysis critical parameter.
3. The method for SPICE voltage or temperature scanning simulation screening bottleneck unit as set forth in claim 1, wherein the step 2) further comprises,
SPICE simulation is carried out on each path element in the time sequence path subset to obtain a slot time sequence simulation value thereof;
screening out a subset of the time sequence path subsets as a critical path set according to a time sequence violation judgment standard;
each element in the critical path set satisfies the following condition:
Wherein, And (3) representing a slot value calculated by SPICE simulation timing results, wherein slot is a timing margin calculated by Setup or Hold timing inspection.
4. The method for SPICE voltage or temperature scanning simulation screening bottleneck unit as set forth in claim 1, wherein the step 4) further comprises,
Selecting a non-common path from a key path set in which elements are arranged in a descending order, wherein a unit point set of non-defect points is used as a time sequence analysis object set;
The non-common path is a non-common part of a transmit clock path and a capture clock path;
the non-defect point is not participated in SPICE simulation, and STA time sequence values are obtained directly.
5. The method for SPICE voltage or temperature scanning simulation screening bottleneck unit as set forth in claim 1, wherein the step 7) further comprises,
Arranging all the calculated trend characteristic comprehensive indexes according to a descending order, and taking N corresponding time sequence units before arrangement to construct a time sequence sensitive time sequence unit set;
checking coverage rate of critical paths of the time sequence unit set in reverse mapping relation between the library reference unit set and the critical path set;
iterating by increasing the previous N values, stopping when the path coverage rate detection reaches 100%, and determining the final previous N value;
taking the time sequence unit set determined after the iteration is stopped as a key time sequence unit concerned in time sequence report and time sequence repair;
wherein N is a positive integer greater than 1.
6. An electronic device comprising a memory and a processor, the memory having stored thereon a computer program running on the processor, the processor executing the steps of the SPICE voltage or temperature scan simulation screening bottleneck unit method of any one of claims 1 to 5 when the computer program is run.
7. A computer readable storage medium having stored thereon a computer program, wherein the computer program when run performs the steps of the SPICE voltage or temperature scan simulation bottleneck unit screening method of any one of claims 1 to 5.
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