CN115118262B - Power-on reset circuit - Google Patents
Power-on reset circuit Download PDFInfo
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- CN115118262B CN115118262B CN202210856038.3A CN202210856038A CN115118262B CN 115118262 B CN115118262 B CN 115118262B CN 202210856038 A CN202210856038 A CN 202210856038A CN 115118262 B CN115118262 B CN 115118262B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
- H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
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Abstract
The application provides a power-on reset circuit, which relates to the field of integrated circuits and comprises a delay module, a signal generation module and a leakage protection module. The first end of the delay module, the first end of the signal generation module and the first end of the leakage protection module are electrically connected with a power supply; the second end of the delay module, the second end of the signal generation module and the second end of the leakage protection module are grounded; the third end of the delay module is electrically connected with the third end of the leakage protection module; the fourth end of the delay module is electrically connected with the third end of the signal generation module; the leakage protection module is conducted when the electric signal transmitted by the power supply changes from a high level to a low level, at the moment, the delay module discharges stored charges so as to charge the electric signal when the electric signal changes from the low level to the high level, and transmits the generated output electric signal to the signal generation module when the charging is completed; the signal generation module generates a power-on reset signal based on the output electric signal, and can normally operate when the electric signal provided by the power supply shakes.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a power-on reset circuit.
Background
In the field of integrated circuit design, various integrated circuits may include a Power On Reset (POR) circuit. POR circuits are typically used to send a reset signal to digital circuits in an integrated circuit to cause the digital circuits to reset to start and initialize to an initial state as desired by the designer.
Conventional power-on reset circuits typically employ an access low-pass filter circuit to achieve signal delay in order to eliminate unstable states at the beginning of power-on. And comparing the connected band gap reference (band gap) voltage with a resistor voltage division signal of the power supply voltage by using a comparator, and generating a reset signal when the resistor voltage division signal is larger than the band gap reference voltage.
However, when the electrical signal provided by the external power supply is subjected to large jitter, the POR circuit in the prior art has the problem of incapability of operating normally.
Disclosure of Invention
In order to solve the technical problems in the prior art, the power-on reset circuit capable of operating normally is provided when the electric signal provided by the external power supply shakes greatly.
The application provides a power-on reset circuit, comprising: the device comprises a delay module, a signal generation module and a leakage protection module; the first end of the delay module, the first end of the signal generation module and the first end of the leakage protection module are electrically connected with a power supply; the second end of the delay module, the second end of the signal generation module and the second end of the leakage protection module are grounded; the third end of the delay module is electrically connected with the third end of the leakage protection module; the fourth end of the delay module is electrically connected with the third end of the signal generation module;
the leakage protection module is used for being conducted when the electric signal transmitted by the power supply changes from a high level to a low level;
The delay module is used for discharging stored charges when the discharging protection module is conducted so as to charge when the electric signal changes from low level to high level, and transmitting the generated output electric signal to the signal generation module when the charging is completed; the signal generation module is used for generating a power-on reset signal based on the output electric signal.
In one embodiment, the leakage protection module comprises a leakage protection unit and a leakage switch; the first end of the leakage switch is electrically connected with a power supply, the second end of the leakage switch is grounded, the third end of the leakage switch is electrically connected with one end of the leakage protection unit, and the other end of the leakage protection unit is grounded;
The leakage protection unit is used for dividing the electric signal when the electric signal transmitted by the power supply changes from a high level to a low level;
The leakage switch is used for being conducted after the voltage of the electric signal is reduced to a preset voltage threshold value.
In one embodiment, a leakage switch includes: the first PMOS tube and the second PMOS tube; the source stage of the first PMOS tube is electrically connected with a power supply, and the drain electrode and the grid electrode of the first PMOS tube are electrically connected with the grid electrode of the second PMOS tube; the drain electrode of the second PMOS tube is grounded, and the source electrode of the second PMOS tube is electrically connected with the delay module.
In one embodiment, the leakage protection unit comprises a resistor; the drain electrode, the grid electrode and the first common end of the grid electrode electric connection of the first PMOS tube are electrically connected with one end of the resistor, and the other end of the resistor is grounded.
In one embodiment, the leakage protection unit further includes a first NMOS transistor; the grid electrode of the first NMOS tube is electrically connected with the first common end, and the source electrode and the drain electrode of the first NMOS tube are grounded;
and the first NMOS tube is used for absorbing burr signals of the electric signals.
In one embodiment, the delay module includes a delay unit and a current generation unit; the first end power supply of the current generating unit is electrically connected, the second end of the current generating unit is grounded, and the third end of the current generating unit is connected with one end of the delay unit; the other end of the delay unit is grounded;
The delay unit is used for discharging the stored charges when the leakage protection module is conducted;
the current generation unit is used for generating current for controlling the charging time length when the power supply is electrified and transmitting the current to the delay unit;
the delay unit is used for facilitating the charging of the current;
And the current generation unit is used for transmitting the output electric signal to the signal generation module when the delay unit is charged.
In one embodiment, the current generating unit includes a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor; the fourth PMOS tube is an inverted ratio tube; the source stage of the third PMOS tube and the source stage of the fifth PMOS tube are respectively and electrically connected with a power supply; the drain electrode of the third PMOS tube is electrically connected with the source electrode of the fourth PMOS tube, and the drain electrode of the fourth PMOS tube is grounded; the drain electrode of the third PMOS tube and the grid electrode of the fifth PMOS tube are respectively and electrically connected with the grid electrode of the third PMOS tube; one end of the delay unit, the third end of the signal generation module and the second common end of the third end of the leakage protection module are electrically connected with the drain electrode of the fifth PMOS tube.
In one embodiment, the delay unit includes a second NMOS transistor; the grid electrode of the second NMOS tube is electrically connected with the second common end; the source and drain of the second NMOS tube are grounded.
In one embodiment, the signal generation module includes a first inverter; the first end of the first inverter is electrically connected with a power supply, the second end of the first inverter is grounded, the third end of the first inverter is electrically connected with the fourth end of the delay module, and the fourth end of the first inverter is electrically connected with the digital circuit;
And the first inverter is used for stopping inverting the output electric signal to generate a power-on reset signal when the voltage of the output electric signal is smaller than a preset reverse voltage threshold value.
In one embodiment, a first inverter includes: a sixth PMOS tube and a third NMOS tube; the source stage of the sixth PMOS tube is electrically connected with a power supply, the drain electrode of the sixth PMOS tube is electrically connected with the drain electrode of the third NMOS tube, and the source stage of the third NMOS tube is grounded; the third common end of the sixth PMOS tube and the third NMOS tube are electrically connected with the fourth end of the delay module.
As can be seen from the above technical solution, the present application provides a power-on reset circuit, which includes: the device comprises a delay module, a signal generation module and a leakage protection module. The leakage protection module is conducted when the electric signal transmitted by the power supply changes from high level to low level. The delay module can discharge stored charges when the leakage protection module is conducted. When the electric signal transmitted by the power supply changes from low level to high level, the delay module can charge, and the generated output electric signal is transmitted to the signal generating module when the charging is completed. The signal generation module is used for generating a power-on reset signal based on the output electric signal so as to reset the digital circuit. The leakage protection module can be conducted when the electric signal provided by the power supply shakes. To release the charge stored in the delay module. When the power-on reset circuit needs to generate the power-on reset signal again, the delay module can recharge, and the normal operation triggers the power-on reset signal, so that the problem that the conventional POR circuit cannot normally operate when the electric signal provided by the external power supply shakes greatly is solved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic diagram of a conventional power-on reset circuit;
FIG. 2 is a schematic diagram of a power-on reset circuit according to a first embodiment of the present application;
FIG. 3 is a schematic diagram of a power-on reset circuit according to a second embodiment of the present application;
FIG. 4 is a schematic diagram of a power-on reset circuit according to a third embodiment of the present application;
FIG. 5 is a schematic diagram of a power-on reset circuit according to a fourth embodiment of the present application;
FIG. 6 is a schematic diagram of a power-on reset circuit according to a fifth embodiment of the present application;
FIG. 7 is a schematic diagram of a power-on reset circuit according to a sixth embodiment of the present application;
fig. 8 is a schematic diagram of a power-on reset circuit according to a seventh embodiment of the application.
Reference numerals:
10-a power-on reset circuit; a 100-delay module; 110-a delay unit; 111-a second NMOS tube;
120-a current generation unit; 121-a third PMOS tube; 122-a fourth PMOS tube;
123-a fifth PMOS tube; 200-a signal generation module; 210-a first inverter;
211-a sixth PMOS tube; 212-a third NMOS tube; 300-a leakage protection module;
310-a leakage protection unit; 311-resistance; 312-a first NMOS tube; 320-discharging switch;
321-a first PMOS tube; 322-a second PMOS tube; 400-power supply; 500-digital circuits.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
The numbering of the components itself, e.g. "first", "second", etc., in the present application is used only to distinguish between the described objects and does not have any sequential or technical meaning. The term "coupled" as used herein includes both direct and indirect coupling (coupling), unless otherwise indicated. In the description of the present application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element in question must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.
In the present application, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
In the field of integrated circuit design, various integrated circuits may include a Power On Reset (POR) circuit. Typically, when an integrated circuit is powered up, the supply voltage has not reached a stable desired state, and the voltage and logic states of the electronic components and circuit nodes in many digital circuits are unstable. In order to enable the integrated circuit system to operate from a state expected by a designer after each power-up, a power-up reset circuit is required to generate a reset signal when the power supply is powered up, so that the integrated circuit system is forced to be in an initial state expected by the designer, and unstable state at the initial time of power-up is eliminated. One common method is to use a low-pass filter circuit (RC circuit) formed by capacitive resistors to generate a delay, i.e., a delay after the power supply of the integrated circuit is powered up for a period of time, to signal the digital circuit POR. The digital circuit gives a certain output state based on the received POR signal.
The conventional power-on reset circuit is to divide the power supply VDD signal, and then compare the divided resistance voltage division signal with a constant electrical signal by a comparator, wherein the constant electrical signal is generated by a band gap voltage reference circuit. If the resistance voltage division signal is less than or equal to the constant electric signal, the POR signal is not generated; when the resistive divider signal of VDD is greater than the constant electrical signal, a POR signal is given. As shown in fig. 1, the resistor R3 and the capacitor C1 form an RC circuit, delay the voltage change of V1, generate a delayed voltage signal V2, and finally compare V2 with Vbg to obtain the POR signal. However, when the power supply fluctuates, if the fluctuation is relatively large, VDD will decrease to a voltage region where some digital circuits cannot work normally, and at this time, the charge in the capacitor is not completely discharged, so that after VDD returns to normal, the POR signal does not function.
Based on this, an embodiment of the present application provides a power-on reset circuit including: the device comprises a delay module, a signal generation module and a leakage protection module. The leakage protection module is conducted when the electric signal transmitted by the power supply changes from high level to low level. The delay module can discharge stored charges when the leakage protection module is conducted. When the electric signal transmitted by the power supply changes from low level to high level, the delay module can charge, and the generated output electric signal is transmitted to the signal generating module when the charging is completed. The signal generation module is used for generating a power-on reset signal based on the output electric signal so as to reset the digital circuit. The leakage protection module can be conducted when the electric signal provided by the power supply shakes. To release the charge stored in the delay module. When the power-on reset circuit needs to generate the power-on reset signal again, the delay module can recharge, and the normal operation triggers the power-on reset signal, so that the problem that the conventional POR circuit cannot normally operate when the electric signal provided by the external power supply shakes greatly is solved. In order to achieve the above object, the technical solution provided by the embodiments of the present application is described in detail below, with reference to the accompanying drawings.
Referring to fig. 2, a power-on reset circuit 10 according to an embodiment of the present application includes: a delay module 100, a signal generation module 200, and a leakage protection module 300. The first end of the delay module 100, the first end of the signal generating module 200 and the first end of the leakage protection module 300 are electrically connected to the power supply 400, the second end of the delay module 100, the second end of the signal generating module 200 and the second end of the leakage protection module 300 are grounded, the third end of the delay module 100 is electrically connected to the third end of the leakage protection module 300, and the fourth end of the delay module 100 is electrically connected to the third end of the signal generating module 200.
The leakage protection module 300 is used for conducting when the electrical signal transmitted by the power supply 400 changes from a high level to a low level. The delay module 100 is configured to drain stored charges when the drain protection module 300 is turned on, to charge when an electrical signal changes from a low level to a high level, and to transmit a generated output electrical signal to the signal generation module 200 when the charging is completed. The signal generation module 200 is configured to generate a power-on reset signal based on the output electrical signal.
It should be noted that, after the digital circuit 500 has received the power-on reset signal, in order to ensure that the power-on reset circuit 10 is powered on the next time the power supply 400, the digital circuit 500 may normally transmit the power-on reset signal again. The charges stored in the delay module for delay need to be released, so that the power-on reset circuit 10 can normally realize the delay function again, and further normally send the power-on reset signal to the digital circuit 500.
In normal operation of the power-on reset circuit 10, a jitter phenomenon may occur in the electrical signal transmitted by the power supply 400, for example, the electrical signal transmitted by the power supply 400 drops from 1.8V to 1.3V, and the digital circuit 500 has stopped operating normally at 1.4V. However, since the electric signal transmitted by the power supply 400 is not reduced from 1.8V to approximately 0V, the stored electric charge cannot be completely released, and when the power-on reset circuit 10 works next time, the electric charge in the delay module is not completely released, so that the delay module is charged again, and the power-on reset signal cannot be triggered normally due to insufficient delay time of the residual electric charge, and the digital circuit 500 cannot receive the power-on reset signal.
Specifically, the leakage protection module 300 may include a switch, a triode, and other electronic devices. The power supply 400 and the grounding end can be controlled to be conducted through a switch or a triode, meanwhile, a parallel large resistor or an inverse ratio tube in the triode can be used for replacing the large resistor, and the electric signal transmitted by the power supply 400 is divided, so that the electric signal transmitted by the power supply 400 is as close as possible to the starting voltage capable of meeting the requirement that the delay module 100 can completely discharge stored charges. The switch may include, without limitation, a single pole single throw switch, a single pole double throw switch, and the like. The Transistor may include, without limitation, an electron Transistor Triode, a bipolar Transistor (Bipolar Junction Transistor, BJT), a J-type field effect Transistor (Junction gate FET), a Metal Oxide semiconductor field effect Transistor (MOS FET), a V-type trench field effect Transistor (VERTICAL METAL Oxide Semiconductor, VMOS), and the like.
When the electrical signal transmitted by the power supply 400 is changed from the low level to the high level, the method may generally include that the electrical signal transmitted by the power supply 400 is raised from 0V to a predetermined voltage when the integrated circuit is powered on. The preset voltage may be set according to actual use requirements, which is not limited herein. The output electrical signal of the delay module may divide the electrical signal transmitted by the input power 400 by the delay module 100, and then change the electrical signal transmitted by the following power 400 from a low level to a high level.
The delay module 100 may include a current mirror circuit and a capacitor. The first end of the current mirror circuit is electrically connected with the power supply 400, the second end of the current mirror circuit is grounded, the third end of the current mirror circuit is electrically connected with one end of the capacitor, the other end of the capacitor is grounded, and a common end of one end of the capacitor and the third end of the current mirror circuit is electrically connected with the third end of the signal generating module 200.
By presetting the current mirror circuits with different parameters, the current mirror circuits can be used for generating the preset current of the nA level when the electric signal transmitted by the power supply 400 changes from low level to high level, and charging the capacitor by using the generated preset current, the delay of the electric signal can be realized. When the capacitor is fully charged, that is, when charging is completed, the generated output electrical signal is transmitted to the signal generating module.
Alternatively, the capacitor in the delay module 100 may be a MOS transistor. The first end of the current mirror circuit is electrically connected with the power supply 400, the second end of the current mirror circuit is grounded, the third end of the current mirror circuit is electrically connected with one end of the MOS tube, and the other end of the MOS tube is grounded; one end of the MOS tube and the common end of the third end of the current mirror circuit are electrically connected with the third end of the signal generating module 200.
By setting different parameters for the current mirror circuit in advance, the current mirror circuit can be used for generating a preset current of nA level when the electric signal transmitted by the power supply 400 changes from low level to high level, and charging the MOS transistor by using the generated preset current, the delay of the electric signal can be realized. When the MOS transistor capacitor is fully charged, that is, when charging is completed, the generated output electrical signal is transmitted to the signal generating module 200. The MOS transistor may include a P-channel type MOS transistor, an N-channel type MOS transistor, and the like, which are not limited herein.
The signal generating module 200 is configured to perform a comparison process on the output electrical signals, generate a power-on reset signal according to the processing result, and transmit the power-on reset signal to the digital circuit 500.
The signal generating module 200 may include a comparator or an inverter with an external bandgap reference circuit, which is not limited herein.
Specifically, if the signal generating module 200 includes a comparator externally connected to the bandgap reference circuit, the voltage of the output electrical signal and the preset voltage provided by the bandgap reference circuit may be compared by the comparator, and when the voltage of the output electrical signal is greater than the preset voltage, a power-on reset signal is output.
If the signal generating module 200 includes an inverter, the output electrical signal may be compared with a preset inversion voltage threshold of the inverter, and when the voltage of the output electrical signal reaches the inversion voltage threshold, the output electrical signal is inverted, and a power-on reset signal is output.
Optionally, the power-on reset circuit 10 may further include: and a noise removal module. The first end of the noise removing module is used for being electrically connected with the power supply 400, the second end of the noise removing module is grounded, the third end of the noise removing module is electrically connected with the fourth end of the signal generating module, and the fourth end of the noise removing module is electrically connected with the digital circuit 500. The noise removal module is configured to remove noise of the power-on reset signal, and transmit the power-on reset signal after removing the noise to the digital circuit 500.
Wherein, noise removal module includes: a schmitt trigger, a second inverter, and a third inverter; the input end of the Schmitt trigger is electrically connected with the fourth end of the signal generation module, and the Schmitt trigger is electrically connected with the input end of the second inverter; the input end of the third inverter and the input end of the digital circuit 500 are respectively and electrically connected with the output end of the second inverter; the output of the third inverter is electrically connected to the input of the digital circuit 500.
In the present embodiment, since the power-on reset circuit 10 includes the delay module 100, the signal generation module 200, and the leakage protection module 300. The leakage protection module is conducted when the electric signal transmitted by the power supply changes from high level to low level. The delay module can discharge stored charges when the leakage protection module is conducted. The signal generating module 200 generates a power-on reset signal based on the output electric signal, and can release all charges stored in the delay module 100 when the electric signal transmitted by the power supply 400 shakes, so as to ensure that the charges stored in the delay module 100 are completely released when the electric signal transmitted by the power supply 400 shakes, so that the delay module can charge when the electric signal transmitted by the next power supply changes from low level to high level, and transmit the generated output electric signal to the signal generating module when the charging is completed. The signal generation module is used for generating a power-on reset signal based on the output electric signal so as to reset the digital circuit.
The above embodiment describes the power-on reset circuit 10, and in the power-on reset circuit 10, the leakage protection module 300 plays a key role in ensuring that the charge can be normally discharged. The leakage protection module 300 will now be described in one embodiment. In some embodiments, referring to fig. 3, the leakage protection module 300 includes a leakage protection unit 310 and a leakage switch 320. The first end of the discharging switch 320 is electrically connected to the power supply 400, the second end of the discharging switch 320 is grounded, the third end of the discharging switch 320 is electrically connected to one end of the discharging protection unit 310, and the other end of the discharging protection unit 310 is grounded.
The leakage protection unit 310 is configured to divide the electrical signal transmitted by the power supply 400 when the electrical signal changes from a high level to a low level. The discharging switch 320 is used for conducting when the voltage of the electrical signal is reduced to a preset voltage threshold.
The leakage protection unit 310 may include a resistor or a triode, which is not limited herein. The drain switch 320 may include a switch and/or a transistor.
If the discharging switch 320 includes two switches, one end of the first switch is electrically connected to the power supply 400, the common end of one end of the discharging protection unit 310 and the other end of the first switch is electrically connected to one end of the second switch and the third end of the delay module 100, respectively, and the other end of the second switch is grounded. Wherein, the first switch or the second switch can be composed of a plurality of switches connected in series.
If the discharging switch 320 includes two triodes, the first end of the first triode is electrically connected to the power supply 400, the common end of one end of the discharging protection unit 310 and the second end of the first triode is electrically connected to the first end of the second triode, the second end of the second triode is grounded, and the third end of the second triode is electrically connected to the third end of the delay module 100.
If the discharging switch 320 includes a third switch and a third triode, one end of the first switch is electrically connected to the power supply 400, the common end of one end of the discharging protection unit 310 and the other end of the first switch are respectively electrically connected to one end of the third triode, the other end of the third triode is grounded, and the third end of the second triode is electrically connected to the third end of the delay module 100. Wherein, the first switch can be composed of a plurality of switches connected in series.
Specifically, when the electrical signal transmitted by the power supply 400 changes from a high level to a low level, the discharging switch 320 is turned on, and the discharging protection unit 310 divides the electrical signal transmitted by the power supply 400, so that the voltage at the third terminal of the delay module 100 is lower than the voltage of the delay module 100, and the delay module 100 discharges, i.e. discharges the charges stored in the delay module 100.
In the present embodiment, since the leakage protection module 300 includes the leakage protection unit 310 and the leakage switch 320. When the electric signal transmitted by the power supply 400 changes from high level to low level, the leakage protection unit 310 switches on the direct current path between the power supply 400 and the ground, and the voltage of the electrical connection between the leakage protection module 300 and the delay module 100 is close to 0V. At this time, the delay module 100 discharges, so as to ensure that the power-on reset circuit 10 is powered on again and can normally operate to generate a power-on reset signal.
In some embodiments, referring to fig. 4, the drain switch 320 includes: a first PMOS transistor 321 and a second PMOS transistor 322. The source of the first PMOS transistor 321 is electrically connected to the power supply 400, the drain and the gate of the first PMOS transistor 321 are electrically connected to the gate of the second PMOS transistor 322, the drain of the second PMOS transistor 322 is grounded, and the source of the second PMOS transistor 322 is electrically connected to the delay module 100. Through the conduction characteristic of the MOS tube, the MOS tube can be applied to a low-power-consumption scene, and has the advantages of low cost and small occupied space.
In some embodiments, referring to fig. 5, the leakage protection unit 310 includes a resistor 311; the drain electrode, the gate electrode of the first PMOS transistor 321 and the first common terminal electrically connected to the gate electrode of the second PMOS transistor 322 are electrically connected to one terminal of the resistor 311, and the other terminal of the resistor 311 is grounded. The voltage division of the electric signal transmitted by the power supply 400 is realized through the resistor 311, so that the voltage of the electric signal transmitted by the power supply 400 is reduced to a voltage condition of switching on the power supply 400 and the grounding terminal, and the delay module 100 is further discharged.
In some embodiments, referring to fig. 5, the leakage protection unit 310 further includes a first NMOS tube 312; the grid electrode of the first NMOS tube 312 is electrically connected with the first common end, and the source electrode and the drain electrode of the first NMOS tube 312 are grounded; the first NMOS transistor 312 is configured to absorb a glitch signal of the electrical signal. When the electrical signal is only slightly changed to generate a weak burr signal, but the burr signal is not enough to be conducted with the bleeder switch, the burr signal can be absorbed by the first NMOS tube 312, so that false touch is avoided.
The foregoing embodiment describes the power-down module, and in the power-on reset circuit 10, the delay module 100 is also a very important part, and the delay module 100 will be further described with an embodiment. In some embodiments, referring to fig. 6, the delay module 100 includes a delay unit 110 and a current generation unit 120. The first end power supply 400 of the current generating unit 120 is electrically connected, the second end of the current generating unit 120 is grounded, the third end of the current generating unit 120 is grounded to one end of the delay unit 110, and the other end of the delay unit 110 is grounded.
The delay unit 110 is used for discharging the stored charge when the leakage protection module 300 is turned on. The current generating unit 120 is configured to generate a current for controlling a charging period when the power supply 400 is powered on, and transmit the current to the delay unit 110. The delay unit 110 is used to facilitate charging by current. The current generating unit 120 is configured to transmit the output electrical signal to the signal generating module 200 when the charging of the delay unit 110 is completed.
The delay unit 110 may include a capacitor or a MOS transistor. When the electrical signal transmitted by the power supply 400 changes from high level to low level and satisfies the conduction condition of the leakage protection module 300, the stored charge is discharged.
When the power-on reset circuit 10 needs to generate the power-on reset signal, the current generating unit 120 may generate a current for controlling the charging period. The current generating unit 120 may include a current mirror circuit, and the current mirror circuit may include a mirror sub-unit and a voltage dividing sub-unit therein. The first end of the mirror sub-unit is electrically connected to the power supply 400, the second end of the mirror sub-unit is connected to the voltage dividing sub-unit, the second end of the voltage dividing sub-unit is grounded, and the second end of the mirror sub-unit and the common end of the voltage dividing sub-unit are electrically connected to one end of the delay unit 110. Wherein the voltage dividing subunit may comprise a resistor or a reverse proportional tube.
The voltage dividing subunit is configured to divide the electrical signal transmitted from the power supply 400 to the mirror subunit, and then generate nA-level current for controlling the charging duration together with the mirror subunit, and transmit the current to the delay unit 110. The delay unit 110 is charged with current, and the current generation unit 120 transmits the generated output electrical signal to the signal generation module 200 when the charging of the delay unit 110 is completed. The current generating unit can replace a low-pass filter circuit in a traditional POR circuit, the occupied space of used devices is smaller, the cost is lower, and nA-level current which cannot be achieved by the traditional low-pass filter circuit can be generated, so that the power consumption of the power-on reset circuit 10 in the operation process is reduced.
In some embodiments, referring to fig. 7, the current generating unit 120 includes a third PMOS transistor 121, a fourth PMOS transistor 122, and a fifth PMOS transistor 123. The fourth PMOS transistor 122 is an inverse ratio transistor. The source of the third PMOS transistor 121 and the source of the fifth PMOS transistor 123 are electrically connected to the power supply 400, respectively, the drain of the third PMOS transistor 121 is electrically connected to the source of the fourth PMOS transistor 122, the drain of the fourth PMOS transistor 122 is grounded, and the drain of the third PMOS transistor 121 and the gate of the fifth PMOS transistor 123 are electrically connected to the gate of the third PMOS transistor 121, respectively. One end of the delay unit 110, the third end of the signal generating module 200, and the second common end of the third end of the leakage protection module 300 are electrically connected to the drain of the fifth PMOS transistor 123. The MOS transistor structure is integrally adopted, so that nA-level current can be generated to realize that the power-on reset circuit 10 operates under extremely low power consumption, and meanwhile, the overall size is smaller and the cost is lower.
In some embodiments, referring to fig. 7, the delay unit 110 includes a second NMOS transistor 111. The gate of the second NMOS transistor 111 is electrically connected to the second common terminal, and both the source and the drain of the second NMOS transistor 111 are grounded. And the MOS tube structure is adopted, so that the occupied integrated circuit is smaller in size and lower in cost.
In the present embodiment, the delay module 100 includes a delay unit 110 and a current generation unit 120. The current generation unit 120 generates a current that controls a charging period when the power supply 400 is powered on, and transmits the current to the delay unit 110. The delay unit 110 is charged with current, and the current generation unit 120 transmits an output electrical signal to the signal generation module 200 when the delay unit 110 is charged. The delay module 100 can generate a micro current of nA level through the current generation unit 120 and transmit to the delay unit 110 to perform delay of the charging implementation signal. The delay module can generate nA-level current to realize that the power-on reset circuit 10 operates under extremely low power consumption, and meanwhile, the overall size is smaller and the cost is lower.
The above embodiment describes the delay module 100, and after the delay module 100 delays, the signal is transmitted to the signal generating module 200 to generate the power-on reset signal. The signal generation module 200 will now be described in one embodiment. In one embodiment, referring to fig. 8, the signal generation module 200 includes a first inverter 210. The first end of the first inverter 210 is electrically connected to the power supply 400, the second end of the first inverter 210 is grounded, the third end of the first inverter 210 is electrically connected to the fourth end of the delay module 100, and the fourth end of the first inverter 210 is electrically connected to the digital circuit 500.
The first inverter 210 is configured to stop inverting the output electrical signal to generate a power-on reset signal when the voltage of the output electrical signal is less than a preset reverse voltage threshold.
In the design of electronic circuits, inverters are often used. An inverter is a circuit that can invert the phase of an input signal by 180 degrees. A common CMOS inverter circuit consists of two enhancement mode MOS field effect transistors. A typical TTL NAND gate consists of an input stage, an intermediate stage and an output stage. In the design of integrated circuits, the power-on reset signal is typically designed as an electrical signal that changes from a high level to a low level.
In some embodiments, referring to fig. 8, the first inverter 210 includes: a sixth PMOS transistor 211 and a third NMOS transistor 212. The source of the sixth PMOS transistor 211 is electrically connected to the power supply 400, the drain of the sixth PMOS transistor 211 is electrically connected to the drain of the third NMOS transistor 212, and the source of the third NMOS transistor 212 is grounded. The third common terminal of the sixth PMOS transistor 211 and the third NMOS transistor 212 are electrically connected to the fourth terminal of the delay module 100.
As can be seen from the above, in the technical solution provided in the embodiment of the present application, the signal generating module 200 includes the first inverter 210. The first inverter 210 stops inverting the output electrical signal to generate a power-on reset signal when the voltage of the output electrical signal is less than a preset reverse voltage threshold. The level of the output electrical signal transmitted by the delay module 100 can be inverted through the first inverter 210, so as to obtain a power-on reset signal changed from a high level to a low level, and compared with a comparator in a traditional POR circuit, the first inverter does not need to be externally connected with a band gap reference circuit to provide a constant reference voltage, has lower power consumption and has the advantage of smaller volume.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (9)
1. A power-on reset circuit, comprising: the device comprises a delay module, a signal generation module and a leakage protection module; the first end of the delay module, the first end of the signal generation module and the first end of the leakage protection module are electrically connected with a power supply; the second end of the delay module, the second end of the signal generation module and the second end of the leakage protection module are grounded; the third end of the delay module is electrically connected with the third end of the leakage protection module; the fourth end of the delay module is electrically connected with the third end of the signal generation module;
the leakage protection module is used for being conducted when the electric signal transmitted by the power supply changes from a high level to a low level;
The delay module is used for discharging stored charges when the leakage protection module is conducted so as to charge when the electric signal changes from low level to high level, and transmitting the generated output electric signal to the signal generation module when the charging is completed, and the delay module comprises a delay unit and a current generation unit; the first end of the current generation unit is electrically connected with the power supply, the second end of the current generation unit is grounded, and the third end of the current generation unit is connected with one end of the delay unit; the other end of the delay unit is grounded, and the delay unit is used for discharging stored charges when the leakage protection module is conducted; the current generation unit is used for generating current for controlling the charging duration when the power supply is electrified and transmitting the current to the delay unit; the delay unit is used for charging the current; the current generation unit is used for transmitting the output electric signal to the signal generation module when the delay unit is charged; the signal generation module is used for generating a power-on reset signal based on the output electric signal.
2. The power-on reset circuit of claim 1, wherein the power-off protection module comprises a power-off protection unit and a power-off switch; the first end of the power release switch is electrically connected with the power supply, the second end of the power release switch is grounded, the third end of the power release switch is electrically connected with one end of the power release protection unit, and the other end of the power release protection unit is grounded;
The leakage protection unit is used for dividing the electric signal transmitted by the power supply when the electric signal changes from a high level to a low level;
the leakage switch is used for being conducted after the voltage of the electric signal is reduced to a preset voltage threshold value.
3. The power-on reset circuit of claim 2, wherein the power-off switch comprises: the first PMOS tube and the second PMOS tube; the source stage of the first PMOS tube is electrically connected with the power supply, and the drain electrode and the grid electrode of the first PMOS tube are electrically connected with the grid electrode of the second PMOS tube; the drain electrode of the second PMOS tube is grounded, and the source electrode of the second PMOS tube is electrically connected with the delay module.
4. A power-on reset circuit as recited in claim 3, wherein the leakage protection unit comprises a resistor; the drain electrode, the grid electrode of the first PMOS tube and the first common end electrically connected with the grid electrode of the second PMOS tube are electrically connected with one end of the resistor, and the other end of the resistor is grounded.
5. The power-on reset circuit of claim 4, wherein the leakage protection unit further comprises a first NMOS transistor; the grid electrode of the first NMOS tube is electrically connected with the first common end, and the source electrode and the drain electrode of the first NMOS tube are grounded;
The first NMOS tube is used for absorbing burr signals of the electric signals.
6. The power-on reset circuit of claim 5, wherein the current generation unit comprises a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor; wherein the fourth PMOS tube is an inverse ratio tube; the source stage of the third PMOS tube and the source stage of the fifth PMOS tube are respectively and electrically connected with the power supply; the drain electrode of the third PMOS tube is electrically connected with the source electrode of the fourth PMOS tube, and the drain electrode of the fourth PMOS tube is grounded; the drain electrode of the third PMOS tube and the grid electrode of the fifth PMOS tube are respectively and electrically connected with the grid electrode of the third PMOS tube; one end of the delay unit, the third end of the signal generation module and the second common end of the third end of the leakage protection module are electrically connected with the drain electrode of the fifth PMOS tube.
7. The power-on reset circuit of claim 6, wherein the delay unit comprises a second NMOS transistor; the grid electrode of the second NMOS tube is electrically connected with the second common end; and the source electrode and the drain electrode of the second NMOS tube are grounded.
8. The power-on reset circuit of claim 5, wherein the signal generation module comprises a first inverter; the first end of the first inverter is used for being electrically connected with the power supply, the second end of the first inverter is grounded, the third end of the first inverter is electrically connected with the fourth end of the delay module, and the fourth end of the first inverter is electrically connected with the digital circuit;
and the first inverter is used for stopping inverting the output electric signal to generate a power-on reset signal when the voltage of the output electric signal is smaller than a preset reverse voltage threshold value.
9. The power-on reset circuit of claim 8, wherein the first inverter comprises: a sixth PMOS tube and a third NMOS tube; the source stage of the sixth PMOS tube is electrically connected with the power supply, the drain electrode of the sixth PMOS tube is electrically connected with the drain electrode of the third NMOS tube, and the source stage of the third NMOS tube is grounded; and the third common end of the sixth PMOS tube and the third NMOS tube is electrically connected with the fourth end of the delay module.
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| CN117240270B (en) * | 2023-09-15 | 2024-11-05 | 深圳市紫光同创电子有限公司 | Power-on reset circuit, chip and electronic equipment |
| CN118971587B (en) * | 2024-10-12 | 2025-01-17 | 深圳市苏非科技有限公司 | Emergency protection circuit of a monitor |
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