CN113114191A

CN113114191A - Reset circuit, circuit board and reset device

Info

Publication number: CN113114191A
Application number: CN202110423747.8A
Authority: CN
Inventors: 王坤鹏; 张芳豪
Original assignee: Zhuhai Boya Technology Co ltd
Current assignee: Zhuhai Boya Technology Co ltd
Priority date: 2021-04-20
Filing date: 2021-04-20
Publication date: 2021-07-13

Abstract

The invention discloses a reset circuit, a circuit board and a reset device, wherein the reset circuit comprises a reset signal generation module, the reset signal generation module comprises a first NMOS tube, a second NMOS tube, a first voltage division unit, a second voltage division unit, a third voltage division unit and a fourth voltage division unit; the drain electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, the grid electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected to a power supply through a first voltage division unit; the drain electrode of the second NMOS tube is connected to the power supply through the second voltage division unit, the drain electrode of the second NMOS tube is connected to the source electrode of the second NMOS tube through the third voltage division unit, and the source electrode of the second NMOS tube is connected to the ground through the fourth voltage division unit. The reset circuit has the advantages of simple structure and low cost, and can reduce the problem of power-on reset failure when the power supply is electrified for the second time.

Description

Reset circuit, circuit board and reset device

Technical Field

The embodiment of the invention relates to the field of integrated circuits, but not limited to the field of integrated circuits, in particular to a reset circuit, a circuit board and a reset device.

Background

At present, when a chip power supply is powered on, the voltage and logic state of each node on a circuit of the chip power supply are unstable, which may cause the chip to operate incorrectly, and then a reset signal is usually generated to initialize a register in a digital circuit, so as to ensure the normal operation of the chip.

Disclosure of Invention

The embodiment of the invention mainly aims to provide a reset circuit, a circuit board and a reset device, wherein the reset circuit has the advantages of simple structure and low cost, and can reduce the problem of power-on reset failure when a power supply is powered on for the second time.

In a first aspect, an embodiment of the present invention provides a reset circuit, including: the reset signal generation module comprises a first NMOS tube, a second NMOS tube, a first voltage division unit, a second voltage division unit, a third voltage division unit and a fourth voltage division unit;

the drain electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, the grid electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected to a power supply through the first voltage division unit;

the drain electrode of the second NMOS tube is connected to the power supply through the second voltage division unit, the drain electrode of the second NMOS tube is connected to the source electrode of the second NMOS tube through the third voltage division unit, and the source electrode of the second NMOS tube is connected to the ground through the fourth voltage division unit.

Optionally, the second voltage division unit is a first PMOS transistor and a first resistor, the first voltage division unit is a second PMOS transistor, a source of the first PMOS transistor is connected to the power supply, a source of the second PMOS transistor is connected to the power supply, a gate of the first PMOS transistor is connected to a gate of the second PMOS transistor, a drain of the first PMOS transistor is connected to a gate of the first PMOS transistor, one end of the first resistor is connected to a drain of the first PMOS transistor, the other end of the first resistor is connected to a gate of the first NMOS transistor, and a drain of the second PMOS transistor is connected to a drain of the first NMOS transistor.

Optionally, the reset signal generation module further includes a schmitt trigger, a drain of the first NMOS transistor is connected to an input terminal of the schmitt trigger, and a gate of the second NMOS transistor is connected to an output terminal of the schmitt trigger.

Optionally, the apparatus further includes a delay module connected to an output end of the reset signal generation module, where the delay module is configured to generate, according to the first signal output by the reset signal generation module, a second signal that is delayed by a first time from the pulse signal output by the reset signal generation module.

Optionally, the delay module further comprises an amplifying and inverting module connected to an output end of the delay module, and the amplifying and inverting module is configured to amplify and invert the signal output by the delay module.

In a second aspect, a reset circuit includes: the reset signal generation module comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first voltage division unit, a second voltage division unit, a third voltage division unit and a fourth voltage division unit;

the grid electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube, the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is connected to the ground through the first voltage division unit;

the grid electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, the source electrode of the second PMOS tube is connected to the power supply through the second voltage division unit, the source electrode of the second PMOS tube is connected to the drain electrode of the second PMOS tube through the third voltage division unit, and the drain electrode of the second PMOS tube is connected to the ground through the fourth voltage division unit.

Optionally, the second voltage division unit is a first NMOS transistor and a first resistor, the first voltage division unit is a second NMOS transistor, a source of the first NMOS transistor is grounded, a source of the second NMOS transistor is grounded, a gate of the first NMOS transistor is connected to a gate of the second NMOS transistor, a drain of the first NMOS transistor is connected to a gate of the first NMOS transistor, one end of the first resistor is connected to a drain of the first NMOS transistor, the other end of the first resistor is connected to a gate of the first PMOS transistor, and a drain of the second NMOS transistor is connected to a drain of the first PMOS transistor.

Optionally, the reset signal generation module further includes a schmitt trigger, a drain of the first PMOS transistor is connected to an input terminal of the schmitt trigger, and a gate of the second PMOS transistor is connected to an output terminal of the schmitt trigger.

In a third aspect, an embodiment of the present invention further provides a circuit board, including the reset circuit in the first aspect, or the reset circuit in the second aspect.

In a fourth aspect, an embodiment of the present invention further provides a resetting device, including the circuit board of the third aspect.

The reset circuit comprises a reset signal generation module, wherein the reset signal generation module comprises a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first voltage division unit, a second voltage division unit, a third voltage division unit and a fourth voltage division unit; the drain electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, the grid electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected to a power supply through a first voltage division unit; the drain electrode of the second NMOS tube is connected to a power supply through a second voltage division unit, the drain electrode of the second NMOS tube is connected to the source electrode of the second NMOS tube through a third voltage division unit, and the source electrode of the second NMOS tube is connected to the ground through a fourth voltage division unit; under the condition that the voltage of a power supply is increased, the voltage value of the grid electrode of the second NMOS tube is smaller than the threshold voltage value, the second NMOS tube is cut off to enable the first NMOS tube to be conducted, and the drain electrode of the first NMOS tube generates a first pulse signal which is reduced from a high level to a low level; under the condition that the voltage of the power supply is reduced, the voltage value of the grid electrode of the second NMOS tube is larger than the threshold voltage value, the second NMOS tube is conducted to cut off the first NMOS tube, and the drain electrode of the first NMOS tube generates a second pulse signal which is increased from a low level to a high level. The reset circuit has the advantages of simple structure and low cost, and can reduce the problem of power-on reset failure when the power supply is electrified for the second time.

Drawings

FIG. 1 is a schematic diagram of a reset circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a reset circuit according to another embodiment of the present invention;

FIG. 3 is a schematic diagram of a reset circuit according to another embodiment of the present invention;

fig. 4 is a schematic diagram of a first schmitt trigger of a reset circuit according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a first schmitt trigger of a reset circuit according to another embodiment of the present invention;

FIG. 6 is a schematic diagram of a reset circuit according to another embodiment of the present invention;

FIG. 7 is a schematic diagram of a reset circuit according to another embodiment of the present invention;

fig. 8 is a schematic diagram of a reset circuit according to another embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

It should be noted that although functional blocks are partitioned in a schematic diagram of an apparatus and a logical order is shown in a flowchart, in some cases, the steps shown or described may be performed in a different order than the partitioning of blocks in the apparatus or the order in the flowchart. The terms first, second and the like in the description and in the claims, and the drawings described above, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

The embodiment provides a reset circuit, a circuit board and a reset device, wherein the reset circuit comprises a reset signal generation module, and the reset signal generation module comprises a first NMOS tube, a second NMOS tube, a first voltage division unit, a second voltage division unit, a third voltage division unit and a fourth voltage division unit; the drain electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, the grid electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected to a power supply through a first voltage division unit; the drain electrode of the second NMOS tube is connected to a power supply through a second voltage division unit, the drain electrode of the second NMOS tube is connected to the source electrode of the second NMOS tube through a third voltage division unit, and the source electrode of the second NMOS tube is connected to the ground through a fourth voltage division unit; under the condition that the voltage of a power supply is increased, the voltage value of the grid electrode of the second NMOS tube is smaller than the threshold voltage value, the second NMOS tube is cut off to enable the first NMOS tube to be conducted, and the drain electrode of the first NMOS tube generates a first pulse signal which is reduced from a high level to a low level; under the condition that the voltage of the power supply is reduced, the voltage value of the grid electrode of the second NMOS tube is larger than the threshold voltage value, the second NMOS tube is conducted to cut off the first NMOS tube, and the drain electrode of the first NMOS tube generates a second pulse signal which is increased from a low level to a high level. The reset circuit has the advantages of simple structure and low cost, and can reduce the problem of power-on reset failure when the power supply is electrified for the second time.

The embodiments of the present invention will be further explained with reference to the drawings.

As shown in fig. 1, fig. 1 is a schematic diagram of a reset circuit in a first embodiment, the reset circuit includes a reset signal generating module, and the reset signal generating module includes a first NMOS transistor MN1, a second NMOS transistor MN2, a first voltage dividing unit R1, a second voltage dividing unit R2, a third voltage dividing unit R3, and a fourth voltage dividing unit R4; the drain electrode of the first NMOS tube MN1 is connected with the gate electrode of the second NMOS tube MN2, the gate electrode of the first NMOS tube MN1 is connected with the drain electrode of the second NMOS tube MN2, the source electrode of the first NMOS tube MN1 is grounded, and the drain electrode of the first NMOS tube MN1 is connected to a power supply through a first voltage division unit R1; the drain of the second NMOS transistor MN2 is connected to the power supply through the second voltage dividing unit R2, the drain of the second NMOS transistor MN2 is connected to the source of the second NMOS transistor MN2 through the third voltage dividing unit R3, and the source of the second NMOS transistor MN2 is connected to the ground through the fourth voltage dividing unit R4. The reset circuit has the advantages of simple structure and low cost, and can reduce the problem of power-on reset failure when the power supply is electrified for the second time.

In the process that the voltage of the power supply starts to rise from 0V, the voltage of the gate of the second NMOS transistor MN2 gradually rises from 0V, at the moment, the voltage of the gate of the first NMOS transistor MN1 is smaller than the threshold voltage of the first NMOS transistor MN1, the first NMOS transistor MN1 is switched to the off state, the voltage of the drain of the first NMOS transistor MN1 gradually increases along with the power supply, when the voltage of the gate of the first NMOS transistor MN1 rises to the threshold voltage of the first NMOS transistor MN1, the first NMOS transistor MN1 is turned on, the voltage of the drain of the first NMOS transistor MN1 gradually decreases, namely, the voltage of the gate of the second NMOS transistor MN2 gradually decreases, when the voltage of the gate of the second NMOS transistor MN2 decreases to be smaller than the threshold voltage of the second NMOS transistor MN2, at the moment, the second NMOS transistor MN2 is switched to the off state, the voltage of the gate of the first NMOS transistor MN1 suddenly increases, the voltage of the drain of the first NMOS transistor MN1 is switched to the fully on state, so that the voltage of the first NMOS transistor MN1 directly decreases to 0V, thereby generating a first pulse signal that falls from a high level to a low level, the first pulse signal being a power-on reset signal.

When the voltage of the power supply is falling, the voltage of the gate of the first NMOS transistor MN1 gradually decreases, the voltage of the drain of the first NMOS transistor MN1 gradually increases, and when the voltage of the drain of the first NMOS transistor MN1 increases to be greater than the threshold voltage of the second NMOS transistor MN2, the second NMOS transistor MN2 switches to the on state, the voltage of the gate of the first NMOS transistor MN1 decreases at an accelerated rate, and the first NMOS transistor MN1 switches to the off state, so that the voltage of the drain of the first NMOS transistor MN1 increases to the voltage value of the power supply, thereby generating a second pulse signal that increases from a low level to a high level, where the second pulse signal is a power-down reset signal.

The first voltage dividing unit R1 and the second voltage dividing unit R2 may be PMOS transistors, resistors, or voltage dividing units in which PMOS transistors and resistors are connected in series, and this embodiment is not particularly limited.

The third voltage divider R3 may be a fixed resistor or a variable resistor, and this embodiment is not particularly limited thereto.

It should be noted that the fourth voltage dividing unit R4 may be an NMOS transistor with a drain and a gate connected, may be a resistor, or may be a diode, and this embodiment is not particularly limited thereto.

It should be noted that the specific specifications of the first NMOS transistor MN1 and the second NMOS transistor MN2 may be set according to practical situations, and the present embodiment does not specifically limit the specifications.

As shown in fig. 2, in an embodiment, based on the reset circuit shown in fig. 1, the second voltage dividing unit R2 is a first PMOS transistor MP1 and a first resistor R5, the first voltage dividing unit R1 is a second PMOS transistor MP2, a source of the first PMOS transistor MP1 is connected to a power supply, a source of the second PMOS transistor MP2 is connected to the power supply, a gate of the first PMOS transistor MP1 is connected to a gate of the second PMOS transistor MP2, a drain of the first PMOS transistor MP1 is connected to a gate of the first PMOS transistor MP1, one end of the first resistor R5 is connected to a drain of the first PMOS transistor MP1, the other end is connected to a gate of the first NMOS transistor MN1, and a drain of the second PMOS transistor MP2 is connected to a drain of the first NMOS transistor MN 1. The drain voltage of the first PMOS transistor MP1 can control the voltages of the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2, so that the resistances of the first PMOS transistor MP1 and the second PMOS transistor MP2 in a conducting state can be controlled, the control capability of the reset circuit is increased, the reset circuit has the advantages of simple structure and low cost, and the problem of power-on reset failure during the secondary power-on of the power supply can be reduced.

In the process that the voltage of the power supply starts to rise from 0V, the initial voltage of the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 is 0, the first PMOS transistor MP1 and the second PMOS transistor MP2 are in the on state, the voltage of the gate of the second NMOS transistor MN2 gradually rises from 0V, at this time, the voltage of the gate of the first NMOS transistor MN1 is less than the threshold voltage of the first NMOS transistor MN1, the first NMOS transistor MN1 is switched to the off state, the voltage of the drain of the first NMOS transistor MN1 gradually increases with the power supply, when the voltage of the gate of the first NMOS transistor MN1 rises to the threshold voltage of the first NMOS transistor MN 63 1, the first NMOS transistor MN1 is turned on, the voltage of the drain of the first NMOS transistor MN1 gradually decreases, that is, the voltage of the gate of the second NMOS transistor MN2 gradually decreases, when the voltage of the gate of the second NMOS transistor MN2 decreases to be less than the threshold voltage of the second NMOS transistor MN2, at this time, the gate of the second NMOS transistor MN1 9 is switched to the off state, the switching of the first NMOS transistor MN1 to the fully on state is accelerated, so that the voltage at the drain of the first NMOS transistor MN1 directly drops to 0V, thereby generating a first pulse signal that drops from a high level to a low level, where the first pulse signal is a power-on reset signal.

Under the condition that the voltage of the power supply is reduced, the voltages of the gates of the first PMOS tube MP1 and the second PMOS tube MP2 are gradually reduced, the voltage of the gate of the first NMOS tube MN1 is gradually reduced, the voltage of the drain of the first NMOS tube MN1 is gradually increased, when the voltage of the drain of the first NMOS tube MN1 is increased to be larger than the threshold voltage of the second NMOS tube MN2, the second NMOS tube MN2 is switched to be in an on state, the voltage of the gate of the first NMOS tube MN1 is accelerated to be reduced, the first NMOS tube MN1 is switched to be in an off state, so that the voltage of the drain of the first NMOS tube MN1 is increased to the voltage value of the power supply, and therefore a second pulse signal which is increased from a low level to a high level is generated, and the second pulse signal is a power-down reset signal.

As shown in fig. 3, in an embodiment, based on the reset circuit of fig. 2, the reset signal generating module in the reset circuit further includes a first schmitt trigger BL1, the drain of the first NMOS transistor MN1 is connected to the input terminal of the first schmitt trigger BL1, the gate of the second NMOS transistor MN2 is connected to the output terminal of the first schmitt trigger BL1, as in the power-up process, the first schmitt trigger BL1 may generate a third pulse signal according to the first pulse signal generated by the drain of the first NMOS transistor MN1 received at the input terminal, the slope of the third pulse signal is greater than the slope of the first pulse signal, that is, the voltage of the third pulse signal can be decreased to 0V more quickly than the voltage of the first pulse signal, the accuracy of the reset signal can be improved, the reset circuit has the advantages of simple structure and low cost, and can reduce the problem of power-on reset failure when the power supply is electrified for the second time.

In the process that the voltage of the power supply starts to rise from 0V, the initial voltage of the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 is 0, the first PMOS transistor MP1 and the second PMOS transistor MP2 are in an on state, the voltage of the gate of the second NMOS transistor MN2 gradually rises from 0V, at this time, the voltage of the gate of the first NMOS transistor MN1 is less than the threshold voltage of the first NMOS transistor MN1, the first NMOS transistor MN1 is switched to an off state, the voltage of the drain of the first NMOS transistor MN1 gradually increases with the power supply, when the voltage of the gate of the first NMOS transistor MN1 rises to the threshold voltage of the first NMOS transistor MN 63 1, the first NMOS transistor MN1 is turned on, the voltage of the drain of the first NMOS transistor MN1 gradually decreases, so that the voltage of the gate of the second NMOS transistor MN2 gradually decreases, when the voltage of the gate of the second NMOS transistor MN2 decreases to be less than the threshold voltage of the second NMOS transistor MN2, at this time, the gate of the second NMOS transistor MN1 9 gradually increases, the switching of the first NMOS transistor MN1 to a complete conduction state is accelerated, so that the voltage of the drain electrode of the first NMOS transistor MN1 is rapidly reduced to 0V, a first pulse signal which is a power-on reset signal and is reduced from a high level to a low level is generated, the first pulse signal generates a third pulse signal through the first Schmitt trigger BL1, the slope of the pulse signal output by the reset circuit can be larger, and the accuracy of the reset signal is improved.

When the voltage of the power supply is reduced, the voltages of the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are gradually reduced, the voltage of the gate of the first NMOS transistor MN1 is gradually reduced, the voltage of the drain of the first NMOS transistor MN1 is gradually increased, when the voltage of the drain of the first NMOS transistor MN1 is increased to be greater than the threshold voltage of the second NMOS transistor MN2, the second NMOS transistor MN2 is switched to the on state, the voltage of the gate of the first NMOS transistor MN1 is rapidly reduced, the first NMOS transistor MN1 is switched to the off state, so that the voltage of the drain of the first NMOS transistor MN1 is increased to the voltage value of the power supply, thereby generating a second pulse signal which is a power-down reset signal, and the second pulse signal generates a fourth pulse signal through the first schmitt trigger BL1, so that the slope of the pulse signal output by the reset circuit can be larger, and the accuracy of the reset signal can be improved.

The configuration of the first schmitt trigger BL1 is not particularly limited, and any configuration of the first schmitt trigger BL1 that can achieve the effect of increasing the slope of the pulse signal output from the reset circuit is within the scope of the present application.

In one embodiment, as shown in fig. 4, the first schmitt trigger BL1 may include a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a first inverter INV 1; a source of a first PMOS transistor MP1 is connected to a second power supply, a drain of the first PMOS transistor MP1 is connected to an input terminal of a first inverter INV1, a gate of the first PMOS transistor MP1 is connected to a gate of a third NMOS transistor MN3, a source of the second PMOS transistor MP2 is connected to the second power supply, a gate of the first PMOS transistor MP1 is connected to a gate of the second PMOS transistor MP2, a drain of the second PMOS transistor MP2 is connected to a source of a third PMOS transistor MP3, a gate of the third PMOS transistor MP3 is connected to an output terminal of the first inverter INV1, a source of the third PMOS transistor MP3 is connected to an input terminal of the first inverter INV1, a drain of the third PMOS transistor MP3 is connected to a drain of a fifth NMOS transistor MN5, a gate of the fifth NMOS transistor MN5 is connected to an output terminal of the first inverter INV1, a source of the fifth NMOS transistor MN5 is connected to a drain of the fourth NMOS transistor MN4, a drain of the fourth NMOS transistor MN 632 is connected to a gate of the fourth NMOS transistor MN4, and a gate of the NMOS transistor MN 828653, the drain of the third NMOS transistor MN3 is connected to the drain of the first PMOS transistor MP1, and the source of the third NMOS transistor MN3 is grounded, wherein the gate of the first PMOS transistor MP1 is the input terminal of the first schmitt trigger BL1, and the output terminal of the first inverter INV1 is the output terminal of the first schmitt trigger BL 1. The third PMOS transistor MP3, the fifth NMOS transistor MN5, and the first inverter INV1 in the first schmitt trigger BL1 form a positive feedback circuit structure, which can increase the switching speed of the first schmitt trigger BL1, the static power consumption of the first schmitt trigger BL1 is 0W, and the first schmitt trigger BL1 consumes energy when it is in the state of switching the output level. The first schmitt trigger BL1 can increase the slope of the pulse signal output from the reset circuit, thereby improving the accuracy of the reset signal.

When the input end of the first schmitt trigger BL1 is in a low level state, the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3 are turned on, the third NMOS transistor MN3, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are turned off, and the output end of the first schmitt trigger BL1 is in a low level state;

when the voltage at the input end of the first schmitt trigger BL1 changes from low to high, the third NMOS transistor MN3 gradually turns on, the voltage at the input end of the first inverter INV1 gradually decreases, and at the same time, the voltage at the output end of the first inverter INV1 gradually increases, and when the voltage at the input end of the first inverter INV1 is lower than the inversion voltage of the first inverter INV1, the third PMOS transistor MP3 gradually turns off, and the fifth NMOS transistor MN5 gradually turns on, so that the voltage at the input end of the first inverter INV1 decreases in the ground equivalent resistance, and the voltage at the input end of the first inverter INV1 can be further decreased, thereby accelerating the speed of increasing the voltage at the output end of the first inverter INV1, and accelerating the turning on of the fifth NMOS transistor MN5 and turning off of the third PMOS transistor MP 3535 3, so that the voltage at the output end of the first inverter INV1 rapidly increases to high level.

When the input end of the first schmitt trigger BL1 is in a high level state, the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3 are turned off, the third NMOS transistor MN3, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are turned on, and the output end of the first schmitt trigger BL1 is in a high level state;

when the voltage at the input end of the first schmitt trigger BL1 changes from high to low, the first PMOS transistor MP1 gradually turns on, the voltage at the input end of the first inverter INV1 gradually increases, and at the same time, the voltage at the output end of the first inverter INV1 gradually decreases, and when the voltage at the input end of the first inverter INV1 is higher than the inversion voltage of the first inverter INV1, the third PMOS transistor MP3 gradually turns on, and the fifth NMOS transistor MN5 gradually turns off, so that the power supply equivalent resistance at the input end of the first inverter INV1 decreases, the voltage at the input end of the first inverter INV1 can be further increased, the speed of decreasing the voltage at the output end of the first inverter INV1 is accelerated, and therefore, the turning on of the third PMOS transistor MP3 and the turning off of the fifth NMOS 35mn 5 are accelerated, and the output end of the first inverter INV1 rapidly decreases to low level.

It should be noted that the requirements of the threshold voltage and the hysteresis width of the first schmitt trigger BL1 can be determined by selecting different model specifications of the second PMOS transistor MP2 and the fourth NMOS transistor MN4, which is not specifically limited in this embodiment.

In an embodiment, as shown in fig. 5, the first schmitt trigger BL1 may include a first PMOS transistor MP1, a second PMOS transistor MP2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first inverter INV1, and a second inverter INV2, wherein a source of the first PMOS transistor MP1 is connected to the power supply, a gate of the first PMOS transistor MP1 is connected to the input terminal of the first inverter INV1, a drain of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2, a gate of the second PMOS transistor MP2 is connected to the output terminal of the second inverter INV2, a drain of the second PMOS transistor MP2 is connected to the input terminal of the second inverter INV2, an output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2, a drain of the third NMOS transistor MN3 is connected to the input terminal of the second inverter INV2, a gate of the third NMOS transistor MN3 is connected to the output terminal of the second inverter INV 823672, a drain of the third NMOS transistor MN2 is connected to the fourth NMOS transistor MN2, the source of the fourth NMOS transistor MN4 is grounded. The first schmitt trigger BL1 has a high transition speed, the static power consumption of the first schmitt trigger BL1 is 0W, and the first schmitt trigger BL1 consumes energy when it is in the state of output level transition. The first schmitt trigger BL1 can increase the slope of the pulse signal output from the reset circuit, thereby improving the accuracy of the reset signal.

The principle of the first schmitt trigger BL1 in this embodiment is similar to that of the first schmitt trigger BL1 in the previous embodiment, and those skilled in the art can understand the function and technical effect of the first schmitt trigger BL1 in this embodiment from the structure of the first schmitt trigger BL1 in this embodiment, which is not described herein again.

As shown in fig. 6, in an embodiment, based on the reset circuit of fig. 3, the reset circuit further includes a delay module connected to an output terminal of the reset signal generation module, and the delay module is configured to generate a third pulse signal different from a generation time of the third pulse signal by a first time according to the third pulse signal and generate a fourth pulse signal different from a generation time of the fourth pulse signal by a second time according to the fourth pulse signal. The delay module can reduce the problem of POR signal error turning caused by power supply voltage jitter through a delay effect.

In one embodiment, the delay module may include a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a second resistor R6, a first capacitor C1, a third inverter INV3, a fourth inverter INV4, and a second schmitt trigger BL2, a source of the fourth PMOS transistor MP4 is connected to the power supply, a gate of the fourth PMOS transistor MP4 is connected to an input terminal of the third inverter INV3, a drain of the fourth PMOS transistor MP4 is connected to a source of the fifth PMOS transistor MP5, a drain of the fifth PMOS transistor MP5 is connected to a drain of the sixth NMOS transistor MN6, a drain of the fifth PMOS transistor MP5 is connected to an input terminal of the second schmitt trigger BL2, one end of the second resistor R6 is connected to an output terminal of the third inverter INV 6, the other end of the fifth PMOS transistor MP 6 is connected to a drain of the fifth NMOS transistor MP 6, a gate of the sixth PMOS transistor MN6 is connected to the drain of the sixth NMOS transistor MN6, a gate of the fourth NMOS transistor MN6 is connected to the drain of the fourth NMOS transistor MN6, the gate of the seventh NMOS transistor MN7 is connected to the input of the third inverter INV3, the source of the seventh NMOS transistor MN7 is grounded, one end of the first capacitor C1 is connected to the input of the second schmitt trigger BL2, the other end is grounded, the output of the second schmitt trigger BL2 is connected to the input of the fourth inverter INV4, wherein the input of the third inverter INV3 is the input of the delay module, and the output of the fourth inverter INV4 is the output of the delay module.

When the voltage of the power supply starts to rise from 0V, the third inverter INV3 receives the third pulse signal, the seventh NMOS transistor MN7 is turned off, the voltage at the input terminal of the second schmitt trigger BL2 gradually and slowly rises from 0 by the action of the second resistor R6 and the first capacitor C1, when the voltage at the input terminal of the second schmitt trigger BL2 rises to be greater than the threshold voltage of the second schmitt trigger BL2, the voltage at the output terminal of the second schmitt trigger BL2 quickly rises to the voltage of the power supply, and the fifth PMOS transistor MP5 is turned on, so that the voltage at the input terminal of the second schmitt trigger BL2 is quickly raised, the speed of further raising the voltage at the output terminal of the second schmitt trigger BL2 to the power supply voltage is increased, the output terminal of the delay module outputs the fifth pulse signal, and the fifth pulse signal has a delay time with respect to the third pulse signal.

In the case where the voltage of the power supply is falling, the third inverter INV3 receives the fourth pulse signal, the voltage at the input terminal of the second schmitt trigger BL2 is acted by the second resistor R6 and the first capacitor C1, the voltage at the input terminal of the second schmitt trigger BL2 gradually and slowly decreases from the voltage of the power supply, when the voltage at the input of the second schmitt trigger BL2 drops to the threshold voltage of the second schmitt trigger BL2, the voltage at the output of the second schmitt trigger BL2 drops rapidly, meanwhile, the fifth PMOS transistor MP5 is switched to be in an off state, the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 are in a complete on state, so that the voltage at the input end of the second Schmitt trigger BL2 is further accelerated to drop, and then the voltage at the output end of the second schmitt trigger BL2 is driven to further accelerate and decrease, the output end of the delay module outputs a sixth pulse signal, and the sixth pulse signal is delayed relative to the fourth pulse signal.

It should be noted that, based on the reset circuit shown in fig. 1, the reset circuit further includes a delay module connected to an output end of the reset signal generation module, where the delay module is configured to generate a fifth pulse signal having a first time difference from a generation time of the first pulse signal according to the first pulse signal, and generate a sixth pulse signal having a second time difference from a generation time of the second pulse signal according to the second pulse signal. The delay module can reduce the problem of POR signal error turning caused by power supply voltage jitter through a delay effect.

It should be noted that the structure of the second schmitt trigger BL2 may be the same as that of the first schmitt trigger BL1, or may be different from that of the first schmitt trigger BL1, and the present embodiment is not particularly limited thereto.

As shown in fig. 7, in an embodiment, based on the reset circuit of fig. 6, the reset circuit further includes an amplifying and inverting module INV5 connected to the output terminal of the delay module, and the amplifying and inverting module INV5 is configured to amplify and invert the signal output by the delay module, so that the signal output by the reset circuit meets the requirements of different chips.

As shown in fig. 8, fig. 8 is a schematic diagram of a reset circuit in a second embodiment, the reset circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first voltage dividing unit R1, a second voltage dividing unit R2, a third voltage dividing unit R3, and a fourth voltage dividing unit R4; the grid electrode of the first PMOS tube MP1 is connected with the drain electrode of the second PMOS tube MP2, the source electrode of the first PMOS tube MP1 is connected with the power supply, and the drain electrode of the first PMOS tube MP1 is connected to the ground through the first voltage division unit R1; the gate of the second PMOS transistor MP2 is connected to the drain of the first PMOS transistor MP1, the source of the second PMOS transistor MP2 is connected to the power supply through the second voltage dividing unit R2, the source of the second PMOS transistor MP2 is connected to the drain of the second PMOS transistor MP2 through the third voltage dividing unit R3, and the drain of the second PMOS transistor MP2 is connected to the ground through the fourth voltage dividing unit R4. The reset circuit has the advantages of simple structure and low cost, and can reduce the problem of power-on reset failure when the power supply is electrified for the second time.

In the process that the voltage of the power supply starts to rise from 0V, the voltage of the gate of the first PMOS transistor MP1 gradually increases from 0V, when the voltage of the gate of the first PMOS transistor MP1 is less than the threshold voltage of the first PMOS transistor MP1, the first PMOS transistor MP1 is in an on state, the voltage of the drain of the first PMOS transistor MP1 gradually increases along with the power supply voltage, when the voltage of the gate of the first PMOS transistor MP1 increases to be greater than the threshold voltage of the first PMOS transistor MP1, the first PMOS transistor MP1 is turned off, the voltage of the drain of the first PMOS transistor MP1 gradually decreases, when the voltage of the drain of the first PMOS transistor MP1 decreases to be less than the threshold voltage of the second PMOS transistor MP2, the second PMOS transistor MP2 is turned on, the voltage of the gate of the first PMOS transistor MP1 suddenly increases due to the short circuit of the third voltage dividing unit R3, which can accelerate the voltage drop of the drain of the first PMOS transistor MP1 to 0V, thereby generating a first pulse level that drops from a high level to a low level, the first pulse signal is a power-on reset signal.

When the voltage of the power supply is falling, the voltage of the gate of the first PMOS transistor MP1 is decreased, the voltage of the drain of the first PMOS transistor MP1 is gradually increased, and when the voltage of the drain of the first PMOS transistor MP1 is increased to be greater than the threshold voltage of the second PMOS transistor MP2, the second PMOS transistor MP2 is turned off, since the resistance value when the second PMOS transistor MP2 is in an on state is smaller than the resistance value of the third voltage dividing unit R3, when the second PMOS transistor MP2 is turned off, the total resistance value on the branch forming the second voltage dividing unit R2, the third voltage dividing unit R3, and the fourth voltage dividing unit R4 is increased, the ratio of the resistance value of the fourth voltage dividing unit R4 to the total resistance value on the branch is suddenly decreased, so that the divided voltage of the fourth voltage dividing unit R4 is suddenly decreased, and the voltage of the gate of the first PMOS transistor MP1 is also suddenly decreased, thereby accelerating the increase of the voltage of the drain of the first PMOS transistor MP1 to the voltage of the power supply, thereby generating a second pulse signal rising from a low level to a high level, the second pulse signal being a power-down reset signal.

It should be noted that the first voltage dividing unit R1 and the fourth voltage dividing unit R4 may be NMOS transistors, resistors, or voltage dividing units in which NMOS transistors and resistors are connected in series, and this embodiment is not particularly limited.

The second voltage divider R2 may be a PMOS transistor with a gate and a source connected, may be a resistor, or may be a diode, and is not particularly limited in this embodiment.

It should be noted that the specific specifications of the first PMOS transistor MP1 and the second PMOS transistor MP2 can be set according to actual situations, and the present embodiment does not limit the specifications.

In an embodiment, the reset circuit may further include a delay block connected to an output terminal of the reset signal generation block, and the delay block is configured to generate a fifth pulse signal different from a generation time of the first pulse signal by a first time according to the first pulse signal and to generate a sixth pulse signal different from a generation time of the second pulse signal by a second time according to the second pulse signal. The delay module can reduce the problem of POR signal error turning caused by power supply voltage jitter through a delay effect.

In an embodiment, the second voltage dividing unit is a first NMOS transistor and a first resistor, the first voltage dividing unit is a second NMOS transistor, a source of the first NMOS transistor is grounded, a source of the second NMOS transistor is grounded, a gate of the first NMOS transistor is connected to a gate of the second NMOS transistor, a drain of the first NMOS transistor is connected to a gate of the first NMOS transistor, one end of the first resistor is connected to a drain of the first NMOS transistor, the other end of the first resistor is connected to a gate of the first PMOS transistor, and a drain of the second NMOS transistor is connected to a drain of the first PMOS transistor. The source electrode voltage of the first NMOS tube can control the voltage of the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube, so that the resistance values of the first PMOS tube and the second NMOS tube in a conducting state can be controlled, the control capability of the reset circuit is improved, the reset circuit has the advantages of being simple in structure and low in cost, and the problem of power-on reset failure during secondary power-on of a power supply can be reduced.

In an embodiment, the reset signal generating module further includes a schmitt trigger, a drain of the first PMOS transistor is connected to an input terminal of the schmitt trigger, and a gate of the second PMOS transistor is connected to an output terminal of the schmitt trigger. For example, in the power-on process, the schmitt trigger can generate a third pulse signal according to a first pulse signal generated by the source electrode of the first PMOS transistor received by the input end, the slope of the third pulse signal is larger than that of the first pulse signal, namely, the voltage of the third pulse signal can be reduced to 0V faster than that of the first pulse signal, the accuracy of the reset signal can be improved, the reset circuit has the advantages of simple structure and low cost, and the problem of power-on reset failure when the power supply is powered on for the second time can be reduced.

It should be noted that the structure of the schmitt trigger is the same as that of the schmitt trigger in the first embodiment of the reset circuit, and details thereof are not repeated in this embodiment.

In an embodiment, the reset circuit is provided with a schmitt trigger, and the reset circuit further includes a delay module connected to an output end of the reset signal generation module, wherein the delay module is configured to generate a third pulse signal different from a generation time of the third pulse signal by a first time according to the third pulse signal, and generate a fourth pulse signal different from a generation time of the fourth pulse signal by a second time according to the fourth pulse signal. The delay module can reduce the problem of POR signal error turning caused by power supply voltage jitter through a delay effect.

It should be noted that the positions of the NMOS transistor and the PMOS transistor in the delay module are replaced with each other on the basis of the structure of the delay module in the first embodiment of the reset circuit, and the delay module of this embodiment can achieve the same function as the delay module in the first embodiment of the reset circuit, and details thereof are not repeated in this embodiment.

In an embodiment, the reset circuit further includes an amplifying and inverting module connected to the output end of the delay module, the amplifying and inverting module is configured to perform amplifying processing and inverting processing on the signal output by the delay module, and the amplifying and inverting module is configured to perform amplifying processing and inverting processing on the signal output by the delay module, so that the signal output by the reset circuit meets the requirements of different chips.

In addition, an embodiment of the present invention further provides a circuit board, where the circuit board may include the reset circuit in the first embodiment, and may also include the reset circuit in the second embodiment. For example, the circuit board includes the reset circuit in the first embodiment, the reset circuit includes a reset signal generation module, and the reset signal generation module includes a first NMOS transistor, a second NMOS transistor, a first voltage division unit, a second voltage division unit, a third voltage division unit, and a fourth voltage division unit; the drain electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, the grid electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected to a power supply through a first voltage division unit; the drain electrode of the second NMOS tube is connected to a power supply through a second voltage division unit, the drain electrode of the second NMOS tube is connected to the source electrode of the second NMOS tube through a third voltage division unit, and the source electrode of the second NMOS tube is connected to the ground through a fourth voltage division unit; under the condition that the voltage of a power supply is increased, the voltage value of the grid electrode of the second NMOS tube is smaller than the threshold voltage value, the second NMOS tube is cut off to enable the first NMOS tube to be conducted, and the drain electrode of the first NMOS tube generates a first pulse signal which is reduced from a high level to a low level; under the condition that the voltage of the power supply is reduced, the voltage value of the grid electrode of the second NMOS tube is larger than the threshold voltage value, the second NMOS tube is conducted to cut off the first NMOS tube, and the drain electrode of the first NMOS tube generates a second pulse signal which is increased from a low level to a high level. The reset circuit in the circuit board has the advantages of simple structure and low cost, and can reduce the problem of power-on reset failure when the power supply is electrified for the second time.

In addition, an embodiment of the present invention further provides a reset device, which includes a circuit board, and the circuit board may include the reset circuit in the first embodiment, and may also include the reset circuit in the second embodiment. For example, the reset device includes a circuit board, the circuit board includes the reset circuit in the first embodiment, the reset circuit includes a reset signal generation module, the reset signal generation module includes a first NMOS transistor, a second NMOS transistor, a first voltage division unit, a second voltage division unit, a third voltage division unit, and a fourth voltage division unit; the drain electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, the grid electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected to a power supply through a first voltage division unit; the drain electrode of the second NMOS tube is connected to a power supply through a second voltage division unit, the drain electrode of the second NMOS tube is connected to the source electrode of the second NMOS tube through a third voltage division unit, and the source electrode of the second NMOS tube is connected to the ground through a fourth voltage division unit; under the condition that the voltage of a power supply is increased, the voltage value of the grid electrode of the second NMOS tube is smaller than the threshold voltage value, the second NMOS tube is cut off to enable the first NMOS tube to be conducted, and the drain electrode of the first NMOS tube generates a first pulse signal which is reduced from a high level to a low level; under the condition that the voltage of the power supply is reduced, the voltage value of the grid electrode of the second NMOS tube is larger than the threshold voltage value, the second NMOS tube is conducted to cut off the first NMOS tube, and the drain electrode of the first NMOS tube generates a second pulse signal which is increased from a low level to a high level. The reset circuit in the circuit board has the advantages of simple structure and low cost, and can reduce the problem of power-on reset failure when the power supply is electrified for the second time.

While the preferred embodiments of the present invention have been described in detail, it will be understood by those skilled in the art that the foregoing and various other changes, omissions and deviations in the form and detail thereof may be made without departing from the scope of this invention.

Claims

1. A reset circuit, characterized in that, comprising: a reset signal generation module, the reset signal generation module comprises a first NMOS tube, a second NMOS tube, a first voltage divider unit, a second voltage divider unit, a third voltage divider pressure unit and a fourth voltage dividing unit;

The drain of the first NMOS transistor is connected to the gate of the second NMOS transistor, the gate of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the source of the first NMOS transistor The electrode is grounded, and the drain of the first NMOS transistor is connected to the power supply through the first voltage dividing unit;

The drain of the second NMOS transistor is connected to the power supply through the second voltage dividing unit, and the drain of the second NMOS transistor is connected to the source of the second NMOS transistor through the third voltage dividing unit electrode, the source electrode of the second NMOS transistor is connected to the ground through the fourth voltage dividing unit.

2 . The reset circuit according to claim 1 , wherein the second voltage dividing unit is a first PMOS transistor and a first resistor, the first voltage dividing unit is a second PMOS transistor, and the first voltage dividing unit is a second PMOS transistor. 3 . The source of the PMOS transistor is connected to the power supply, the source of the second PMOS transistor is connected to the power supply, the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, and the first PMOS transistor is connected to the gate of the second PMOS transistor. The drain of a PMOS transistor is connected to the gate of the first PMOS transistor, one end of the first resistor is connected to the drain of the first PMOS transistor, and the other end is connected to the gate of the first NMOS transistor , the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor.

3 . The reset circuit according to claim 1 , wherein the reset signal generating module further comprises a Schmitt trigger, the drain of the first NMOS transistor and the input end of the Schmitt trigger connected, the gate of the second NMOS transistor is connected to the output end of the Schmitt trigger.

4. The reset circuit according to any one of claims 1 to 3, further comprising a delay module connected to an output end of the reset signal generating module, the delay module being configured to generate the reset signal according to the reset signal The first signal output by the module generates a second signal delayed by a first time from the pulse signal output by the reset signal generating module.

5 . The reset circuit according to claim 4 , further comprising an amplifying and inverting module connected to the output end of the delay module, and the amplifying and inverting module is used to perform a signal output from the delay module. 6 . Amplification and inversion.

6. A reset circuit, characterized in that it comprises: a reset signal generation module, the reset signal generation module comprises a first PMOS tube, a second PMOS tube, a first voltage dividing unit, a second voltage dividing unit, a third dividing unit. pressure unit and a fourth voltage dividing unit;

The gate of the first PMOS transistor is connected to the drain of the second PMOS transistor, the source of the first PMOS transistor is connected to the power supply, and the drain of the first PMOS transistor is connected by the first voltage divider unit is connected to ground;

The gate of the second PMOS transistor is connected to the drain of the first PMOS transistor, the source of the second PMOS transistor is connected to the power supply through the second voltage dividing unit, and the second PMOS transistor The source of the PMOS is connected to the drain of the second PMOS transistor through the third voltage dividing unit, and the drain of the second PMOS transistor is connected to the ground through the fourth voltage dividing unit.

7 . The reset circuit according to claim 6 , wherein the second voltage dividing unit is a first NMOS transistor and a first resistor, the first voltage dividing unit is a second NMOS transistor, and the first voltage dividing unit is a second NMOS transistor. 8 . The source of the NMOS transistor is grounded, the source of the second NMOS transistor is grounded, the gate of the first NMOS transistor is connected to the gate of the second NMOS transistor, and the drain of the first NMOS transistor is connected to the gate of the second NMOS transistor. The gate of the first NMOS transistor is connected, one end of the first resistor is connected to the drain of the first NMOS transistor, and the other end is connected to the gate of the first PMOS transistor. The drain is connected to the drain of the first PMOS transistor.

8 . The reset circuit according to claim 6 , wherein the reset signal generating module further comprises a Schmitt trigger, the drain of the first PMOS transistor and the input end of the Schmitt trigger connected, the gate of the second PMOS transistor is connected to the output end of the Schmitt trigger.

9 . The reset circuit according to claim 6 , further comprising a delay module connected to an output end of the reset signal generating module, the delay module being configured to generate the reset signal according to the reset signal. 10 . The first signal output by the module generates a second signal delayed by a first time from the pulse signal output by the reset signal generating module.

10 . The reset circuit according to claim 9 , further comprising an amplifying and inverting module connected to the output end of the delay module, and the amplifying and inverting module is used to perform a signal output from the delay module. 11 . Amplification and inversion.

11 . A circuit board, characterized by comprising the reset circuit of any one of claims 1 to 5 , or the reset circuit of any one of claims 6 to 10 .

12. A reset device, comprising the circuit board of claim 11.