CN115037254B - Image signal transmission device and signal output circuit - Google Patents
Image signal transmission device and signal output circuitInfo
- Publication number
- CN115037254B CN115037254B CN202110233979.7A CN202110233979A CN115037254B CN 115037254 B CN115037254 B CN 115037254B CN 202110233979 A CN202110233979 A CN 202110233979A CN 115037254 B CN115037254 B CN 115037254B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
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Abstract
本申请公开一种影像信号传送装置及其具有直流增益维持机制的信号输出电路，应用于影像信号传送装置中，包括：前级驱动电路以及后级驱动电路。前级驱动电路包括具有可变电容的连续时间线性均衡器，并配置以接收数字输入信号进行高频强化，以提升数字输入信号的带宽，进而产生前级输出信号。后级驱动电路包括不具有可变电容的连续时间线性均衡器，并配置以对前级输出信号进行直流增益提升，以对前级输出信号相对数字输入信号的直流增益下降进行补偿，进一步产生后级输出信号至影像信号接收装置中。
The present application discloses an image signal transmission device and a signal output circuit having a DC gain maintenance mechanism, which are applied to the image signal transmission device and include: a pre-stage driving circuit and a post-stage driving circuit. The pre-stage driving circuit includes a continuous-time linear equalizer with a variable capacitor, and is configured to receive a digital input signal and perform high-frequency enhancement to increase the bandwidth of the digital input signal, thereby generating a pre-stage output signal. The post-stage driving circuit includes a continuous-time linear equalizer without a variable capacitor, and is configured to perform a DC gain boost on the pre-stage output signal to compensate for the decrease in the DC gain of the pre-stage output signal relative to the digital input signal, thereby further generating a post-stage output signal to the image signal receiving device.
Description
Technical Field
The present invention relates to a signal output technology, and more particularly, to a video signal transmission device and a signal output circuit thereof having a dc gain maintaining mechanism.
Background
The high-definition multimedia interface (high definition multimedia interface; HDMI) is a fully digital video and audio transmission interface capable of transmitting uncompressed audio and video signals. Because the same wire can be adopted to transmit audio signals and video signals simultaneously, the transmission technology of the high-image-quality multimedia interface greatly simplifies the installation difficulty of the system circuit.
The system adopting the transmission technology comprises a source end for transmitting the video-audio signal and a receiving end for receiving the video-audio signal. The source end needs to rely on the setting of the signal output circuit to properly adjust the video and audio signals so that the receiving end receives the high-quality video and audio signals. However, the signal output circuit tends to sacrifice the performance of the dc gain in order to increase the ac gain.
Disclosure of Invention
In view of the above problems, an objective of the present invention is to provide an image signal transmission device and a signal output circuit with a dc gain maintaining mechanism thereof, so as to improve the prior art.
The invention comprises a signal output circuit with a direct current gain maintaining mechanism, which is applied to an image signal transmission device (TX) and comprises a front-stage driving circuit and a rear-stage driving circuit. The pre-stage driving circuit comprises a Continuous Time Linear Equalizer (CTLE) with a variable capacitor, and is configured to receive a digital input signal for high-frequency enhancement so as to increase the bandwidth of the digital input signal and generate a pre-stage output signal. The post-stage driving circuit comprises a continuous time linear equalizer without a variable capacitor and is configured to perform DC gain boosting on the pre-stage output signal so as to compensate the DC gain reduction of the pre-stage output signal relative to the digital input signal, and further generate the post-stage output signal to the image signal receiving device (RX).
The invention also comprises a video signal transmission device which is applied to a video signal transmission system and comprises a digital signal processing circuit and a signal output circuit. The digital signal processing circuit is configured to generate a digital input signal. The signal output circuit comprises a front-stage driving circuit and a rear-stage driving circuit. The pre-stage driving circuit comprises a continuous time linear equalizer and is configured to receive a digital input signal for high-frequency enhancement so as to improve the bandwidth of the digital input signal and further generate a pre-stage output signal. The post-stage driving circuit comprises a continuous time linear equalizer without a variable capacitor and is configured to perform DC gain boost on the pre-stage output signal so as to compensate the DC gain drop of the pre-stage output signal relative to the digital input signal, and further generate the post-stage output signal to the image signal receiving device.
The features, implementation and effects of the present application are described in detail below with reference to the preferred embodiments of the present application in conjunction with the accompanying drawings.
Drawings
FIG. 1 is a block diagram of an image signal transmission system according to an embodiment of the present invention, and
FIG. 2 shows a circuit diagram of a pre-stage driving circuit according to an embodiment of the invention;
FIG. 3 is a schematic diagram showing the frequency response of the front stage driving circuit according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a post-stage driving circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram showing the frequency response of the rear stage driving circuit according to an embodiment of the present invention, and
Fig. 6 is a schematic diagram showing a frequency response of the digital input signal after being processed by the front stage driving circuit and the rear stage driving circuit to output the rear stage output signal according to an embodiment of the present invention.
[ Symbolic description ]
100 Video signal transmission system
110 Video signal transmitting device
120 Video signal receiving device
130 Digital signal processing circuit
140 Signal output circuit
150 Pre-stage driving circuit
160 Post-stage drive circuit
C1, C2 load capacitance
C3 variable capacitance
Cd. Cs capacitance value
GND ground terminal
I1, I2 current sources
MN1, MN2 input transistors
O1, O2 output end
Vip, vin digital input signal
Vop1, von1, pre-stage output signal
Vop2, von2, post-stage output signal
R1, R2 load resistor
R3 variable resistor
Rd, rs resistance value
Omega P1、ωP2 pole
Omega Z zero point
Detailed Description
One objective of the present invention is to provide an image signal transmission device and a signal output circuit with a dc gain maintaining mechanism thereof, which can increase the dc gain by setting the rear driving circuit to compensate the dc gain decrease caused by the front driving circuit, and increase the bandwidth of the output signal without losing the dc gain.
Please refer to fig. 1. Fig. 1 shows a block diagram of an image signal transmission system 100 according to an embodiment of the invention. The video signal transmission system 100 includes a video signal transmitting apparatus (TX) 110 and a video signal receiving apparatus (RX) 120.
In one embodiment, the image signal transmission system 100 is a system for transmitting images and sounds according to a high-quality multimedia interface. The video signal transmitting apparatus 110 is a source, such as but not limited to a set top box, a DVD player, a computer, etc. The image signal receiving apparatus 120 is a sink (sink), such as but not limited to a television, a projector, or other display device. The video signal transmitting device 110 is configured to process the video signal and transmit the processed video signal to the video signal receiving device 120 for playing.
The video signal transmitting apparatus 110 includes a digital signal processing circuit 130 and a signal output circuit 140.
The digital signal processing circuit 130 is configured to generate digital input signals Vip, vin in differential (differential) form. The signal output circuit 140 has a dc gain maintaining mechanism to strengthen the output of the digital input signals Vip and Vin. The signal output circuit 140 includes a front stage driving circuit 150 and a rear stage driving circuit 160.
The pre-stage driving circuit 150 is configured to receive the digital input signals Vip and Vin for high-frequency enhancement, so as to boost the bandwidths of the digital input signals Vip and Vin, and further generate the pre-stage output signals Vop1 and Von1. The pre-stage output signals Vop1 and Von1 are also differential signals.
Please refer to fig. 2. Fig. 2 shows a circuit diagram of the front-stage driving circuit 150 according to an embodiment of the invention. In one embodiment, the pre-stage driver circuit 150 comprises a continuous time linear equalizer with variable capacitance. In more detail, the continuous-time linear equalizer includes two input transistors MN1, MN2, two load resistors R1, R2, two load capacitors C1, C2, a variable resistor R3, a variable capacitor C3, and two current sources I1, I2.
Each of the input transistors MN1, MN2 includes a gate, a drain and a source. The gate of the input transistor MN1 is configured to receive the digital input signal Vip. The gate of the input transistor MN2 is configured to receive the digital input signal Vin. The drain of the input transistor MN1 is electrically coupled to the output terminal O1, and the drain of the input transistor MN2 is electrically coupled to the output terminal O2.
The drain of the input transistor MN1 is configured to generate the pre-stage output signal Vop1 to the output terminal O1, and the drain of the input transistor MN2 is configured to generate the pre-stage output signal Von1 to the output terminal O2.
The load resistor R1 is electrically coupled between the drain of the input transistor MN1 and the operating voltage source VDD. The load resistor R2 is electrically coupled between the drain of the input transistor MN2 and the operating voltage source VDD. The load capacitor C1 is electrically coupled between the drain of the input transistor MN1 and the operating voltage source VDD. The load capacitor C2 is electrically coupled between the drain of the input transistor MN2 and the operating voltage source VDD.
The variable resistor R3 and the variable capacitor C3 are electrically connected in parallel between the sources of the input transistors MN1 and MN 2. The current source I1 is electrically coupled between the source of the input transistor MN1 and the ground GND. The current source I2 is electrically coupled between the source of the input transistor MN2 and the ground GND.
In one embodiment, the zero and two polarities of the frequency response of the pre-driver circuit 150 are determined by a plurality of circuit parameter values of the pre-driver circuit 150.
Please refer to fig. 3 at the same time. Fig. 3 shows a schematic diagram of the frequency response of the front-end driving circuit 150 according to an embodiment of the invention. Wherein the horizontal axis is frequency and the vertical axis is gain. In this embodiment, the gain magnitude corresponding to the horizontal axis is the original gain magnitude of the digital input signals Vip and Vin.
In one embodiment, the circuit parameters of the front stage driving circuit 150 include the transconductance of the transistor, the resistance of each resistor, and the capacitance of each capacitor. For example, the transconductance (transconductance) of the input transistors MN1, MN2 is gm, the resistance of each load resistor R1, R2 is Rd, the capacitance of each load capacitor C1, C2 is Cd, the resistance of the variable resistor is 2Rs, and the capacitance of the variable capacitor is Cs.
Thus, with respect to the frequency response of the front-stage driving circuit 150, the conversion function H(s) that converts the digital input signals Vip, vin into the front-stage output signals Vop1, von1 can be expressed as follows:
H(s)=(gmRd)(1+sRsCs)/(1+sRcCs+gmRs)(1+sRdCd))
the dc gain of the front-stage driving circuit 150 can be expressed as follows:
(gmRd)/(1+(gmRs))
The zero ω Z on the frequency response can be expressed as:
ωZ=1/(RsCs)
One of the poles ω P1 may be expressed as:
ωP1=(1+gmRs)/(RsCs)
The other pole ω P2 can be expressed as:
ωP2=1/(RdCd)
Therefore, by adjusting the above circuit parameters, the zero and two poles of the frequency response of the front driving circuit 150 can be changed accordingly, so as to improve the dc gain and the high frequency part to different degrees.
It should be noted that, after the processing of the pre-driver circuit 150, the dc gain of the pre-driver output signals Vop1 and Von1 is reduced relative to the dc gain of the digital input signals Vip and Vin.
The post-stage driving circuit 160 is configured to receive the pre-stage output signals Vop1 and Von1 for dc gain boosting, to compensate for the dc gain drop of the pre-stage output signals Vop1 and Von1 relative to the digital input signals Vip and Vin, and to further generate the post-stage output signals Vop2 and Von2 to the image signal receiving device 120. The post-stage output signals Vop2 and Von2 are also differential signals.
Please refer to fig. 4. Fig. 4 shows a circuit diagram of the rear driving circuit 160 according to an embodiment of the invention. In one embodiment, the post driver circuit 160 comprises a continuous time linear equalizer without a variable capacitance. In more detail, the continuous-time linear equalizer includes two input transistors MN1, MN2, two load resistors R1, R2, two load capacitors C1, C2, a variable resistor R3, and two current sources I1, I2. It should be noted that, because the rear driving circuit 160 is similar to the front driving circuit 150 in terms of structure, corresponding components are not additionally provided with new reference numerals.
The connection and operation of the other components of the rear driving circuit 160 are different from those of the front driving circuit 150 except for the variable capacitance, and thus the description thereof will not be repeated. In the present embodiment, the gate of the input transistor MN1 of the post driver 160 is configured to receive the pre output signal Vop1. The gate of the input transistor MN2 is configured to receive the pre-stage output signal Von1. And, the drain of the input transistor MN1 is configured to generate the post output signal Vop2 to the output terminal O1, and the drain of the input transistor MN2 is configured to generate the post output signal Von2 to the output terminal O2.
In one embodiment, the frequency response of the post driver 160 will include only a single pole, and the pole is determined by a plurality of circuit parameter values of the post driver 160.
Please refer to fig. 5 at the same time. Fig. 5 shows a schematic diagram of the frequency response of the back-end driving circuit 160 according to an embodiment of the invention. Wherein the horizontal axis is frequency and the vertical axis is gain. In this embodiment, the gain size corresponding to the horizontal axis is the original gain size of the front-stage output signals Vop1 and Von 1.
Similar to the front stage driving circuit 150, the circuit parameters of the rear stage driving circuit 160 include the transconductance of the transistor, the resistance value of each resistor, and the capacitance value of each capacitor, however, these circuit parameters have differences from those of the front stage driving circuit 150. More specifically, the transconductance of the input transistors MN1 and MN2 is gm, the resistance of the load resistors R1 and R2 is Rs, the capacitance of the load capacitors C1 and C2 is Cd, and the resistance of the variable resistor is 2Rd.
Therefore, regarding the frequency response of the post-stage driving circuit 160, the conversion function formula H(s) that converts the pre-stage output signals Vop1, von1 into the post-stage output signals Vop2, von2 can be expressed as follows:
H(s)=(gmRs)/(1+gmRd)(1+sRsCd)
The dc gain of the rear drive circuit 160 can be expressed as follows:
(gmRs)/(1+(gmRd))
The single pole ω P2 can be expressed as:
ωP2=1/(RsCd)
It should be noted that, after the processing of the post-stage driving circuit 160, the dc gains of the post-stage output signals Vop2 and Von2 are increased relative to the dc gains of the pre-stage output signals Vop1 and Von 1.
Please refer to fig. 6. Fig. 6 shows a schematic diagram of the frequency response of the output signals Vop2 and Von2 of the subsequent stage after the digital input signals Vip and Vin are processed by the previous stage driving circuit 150 and the subsequent stage driving circuit 160 according to an embodiment of the present invention. In more detail, the waveforms of fig. 6 correspond to the result of superimposing the waveforms of fig. 3 and 5.
Since the dc gain of the front-stage driving circuit 150 is (gmRd)/(1+ (gmRs)), and the dc gain of the rear-stage driving circuit 160 is (gmRs)/(1+ (gmRd)), the dc gain of the rear-stage output signals Vop2, von2 relative to the digital input signals Vip, vin can be expressed as follows:
((gmRd)(gmRs))/((1+(gmRs))(1+(gmRd)))
In one embodiment, when the product of the transconductance and the resistance of the load resistor (i.e., gmRd and gmRs) of the front-stage driving circuit 150 and the rear-stage driving circuit 160 is substantially greater than 1, the dc gains generated by the front-stage driving circuit 150 and the rear-stage driving circuit 160 cancel each other. In more detail, in this case, the dc gain of the post-stage output signals Vop2, von2 with respect to the digital input signals Vip, vin is 1.
When the signal output circuit is processed by the front-stage driving circuit, the effect of amplifying the alternating-current gain and increasing the bandwidth can be achieved, but the direct-current gain is reduced. Therefore, the signal output circuit can improve the DC gain by the setting of the rear-stage driving circuit so as to compensate the DC gain reduction caused by the front-stage driving circuit and improve the bandwidth of the output signal under the condition of not losing the DC gain.
It should be noted that the above embodiment is only an example. In other embodiments, those skilled in the art will appreciate that modifications may be made without departing from the spirit of the invention.
In summary, the image signal transmitting device and the signal output circuit with the dc gain maintaining mechanism of the present invention can increase the dc gain by the setting of the rear driving circuit to compensate the dc gain decrease caused by the front driving circuit, and increase the bandwidth of the output signal without losing the dc gain.
Although the embodiments of the present application have been described above, the present application is not limited thereto, and those skilled in the art can make various changes to the technical features of the present application according to the explicit or implicit disclosure of the present application, and all such changes may be made within the scope of the present application, that is, the scope of the present application is defined by the claims of the present application.
Claims (7)
1. A signal output circuit with a DC gain maintaining mechanism is applied to an image signal transmission device, and is characterized by comprising:
A front-end driving circuit including a continuous time linear equalizer with a variable capacitor and configured to receive a digital input signal for high frequency enhancement to increase a bandwidth of the digital input signal and generate a front-end output signal, and
A post-stage driving circuit including the continuous time linear equalizer without the variable capacitor and configured to perform a dc gain boost on the pre-stage output signal to compensate a dc gain drop of the pre-stage output signal with respect to the digital input signal, and further generate a post-stage output signal into an image signal receiving device;
Wherein, this preceding stage drive circuit includes:
two input transistors, each comprising:
A gate configured to receive the digital input signal;
A drain electrically coupled to an output terminal and configured to generate the pre-stage output signal to the output terminal, and
A source electrode;
two load resistors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source;
Two load capacitors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source;
a variable resistor and a variable capacitor electrically connected in parallel between the sources of the two input transistors, and
Two current sources, each of which is electrically coupled between the source of one of the two input transistors and the ground;
Wherein, this rear stage drive circuit includes:
two input transistors, each comprising:
A gate configured to receive the pre-stage output signal;
A drain electrically coupled to an output terminal and configured to generate the post output signal to the output terminal, and
A source electrode;
two load resistors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source;
Two load capacitors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source;
a variable resistor electrically connected in parallel between the sources of the two input transistors, and
Two current sources, each of which is electrically coupled between the source of one of the two input transistors and the ground;
Wherein, a zero point and two poles of the frequency response of the pre-stage driving circuit are determined by a plurality of circuit parameter values of the pre-stage driving circuit, and the plurality of circuit parameters comprise a resistance value Rd of each of the two load resistors, a capacitance value Cd of each of the two load capacitors, a resistance value 2Rs of the variable resistor and a capacitance value Cs of the variable capacitor;
Wherein one transconductance of the two input transistors is gm, the zero point is 1/(RsCs), the two polar points are (1+gmrs)/(RsCs) and 1/(RdCd), respectively, a conversion function between the digital input signal and the front-stage output signal is (gmRd) (1+srscs)/(1+srccs+gmrs) (1+srdcd)), and a dc gain of the front-stage driving circuit is (gmRd)/(1+ (gmRs)).
2. The signal output circuit of claim 1 wherein the digital input signal, the pre-stage output signal and the post-stage output signal are each a differential signal.
3. The signal output circuit of claim 1 wherein the pre-driver circuit receives the digital input signal from a digital signal processing circuit included in the video signal transmission device.
4. The signal output circuit according to claim 1, wherein a pole of the frequency response of the post driver circuit is determined by a plurality of circuit parameter values of the post driver circuit, the plurality of circuit parameters including a resistance value Rs of each of the two load resistors, a capacitance value Cd of each of the two load capacitors, and a resistance value 2Rd of the variable resistor;
Wherein one of the two input transistors has a transconductance of gm, the pole is 1/(RsCd), a transfer function between the digital input signal and the front-stage output signal is gmRs)/(1+gmRd (1+sRsCd), and a DC gain of the rear-stage driving circuit is (gmRs)/(1+ (gmRd)).
5. The signal output circuit according to claim 1, wherein a dc gain of each of the front-stage driving circuits and the rear-stage driving circuits is offset when a product of resistance values of each corresponding one of the transconductors and one of the load resistors is substantially greater than 1.
6. An image signal transmission device is applied to an image signal transmission system, and comprises:
A digital signal processing circuit configured to generate a digital input signal, and
A signal output circuit, comprising:
A front-end driving circuit including a continuous time linear equalizer with a variable capacitor and configured to receive a digital input signal for high frequency enhancement to increase a bandwidth of the digital input signal and generate a front-end output signal, and
A post-stage driving circuit including the continuous time linear equalizer without the variable capacitor and configured to perform a dc gain boost on the pre-stage output signal to compensate a dc gain drop of the pre-stage output signal with respect to the digital input signal, and further generate a post-stage output signal into an image signal receiving device;
Wherein, this preceding stage drive circuit includes:
two input transistors, each comprising:
A gate configured to receive the digital input signal;
A drain electrically coupled to an output terminal and configured to generate the pre-stage output signal to the output terminal, and
A source electrode;
two load resistors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source;
Two load capacitors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source;
a variable resistor and a variable capacitor electrically connected in parallel between the sources of the two input transistors, and
Two current sources, each of which is electrically coupled between the source of one of the two input transistors and the ground;
Wherein, this rear stage drive circuit includes:
two input transistors, each comprising:
A gate configured to receive the pre-stage output signal;
A drain electrically coupled to an output terminal and configured to generate the post output signal to the output terminal, and
A source electrode;
two load resistors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source;
Two load capacitors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source;
a variable resistor electrically connected in parallel between the sources of the two input transistors, and
Two current sources, each of which is electrically coupled between the source of one of the two input transistors and the ground;
Wherein, a zero point and two poles of the frequency response of the pre-stage driving circuit are determined by a plurality of circuit parameter values of the pre-stage driving circuit, and the plurality of circuit parameters comprise a resistance value Rd of each of the two load resistors, a capacitance value Cd of each of the two load capacitors, a resistance value 2Rs of the variable resistor and a capacitance value Cs of the variable capacitor;
Wherein one transconductance of the two input transistors is gm, the zero point is 1/(RsCs), the two polar points are (1+gmrs)/(RsCs) and 1/(RdCd), respectively, a conversion function between the digital input signal and the front-stage output signal is (gmRd) (1+srscs)/(1+srccs+gmrs) (1+srdcd)), and a dc gain of the front-stage driving circuit is (gmRd)/(1+ (gmRs)).
7. The video signal transmission device according to claim 6, wherein a dc gain of each of the front-stage driving circuits and the rear-stage driving circuits is offset when a product of resistance values of a corresponding transconductance and a load resistance is substantially greater than 1.
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| CN202110233979.7A CN115037254B (en) | 2021-03-03 | 2021-03-03 | Image signal transmission device and signal output circuit |
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| CN202110233979.7A CN115037254B (en) | 2021-03-03 | 2021-03-03 | Image signal transmission device and signal output circuit |
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| CN102801666B (en) * | 2011-05-23 | 2015-09-02 | 联咏科技股份有限公司 | Equalizer and communication system |
| US9484888B2 (en) * | 2012-12-19 | 2016-11-01 | Intel Corporation | Linear resistor with high resolution and bandwidth |
| US9806915B1 (en) * | 2016-06-27 | 2017-10-31 | Xilinx, Inc. | Circuit for and method of receiving an input signal |
| CN106209709B (en) * | 2016-07-15 | 2019-03-19 | 中国电子科技集团公司第五十八研究所 | A kind of linear equalizer suitable for HSSI High-Speed Serial Interface |
| CN109450471A (en) * | 2018-10-15 | 2019-03-08 | 上海兆芯集成电路有限公司 | Acceptor circuit and the method for increasing bandwidth |
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