CN115037254A - Image signal transmission device and signal output circuit with direct current gain maintaining mechanism thereof - Google Patents

Abstract

The application discloses an image signal transmission device and signal output circuit with DC gain maintaining mechanism, applied in the image signal transmission device, including: a front stage driving circuit and a rear stage driving circuit. The pre-stage driving circuit comprises a continuous time linear equalizer with a variable capacitor and is configured to receive a digital input signal to perform high frequency enhancement so as to improve the bandwidth of the digital input signal and further generate a pre-stage output signal. The rear stage driving circuit comprises a continuous time linear equalizer without a variable capacitor, and is configured to perform direct current gain boost on the front stage output signal, compensate for direct current gain reduction of the front stage output signal relative to the digital input signal, and further generate a rear stage output signal to the image signal receiving device.

Description

Image signal transmission device and signal output with DC gain maintaining mechanism circuit

technical field

The present invention relates to a signal output technology, in particular to an image signal transmission device and a signal output circuit with a DC gain maintaining mechanism.

Background technique

High definition multimedia interface (high definition multimedia interface; HDMI) is a fully digital image and sound transmission interface that can transmit uncompressed audio and video signals. Since the same wire can be used to transmit audio and video signals at the same time, the transmission technology of the high-quality multimedia interface greatly simplifies the installation difficulty of the system line.

A system using this transmission technology includes a source end for transmitting video and audio signals and a receiver end for receiving video and audio signals. The source end needs to make appropriate adjustments to the audio and video signals depending on the settings of the signal output circuit, so that the receiver end can receive high-quality audio and video signals. However, signal output circuits often sacrifice the performance of DC gain in order to increase AC gain.

SUMMARY OF THE INVENTION

In view of the problems in the prior art, an object of the present invention is to provide an image signal transmission device and a signal output circuit with a DC gain maintaining mechanism to improve the prior art.

The present invention includes a signal output circuit with a DC gain maintaining mechanism, which is applied to an image signal transmission device (TX) and includes a pre-stage driving circuit and a post-stage driving circuit. The pre-stage driving circuit includes a continuous time linear equalizer (CTLE) with variable capacitance, and is configured to receive a digital input signal for high frequency enhancement, so as to increase the bandwidth of the digital input signal, and then generate a pre-stage output signal . The post-stage driving circuit includes a continuous-time linear equalizer without variable capacitance, and is configured to boost the DC gain of the pre-stage output signal, so as to compensate the DC gain drop of the pre-stage output signal relative to the digital input signal, and further generate the post-stage output signal. The stage outputs the signal to the video signal receiving device (RX).

The present invention further includes an image signal transmission device, which is applied in an image signal transmission system, comprising: a digital signal processing circuit and a signal output circuit. A digital signal processing circuit is configured to generate a digital input signal. The signal output circuit includes: a pre-stage driving circuit and a post-stage driving circuit. The pre-stage driving circuit includes a continuous-time linear equalizer, and is configured to receive the digital input signal for high-frequency enhancement, so as to increase the bandwidth of the digital input signal, thereby generating the pre-stage output signal. The post-stage driving circuit includes a continuous-time linear equalizer without variable capacitance, and is configured to boost the DC gain of the pre-stage output signal, so as to compensate the DC gain drop of the pre-stage output signal relative to the digital input signal, and further generate the post-stage output signal. The stage output signal is sent to the image signal receiving device.

Regarding the features, implementations and effects of the present application, preferred embodiments are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

FIG. 1 shows a block diagram of an image signal transmission system according to an embodiment of the present invention; and

FIG. 2 shows a circuit diagram of a pre-driver circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram showing the frequency response of the front-stage driving circuit according to an embodiment of the present invention;

FIG. 4 shows a circuit diagram of a post-stage driving circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram showing the frequency response of the post-stage driving circuit according to an embodiment of the present invention; and

FIG. 6 is a schematic diagram showing the frequency response of the output signal of the post-stage output after the digital input signal is processed by the pre-stage driving circuit and the post-stage driving circuit according to an embodiment of the present invention.

【Symbol Description】

100: Video signal transmission system

110: Video signal transmission device

120: Video signal receiving device

130: Digital signal processing circuit

140: Signal output circuit

150: Pre-drive circuit

160: Post-stage driver circuit

C1, C2: load capacitance

C3: Variable Capacitor

Cd, Cs: Capacitance value

GND: ground terminal

I1, I2: current source

MN1, MN2: input transistors

O1, O2: output terminal

Vip, Vin: digital input signal

Vop1, Von1: Pre-stage output signal

Vop2, Von2: Post-stage output signal

R1, R2: load resistance

R3: variable resistor

Rd, Rs: resistance value

ω _P1 , ω _P2 : poles

ω _Z : zero point

Detailed ways

An object of the present invention is to provide an image signal transmission device and a signal output circuit with a DC gain maintaining mechanism. The DC gain is increased by the setting of the post-stage driving circuit to compensate for the decrease in the DC gain caused by the pre-stage driving circuit. Increase the bandwidth of the output signal without losing DC gain.

Please refer to Figure 1. FIG. 1 shows a block diagram of an image signal transmission system 100 according to an embodiment of the present invention. The video signal transmission system 100 includes a video signal transmission device (TX) 110 and a video signal reception device (RX) 120 .

In one embodiment, the video signal transmission system 100 is a system for transmitting video and audio according to a high-definition multimedia interface. The image signal transmission device 110 is a source, such as but not limited to a set-top box, a DVD player, a computer, and the like. The image signal receiving device 120 is a sink, such as but not limited to a TV, a projector or other display devices. The video signal transmission device 110 is configured to process the video and audio signals, and then transmit them to the video signal reception device 120 for playback.

The video signal transmission device 110 includes a digital signal processing circuit 130 and a signal output circuit 140 .

The digital signal processing circuit 130 is configured to generate digital input signals Vip, Vin in differential form. The signal output circuit 140 has a DC gain maintenance mechanism to enhance the output of the digital input signals Vip and Vin. The signal output circuit 140 includes: a pre-stage driving circuit 150 and a post-stage driving circuit 160 .

The pre-stage driving circuit 150 is configured to receive the digital input signals Vip and Vin for high frequency enhancement, so as to increase the bandwidth of the digital input signals Vip and Vin, thereby generating the pre-stage output signals Vop1 and Von1 . The pre-stage output signals Vop1 and Von1 are also differential signals.

Please refer to Figure 2. FIG. 2 shows a circuit diagram of the pre-driver circuit 150 according to an embodiment of the present invention. In one embodiment, the pre-driver circuit 150 includes a continuous-time linear equalizer with variable capacitance. More specifically, the continuous-time linear equalizer includes two input transistors MN1, MN2, two load resistors R1, R2, two load capacitors C1, C2, a variable resistor R3, a variable capacitor C3, and two current sources I1, I2.

Each of the input transistors MN1 and MN2 includes a gate, a drain and a source. The gate of the input transistor MN1 is configured to receive the digital input signal Vip. The gate of the input transistor MN2 is configured to receive the digital input signal Vin. The drain of the input transistor MN1 is electrically coupled to the output terminal O1, and the drain of the input transistor MN2 is electrically coupled to the output terminal O2.

The drain of the input transistor MN1 is configured to generate the preceding output signal Vop1 to the output terminal O1, and the drain of the input transistor MN2 is configured to generate the preceding output signal Von1 to the output terminal O2.

The load resistor R1 is electrically coupled between the drain of the input transistor MN1 and the operating voltage source VDD. The load resistor R2 is electrically coupled between the drain of the input transistor MN2 and the operating voltage source VDD. The load capacitor C1 is electrically coupled between the drain of the input transistor MN1 and the operating voltage source VDD. The load capacitor C2 is electrically coupled between the drain of the input transistor MN2 and the operating voltage source VDD.

The variable resistor R3 and the variable capacitor C3 are electrically connected in parallel between the sources of the input transistors MN1 and MN2. The current source I1 is electrically coupled between the source of the input transistor MN1 and the ground terminal GND. The current source I2 is electrically coupled between the source of the input transistor MN2 and the ground terminal GND.

In one embodiment, the zero point and the two poles of the frequency response of the pre-stage driving circuit 150 are determined by a plurality of circuit parameter values of the pre-stage driving circuit 150 .

Please also refer to Figure 3. FIG. 3 is a schematic diagram showing the frequency response of the pre-driver circuit 150 according to an embodiment of the present invention. Among them, the horizontal axis is the frequency, and the vertical axis is the gain. In this embodiment, the gain corresponding to the horizontal axis is the original gain of the digital input signals Vip and Vin.

In one embodiment, the circuit parameters of the pre-drive circuit 150 include the transconductance of the transistor, the resistance value of each resistor, and the capacitance value of each capacitor. For example, the transconductance of the input transistors MN1 and MN2 is gm, the resistance value of each load resistor R1 and R2 is Rd, the capacitance value of each load capacitor C1 and C2 is Cd, and the resistance value of the variable resistor is 2Rs , and the capacitance value of the variable capacitor is Cs.

Therefore, as far as the frequency response of the pre-stage driving circuit 150 is concerned, the conversion function H(s) for converting the digital input signals Vip and Vin into the pre-stage output signals Vop1 and Von1 can be expressed as:

H(s)=(gmRd)(1+sRsCs)/(1+sRcCs+gmRs)(1+sRdCd))

Moreover, the DC gain of the front-end driving circuit 150 can be expressed as:

(gmRd)/(1+(gmRs))

The zero point ω _Z on the frequency response can be expressed as:

ω _Z =1/(RsCs)

One of the poles ω _P1 can be expressed as:

ω _P1 =(1+gmRs)/(RsCs)

Another pole ω _P2 can be expressed as:

ω _P2 =1/(RdCd)

Therefore, by adjusting the above-mentioned circuit parameters, the zero point and the two poles of the frequency response of the pre-stage driving circuit 150 can be changed accordingly, and the DC gain and the high frequency part can be improved to different degrees.

It should be noted that, after being processed by the pre-stage driving circuit 150 , the DC gains of the pre-stage output signals Vop1 and Von1 relative to the digital input signals Vip and Vin are reduced.

The post-stage driving circuit 160 is configured to receive the pre-stage output signals Vop1 and Von1 to perform DC gain enhancement, so as to compensate the DC gain drop of the pre-stage output signals Vop1 and Von1 relative to the digital input signals Vip and Vin, and further generate the post-stage output signal Vop2 , Von2 to the video signal receiving device 120 . Among them, the post-stage output signals Vop2 and Von2 are also differential signals.

Please refer to Figure 4. FIG. 4 shows a circuit diagram of the post-stage driving circuit 160 according to an embodiment of the present invention. In one embodiment, the post-driving circuit 160 includes a continuous-time linear equalizer without variable capacitance. More specifically, the continuous-time linear equalizer includes two input transistors MN1, MN2, two load resistors R1, R2, two load capacitors C1, C2, a variable resistor R3, and two current sources I1, I2. It should be noted that, since the post-stage driving circuit 160 is similar to the pre-stage driving circuit 150 in terms of structure, corresponding components are not additionally marked with new numbers.

Except that the post-stage driving circuit 160 does not have a variable capacitor, the connection and operation of other components are similar to those of the pre-stage driving circuit 150 , so the similarities will not be repeated. In this embodiment, the gate of the input transistor MN1 of the post-stage driving circuit 160 is configured to receive the pre-stage output signal Vop1. The gate of the input transistor MN2 is configured to receive the preceding output signal Von1. In addition, the drain of the input transistor MN1 is configured to generate the output signal Vop2 of the subsequent stage to the output terminal O1, and the drain of the input transistor MN2 is configured to generate the output signal Von2 of the subsequent stage to the output terminal O2.

In one embodiment, the frequency response of the post-drive circuit 160 will only include a single pole, and this pole is determined by a plurality of circuit parameter values of the post-drive circuit 160 .

Please also refer to Figure 5. FIG. 5 is a schematic diagram showing the frequency response of the post-stage driving circuit 160 according to an embodiment of the present invention. Among them, the horizontal axis is the frequency, and the vertical axis is the gain. In this embodiment, the gain corresponding to the horizontal axis is the original gain of the output signals Vop1 and Von1 of the previous stage.

Similar to the pre-drive circuit 150 , the circuit parameters of the post-drive circuit 160 include the transconductance of the transistor, the resistance value of each resistor, and the capacitance value of each capacitor. However, these circuit parameters are different from those of the pre-drive circuit 150 . More specifically, the transconductance of the input transistors MN1 and MN2 is gm, the resistance value of each load resistor R1 and R2 is Rs, the capacitance value of each load capacitor C1 and C2 is Cd, and the resistance value of the variable resistor is 2Rd.

Therefore, in terms of the frequency response of the post-stage driving circuit 160, the conversion function formula H(s) for converting the pre-stage output signals Vop1 and Von1 into the post-stage output signals Vop2 and Von2 can be expressed as: conversion function formula H (s) can be expressed as:

H(s)=(gmRs)/(1+gmRd)(1+sRsCd)

Moreover, the DC gain of the post-stage driving circuit 160 can be expressed as:

(gmRs)/(1+(gmRd))

A single pole ω _P2 can be expressed as:

ω _P2 =1/(RsCd)

It should be noted that, after being processed by the post-stage driving circuit 160 , the DC gains of the post-stage output signals Vop2 and Von2 relative to the pre-stage output signals Vop1 and Von1 are increased.

Please refer to Figure 6. FIG. 6 is a schematic diagram showing the frequency response of the output signals Vop2 and Von2 after the digital input signals Vip and Vin are processed by the pre-driving circuit 150 and the post-driving circuit 160 according to an embodiment of the present invention. More specifically, the waveform of FIG. 6 corresponds to the result of superimposing the waveforms of FIG. 3 and FIG. 5 .

Since the DC gain of the pre-stage driving circuit 150 is (gmRd)/(1+(gmRs)), and the DC gain of the post-stage driving circuit 160 is (gmRs)/(1+(gmRd)), the post-stage output signal Vop2 , The DC gain of Von2 relative to the digital input signals Vip and Vin can be expressed as:

((gmRd)(gmRs))/((1+(gmRs))(1+(gmRd)))

In one embodiment, when the product of the corresponding transconductance of the front-stage driving circuit 150 and the back-stage driving circuit 160 and the resistance value of the load resistance (that is, gmRd and gmRs) is much greater than 1, the front-stage driving circuit 150 and the back-stage driving circuit 160 The DC gains generated by the stage drive circuits 160 will cancel each other out. More specifically, in such a situation, the DC gain of the post-stage output signals Vop2 and Von2 with respect to the digital input signals Vip and Vin is 1.

When the signal output circuit is processed by the front-stage driving circuit, although the AC gain can be amplified and the bandwidth can be increased, the DC gain will also be reduced. Therefore, the signal output circuit of the present invention can increase the DC gain through the setting of the rear-stage driving circuit to compensate for the decrease of the DC gain caused by the front-stage driving circuit, and increase the bandwidth of the output signal without losing the DC gain.

It should be noted that the above-mentioned embodiment is only an example. In other embodiments, those skilled in the art can make changes without departing from the spirit of the present invention.

In view of the above, the image signal transmission device and the signal output circuit with the DC gain maintaining mechanism in the present invention can increase the DC gain by setting the post-stage driving circuit to compensate for the decrease in the DC gain caused by the pre-stage driving circuit without loss of Increase the bandwidth of the output signal in the case of DC gain.

Although the embodiments of the present application are as described above, these embodiments are not intended to limit the present application. Those skilled in the art can change the technical features of the present application according to the explicit or implicit contents of the present application. All such changes may belong to the scope of patent protection sought by this application, in other words, the scope of patent protection of this application shall be determined by the claims in this specification.

Claims (10)

1. A signal output circuit with a DC gain maintaining mechanism, applied in an image signal transmission device, characterized in that, comprising: A pre-drive circuit includes a continuous-time linear equalizer with a variable capacitor, and is configured to receive a digital input signal for high-frequency enhancement, so as to increase a bandwidth of the digital input signal, thereby generating a pre-stage output signal ;as well as A post-stage driving circuit, including the continuous-time linear equalizer without the variable capacitor, and configured to perform a DC gain boost on the pre-stage output signal, so that the pre-stage output signal has a constant DC gain relative to the digital input signal. The stream gain drop is compensated for, and a post-stage output signal is further generated to an image signal receiving device. 2 . The signal output circuit of claim 1 , wherein the digital input signal, the pre-stage output signal and the post-stage output signal are respectively a differential signal. 3 . 3 . The signal output circuit of claim 1 , wherein the pre-stage driving circuit receives the pre-stage output signal from a digital signal processing circuit included in the image signal transmission device. 4 . 4. The signal output circuit of claim 1, wherein the pre-driver circuit comprises: Two input transistors, each consisting of: a gate configured to receive the digital input signal; a drain, electrically coupled to an output terminal, configured to generate the pre-stage output signal to the output terminal; and a source; two load resistors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source; two load capacitors, each electrically coupled between the drain of one of the two input transistors and a ground terminal; A variable resistor and the variable capacitor are electrically connected in parallel between the sources of the two input transistors; and Two current sources, each electrically coupled between the source of one of the two input transistors and the ground terminal. 5 . The signal output circuit of claim 4 , wherein a zero point and two poles of the frequency response of the pre-stage driving circuit are determined by a plurality of circuit parameter values of the pre-stage driving circuit, and the plurality of The circuit parameters include the resistance value Rd of each of the two load resistors, the capacitance value Cd of each of the two load capacitors, the resistance value 2Rs of the variable resistor, and the capacitance value Cs of the variable capacitor; One of the transconductances of the two input transistors is gm, the zero point is 1/(RsCs), the two poles are (1+gmRs)/(RsCs) and 1/(RdCd) respectively, the digital input signal and the pre-stage A transfer function between the output signals is (gmRd)(1+sRsCs)/(1+sRcCs+gmRs)(1+sRdCd)), and the DC gain of the pre-driver circuit is (gmRd)/(1+( gmRs)). 6. The signal output circuit of claim 1, wherein the post-stage driving circuit comprises: Two input transistors, each consisting of: a gate, configured to receive the output signal of the preceding stage; a drain, electrically coupled to an output terminal, configured to generate the output signal of the subsequent stage to the output terminal; and a source; two load resistors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source; two load capacitors, each electrically coupled between the drain of one of the two input transistors and a ground terminal; a variable resistor electrically connected in parallel between the sources of the two input transistors; and Two current sources, each electrically coupled between the source of one of the two input transistors and the ground terminal. 7. The signal output circuit of claim 6, wherein a pole of the frequency response of the post-stage driving circuit is determined by a plurality of circuit parameter values of the post-stage driving circuit, the plurality of circuit parameters including each of the two The resistance value Rs of the load resistor, the capacitance value Cd of each of the two load capacitors, and the resistance value 2Rd of the variable resistor; A transconductance of the two input transistors is gm, the pole is 1/(RsCd), and a transfer function between the digital input signal and the output signal of the previous stage is (gmRs)/(1+gmRd)(1+ sRsCd), the DC gain of the post-stage driver circuit is (gmRs)/(1+(gmRd)). 8. The signal output circuit as claimed in claim 1, wherein the product of the DC gain of each of the front-stage driver circuit and the rear-stage driver circuit is much greater than 1 when the product of a corresponding transconductance and a resistance value of a load resistor offset each other. 9. An image signal transmission device, applied in an image signal transmission system, comprising: a digital signal processing circuit configured to generate a digital input signal; and a signal output circuit, comprising: A pre-drive circuit includes a continuous-time linear equalizer with a variable capacitor, and is configured to receive a digital input signal for high-frequency enhancement, so as to increase a bandwidth of the digital input signal, thereby generating a pre-stage output signal ;as well as A post-stage driving circuit, including the continuous-time linear equalizer without the variable capacitor, and configured to perform a DC gain boost on the pre-stage output signal, so that the pre-stage output signal has a constant DC gain relative to the digital input signal. The stream gain is decreased to compensate, and a post-stage output signal is further generated to an image signal receiving device. 10. The image signal transmission device as claimed in claim 9, wherein the product of the DC gain of each of the pre-stage driving circuit and the post-stage driving circuit is much greater than the product of the corresponding resistance values of a transconductance and a load resistor 1 o'clock offset each other.

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