CN115023052B - Printed circuit board, manufacturing method thereof and miniature luminous display device - Google Patents
Printed circuit board, manufacturing method thereof and miniature luminous display device Download PDFInfo
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- CN115023052B CN115023052B CN202210757476.4A CN202210757476A CN115023052B CN 115023052 B CN115023052 B CN 115023052B CN 202210757476 A CN202210757476 A CN 202210757476A CN 115023052 B CN115023052 B CN 115023052B
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- copper
- multilayer board
- printed circuit
- blind holes
- outer layer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 173
- 229910052802 copper Inorganic materials 0.000 claims abstract description 126
- 239000010949 copper Substances 0.000 claims abstract description 126
- 239000011889 copper foil Substances 0.000 claims abstract description 47
- 230000008021 deposition Effects 0.000 claims abstract description 34
- 238000009713 electroplating Methods 0.000 claims abstract description 29
- 238000000059 patterning Methods 0.000 claims abstract description 18
- 238000009413 insulation Methods 0.000 claims abstract description 7
- 238000010030 laminating Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 36
- 230000009467 reduction Effects 0.000 claims description 21
- 230000008569 process Effects 0.000 claims description 16
- 238000001514 detection method Methods 0.000 claims description 3
- 230000003287 optical effect Effects 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 abstract description 15
- 101001134276 Homo sapiens S-methyl-5'-thioadenosine phosphorylase Proteins 0.000 description 5
- 102100022050 Protein canopy homolog 2 Human genes 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010329 laser etching Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The invention discloses a printed circuit board, a preparation method thereof and a miniature luminous display device. The preparation method of the printed circuit board comprises the following steps: laminating a copper foil on the surface of the multilayer board, wherein the thickness of the copper foil is smaller than or equal to a preset thickness; patterning the copper foil to form an outer layer circuit, wherein the outer layer circuit at least comprises a plurality of bonding pads and circuits connected with the bonding pads, and the minimum spacing between the bonding pads is smaller than or equal to the preset spacing; forming a plurality of blind holes, wherein the orthographic projection of the blind holes on the multilayer board is positioned in the orthographic projection of the bonding pads on the multilayer board, and the blind holes are arranged in one-to-one correspondence with the bonding pads; copper deposition treatment is carried out on the surface of the multilayer board so as to form a copper deposition layer covering the multilayer board; electroplating the blind holes to form an electroplated copper layer covering the blind holes; and carrying out microetching treatment on the outer layer circuit to remove the copper deposition layer in the outer layer circuit insulation groove. The technical scheme provided by the embodiment of the invention reduces the pad spacing of the printed circuit board and reduces the manufacturing cost of the printed circuit board.
Description
Technical Field
The invention relates to the technical field of printed circuit boards, in particular to a printed circuit board, a preparation method and a miniature luminous display device.
Background
With the development of light emitting technology, the Micro light emitting unit is, for example, a Mini/Micro LED Micro light emitting unit, which can greatly improve the performance of the Micro light emitting device, has the characteristics of high resolution, high brightness, high contrast, wide color gamut, and is lighter, thinner and energy-saving.
The pitch of the two bonding pads connected with the electrodes of the micro light emitting units is generally narrower, and the current pitch of the two bonding pads connected with the electrodes of the micro light emitting units can be reduced to 60 μm or even 50 μm by the traditional process of a high resolution exposure machine and thin copper. However, the conventional process cannot further reduce the pitch of the two bonding pads connected to the electrodes of the micro light emitting unit, and an expensive MSAP or SAP process is required to reduce the pitch of the two bonding pads connected to the electrodes of the micro light emitting unit, so that the processing cost is very high.
Therefore, there is a need for a printed circuit board having a pad pitch that matches the size of the micro light emitting unit and that is inexpensive to manufacture.
Disclosure of Invention
The invention provides a printed circuit board, a preparation method and a miniature luminous display device, which are used for reducing the pad spacing of the printed circuit board and reducing the manufacturing cost of the printed circuit board.
According to an aspect of the present invention, there is provided a method for manufacturing a printed circuit board, comprising:
Laminating a copper foil on the surface of the multilayer board, wherein the thickness of the copper foil is smaller than or equal to a preset thickness;
Patterning the copper foil to form an outer layer circuit, wherein the outer layer circuit at least comprises a plurality of bonding pads and circuits connected with the bonding pads, and the minimum spacing between the bonding pads is smaller than or equal to a preset spacing;
Forming a plurality of blind holes, wherein the orthographic projection of the blind holes on the multilayer board is positioned in the orthographic projection of the bonding pads on the multilayer board, and the blind holes are arranged in one-to-one correspondence with the bonding pads;
Copper deposition treatment is carried out on the surface of the multilayer board so as to form a copper deposition layer covering the multilayer board;
electroplating the blind holes to form an electroplated copper layer covering the blind holes, wherein the height difference between the electroplated copper layer and the base copper of the multilayer board is smaller than or equal to a preset height difference, and the base copper of the multilayer board is the part of the bonding pad, from which the blind holes are removed, and the copper deposition layer on the base copper of the multilayer board;
and carrying out microetching treatment on the outer layer circuit to remove the copper deposition layer in the outer layer circuit insulation groove.
Optionally, patterning the copper foil to form an outer layer circuit includes:
Forming a first dry film on the surface of the copper foil, which is away from the multilayer board;
Patterning the copper foil by taking the first dry film as a mask pattern to form an outer layer circuit;
and removing the first dry film.
Optionally, performing electroplating treatment on the blind hole to form an electroplated copper layer covering the blind hole comprises:
forming a second dry film on the surface of the copper deposition layer, which is away from the multilayer board;
electroplating the blind holes by taking the second dry film as a mask pattern to form an electroplated copper layer covering the multilayer board;
taking the second dry film as a mask pattern, and performing copper reduction treatment on the electroplated copper layer;
And the height difference of the base copper of the electroplated copper layer and the multilayer board is smaller than or equal to a preset height difference, stopping copper reduction treatment, and removing the second dry film.
Optionally, forming a second dry film on a surface of the copper deposition layer facing away from the multilayer board includes:
The surface of the copper deposition layer, which is away from the multilayer board, is provided with a second dry film comprising a plurality of windows, wherein the windows are arranged in one-to-one correspondence with the blind holes, and the blind holes and orifices of the blind holes are exposed.
Optionally, before the copper reduction treatment is performed on the electroplated copper layer, the second dry film is used as a mask pattern, and the method further comprises:
and determining the height difference of the electroplated copper layer and the base copper of the multilayer board by slicing the blind holes.
Optionally, microetching the outer layer circuit, and removing the copper deposition layer in the outer layer circuit insulation groove further comprises:
And carrying out optical detection on the outer layer circuit of the printed circuit board.
Optionally, the copper foil has a thickness of less than or equal to 1/4 ounce.
Optionally, the minimum spacing between the pads is less than or equal to 30 microns.
According to another aspect of the invention, a printed circuit board is provided, which is prepared by the method for preparing a printed circuit board according to any one of the embodiments of the invention.
According to another aspect of the present invention, there is provided a micro light emitting device comprising: the back plate comprises the printed circuit board according to any one of the embodiments of the present invention, wherein a first bonding pad and a second bonding pad are arranged on the surface of the back plate, and the distance between the first bonding pad and the second bonding pad is smaller than or equal to a preset distance;
The micro light-emitting units are provided with first electrodes and second electrodes, the micro light-emitting units are located on the surface of the backboard, the first electrodes are located on the surface, away from the backboard, of the first bonding pads, and the second electrodes are located on the surface, away from the backboard, of the second bonding pads;
the space between the first bonding pad and the second bonding pad is matched with the size of the miniature light-emitting unit.
According to the technical scheme provided by the embodiment, before the blind holes are formed, copper foil with the thickness smaller than or equal to the preset thickness is laminated on the surface of the multilayer board, the thickness of the copper foil is relatively thin, the flatness and the surface uniformity of the copper foil are high, and an outer layer circuit with a small size can be formed through patterning. The method is characterized in that bonding pads with the minimum spacing smaller than or equal to the preset spacing can be formed, the spacing between the two bonding pads connected with the electrodes of the miniature luminous unit is reduced, and the bonding pad spacing of the outer layer circuit of the printed circuit board is matched with the size of the miniature luminous unit. The method comprises the steps of forming an outer layer circuit before forming a blind hole, and forming the outer layer circuit after electroplating to fill the blind hole and reducing copper, so that the problem of low uniformity of electroplating and copper reduction can be avoided, bonding pads with minimum spacing smaller than or equal to preset spacing can be formed, the spacing between two bonding pads connected with electrodes of a miniature light-emitting unit and a printed circuit board is reduced, and the size matching degree of the bonding pad spacing of the outer layer circuit of the printed circuit board and the miniature light-emitting unit is further increased. In addition, the technical scheme does not need to adopt an expensive MSAP or SAP technology to prepare the printed circuit board, so that the preparation cost of the printed circuit board is reduced.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method for manufacturing a printed circuit board according to an embodiment of the present invention;
FIG. 2 is a flow chart of a preparation method included in S120 in FIG. 1;
Fig. 3 to fig. 10 are schematic structural diagrams corresponding to steps of a method for manufacturing a printed circuit board according to an embodiment of the present invention;
FIG. 11 is a flowchart of a preparation method included in S150 in FIG. 1;
Fig. 12 to 14 are schematic structural diagrams corresponding to each step of the preparation method included in S150 in fig. 11.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The embodiment of the invention provides a preparation method of a printed circuit board. Fig. 1 is a flowchart of a method for manufacturing a printed circuit board according to an embodiment of the present invention. Referring to fig. 1, the method for manufacturing a printed circuit board includes the steps of:
S110, laminating copper foil on the surface of the multilayer board, wherein the thickness of the copper foil is smaller than or equal to the preset thickness.
Referring to fig. 3, a multi-layer board 001 is provided, and copper foils 10 are laminated on two opposite surfaces of the multi-layer board 001, wherein the thickness of the copper foil 10 is less than or equal to a preset thickness. Optionally, the thickness of the copper foil 10 is less than or equal to 1/4 ounce.
Specifically, in this embodiment, the copper foil 10 with a thickness less than or equal to the preset thickness is laminated on the surface of the multilayer board 001, the thickness of the copper foil 10 is relatively thin, the flatness and surface uniformity of the copper foil 10 are high, and a circuit with a smaller size can be formed through patterning.
And S120, patterning the copper foil to form an outer layer circuit, wherein the outer layer circuit at least comprises a plurality of bonding pads and circuits connected with the bonding pads, and the minimum spacing between the bonding pads is smaller than or equal to the preset spacing.
Referring to fig. 4, the outer layer wiring is formed by patterning the copper foil 10. Illustratively, the outer layer of wiring includes pads 11 and wiring connected to the pads 11. Wherein the pads 11 include a first pad 11a and a second pad 11b. Illustratively, when the first electrode of the micro light emitting unit is electrically connected to the first pad 11a in a binding manner, and the second electrode of the micro light emitting unit is electrically connected to the second pad 11b in a binding manner, the first pad 11a and the second pad 11b are used to provide a driving signal for the micro light emitting unit. The Micro light emitting unit is, for example, a Mini/Micro LED Micro light emitting unit. In the present embodiment, the pitch d of the first pads 11a and the second pads 11b is the minimum pitch between the pads. Because the thickness of the copper foil 10 is relatively thin, the copper foil 10 has high flatness and surface uniformity, and a circuit with a small size can be formed through patterning. The minimum distance d between the first pad 11a and the second pad 11b may be less than or equal to 30 micrometers. The minimum distance d between the first pad 11a and the second pad 11b may be 20 μm or 30 μm, for example.
Optionally, referring to fig. 2, patterning the copper foil to form an outer layer circuit at S120 includes:
And S1201, forming a first dry film on the surface of the copper foil, which is away from the multilayer board.
S1202, patterning the copper foil by taking the first dry film as a mask pattern to form an outer layer circuit.
S1203, removing the first dry film.
The first dry film is exposed and developed to obtain a first dry film with a preset pattern. The copper foil 10 is etched under vacuum using the first dry film as a mask pattern to form an outer layer line. Wherein the first dry film with a thickness of about 15 micrometers is pressed on the multilayer board 001 at a pressing speed of about 2.0m/min. The first dry film was exposed using a 3 μm high resolution exposure machine and developed at a speed of 3 m/min.
S130, forming a plurality of blind holes, wherein the orthographic projection of the blind holes on the multilayer board is positioned in the orthographic projection of the bonding pads on the multilayer board, and the blind holes are arranged in one-to-one correspondence with the bonding pads.
Referring to fig. 5 and 6, a plurality of blind holes 12 are formed, the orthographic projection of the blind holes 12 on the multilayer board 001 is located within the orthographic projection of the bonding pads 11 on the multilayer board 001, and the blind holes 12 are arranged in one-to-one correspondence with the bonding pads 11. Blind vias 12 pass from copper foil 10 to copper layers inside multilayer board 001. For example, the outer layer line 11 may be first browned, and then a plurality of blind holes 12 may be formed by laser etching. Wherein the rate of browning is about 3.5m/min. And exposing and developing the first dry film to obtain a first dry film with a preset pattern. The copper foil 10 is etched under vacuum using the first dry film as a mask pattern to form an outer layer circuit 10a.
And S140, carrying out copper deposition treatment on the surface of the multilayer board to form a copper deposition layer covering the multilayer board.
Referring to fig. 7, copper deposition is performed on the surface of the multilayer board 001 to form a copper deposition layer 20 covering the multilayer board 001, and the copper deposition layer 20 covers the bottom surface and the side wall of the blind hole 12, so that the surface of the multilayer board 001 is in a conductive connection state, and normal manufacturing of subsequent electroplating filling holes is ensured.
And S150, electroplating the blind holes to form an electroplated copper layer covering the blind holes, wherein the height difference between the electroplated copper layer and the base copper of the multilayer board is smaller than or equal to the preset height difference, and the base copper of the multilayer board is the part of the bonding pad, from which the blind holes are removed, and the copper deposition layer on the base copper.
Referring to fig. 8, the blind via 12 is subjected to an electroplating process to form an electroplated copper layer 40 covering the blind via 12, wherein a difference in height between the electroplated copper layer 40 and the base copper of the multi-layer board 001 is less than or equal to a preset difference in height, and the base copper of the multi-layer board 001 is the portion of the pad 11 from which the blind via 12 is removed and the copper deposition layer 20 thereon. Wherein, the electroplating parameter is 12ASF 60min, and the electroplating area is calculated according to the blind hole 12 and Kong Huanmian product of the blind hole 12.
Specifically, the blind hole 12 subjected to electroplating treatment can enable the first bonding pad 11a and the second bonding pad 11b to electrically connect the internal circuit of the multilayer board 001 with the first electrode and the second electrode of the micro light emitting unit, so that the printed circuit board can provide driving signals for the micro light emitting unit.
S160, carrying out microetching treatment on the outer layer circuit, and removing the copper deposition layer in the insulating groove of the outer layer circuit.
Referring to fig. 9 and 10, the outer layer line 10a is microetched to remove the copper deposition layer 20 in the insulation groove of the outer layer line 10 a. The liquid medicine for microetching treatment can be selected from 30-60g/L NaPS and 100-150g/LH 2SO4 microetching speed of 2.5m/min, microetching amount of 0.5-1 mu m, removing the copper deposition layer 20 in the insulating groove of the outer layer circuit 10a, and completing the electrical connection of the outer layer circuit 10 a.
Optionally, S160 performs microetching treatment on the outer layer line, and after removing the copper deposition layer in the insulation groove of the outer layer line, the method further includes: the outer layer wiring 10a of the printed circuit board is optically inspected.
Specifically, by performing optical detection on the outer layer circuit 10a of the printed circuit board, faults of the outer layer circuit 10a can be found in time, so that the yield of the printed circuit board is improved.
According to the technical scheme provided by the embodiment, before the blind holes are formed, copper foil with the thickness smaller than or equal to the preset thickness is laminated on the surface of the multilayer board, the thickness of the copper foil is relatively thin, the flatness and the surface uniformity of the copper foil are high, and an outer layer circuit with a small size can be formed through patterning. The method is characterized in that bonding pads with the minimum spacing smaller than or equal to the preset spacing can be formed, the spacing between the two bonding pads connected with the electrodes of the miniature luminous unit is reduced, and the bonding pad spacing of the outer layer circuit of the printed circuit board is matched with the size of the miniature luminous unit. The method comprises the steps of forming an outer layer circuit before forming a blind hole, and forming the outer layer circuit after electroplating to fill the blind hole and reducing copper, so that the problem of low uniformity of electroplating and copper reduction can be avoided, bonding pads with minimum spacing smaller than or equal to preset spacing can be formed, the spacing between two bonding pads connected with electrodes of a miniature light-emitting unit and a printed circuit board is reduced, and the size matching degree of the bonding pad spacing of the outer layer circuit of the printed circuit board and the miniature light-emitting unit is further increased. In addition, the technical scheme does not need to adopt an expensive MSAP or SAP technology to prepare the printed circuit board, so that the preparation cost of the printed circuit board is reduced.
Fig. 11 is a flowchart of the preparation method included in S150 in fig. 1. Optionally, S150 performing an electroplating process on the blind hole to form an electroplated copper layer covering the blind hole includes:
S1501, forming a second dry film on the surface of the copper deposition layer, which is away from the multilayer board.
Referring to fig. 12 and 13, a second dry film 30 is formed on the surface of the copper deposition layer 20 facing away from the multilayer board 001.
Optionally, forming the second dry film on the surface of the copper deposition layer facing away from the multilayer board in S1501 includes: and forming a second dry film comprising a plurality of windows on the surface of the copper deposition layer, which is away from the multilayer board, wherein the windows are arranged in one-to-one correspondence with the blind holes, and the blind holes and the orifices of the blind holes are exposed.
Referring to fig. 13, a second dry film 30 including a plurality of windows is formed on the surface of the copper deposition layer 20 facing away from the multilayer board 001, wherein the windows are disposed in one-to-one correspondence with the blind holes 12, and the windows expose the blind holes 12 and the orifices 12a of the blind holes 12. Specifically, the second dry film 30 is formed by forming the second dry film 30 on the multilayer board 001 after the copper deposition process, and the second dry film 30 after the patterning process exposes the blind holes 12 and the apertures 12a of the blind holes 12. Illustratively, the annular width of the aperture 12a of the blind bore 12 is about 3 mils.
S1502, electroplating the blind holes by taking the second dry film as a mask pattern to form an electroplated copper layer covering the multilayer board.
Referring to fig. 14, the blind via 12 is subjected to an electroplating process by a VCP electroplating process using the second dry film 30 as a mask pattern to form an electroplated copper layer 40 covering the multi-layer board 001. Wherein, the electroplating parameter is 12ASF 60min, and the electroplating area is calculated according to the area of the blind hole 12 and the orifice 12a of the blind hole 12.
S1503, taking the second dry film as a mask pattern, and performing copper reduction treatment on the electroplated copper layer.
Referring to fig. 14, the electroplated copper layer 40 is subjected to a copper reduction treatment using the second dry film 30 as a mask pattern. In this embodiment, the blind holes 12 are subjected to an electroplating process using the second dry film 30 as a mask pattern to form an electroplated copper layer 40 covering the multilayer board 001. Namely, a copper reduction treatment process with dry film copper reduction is adopted in the embodiment. Wherein, the etching liquid for copper reduction treatment adopts 100-150g/L H SO4 and 40-80g/L H 2O2 copper reduction.
Optionally, S1503 further includes, before the copper reduction treatment is performed on the electroplated copper layer, using the second dry film as a mask pattern: the difference in the height of the base copper of the electroplated copper layer 40 and the multilayer board 001 is determined by subjecting the blind via 12 to a dicing process.
Specifically, by performing the dicing process on the blind hole 12 to determine the difference in the heights of the base copper of the electroplated copper layer 40 and the multilayer board 001, the difference in the heights of the base copper of the electroplated copper layer 40 and the multilayer board 001 can be accurately obtained, thereby contributing to improvement in the flatness of the base copper surfaces of the electroplated copper layer 40 and the multilayer board 001.
S1504, the height difference of the base copper of the electroplated copper layer and the multilayer plate is smaller than or equal to the preset height difference, the copper reduction treatment is stopped, and the second dry film is removed.
Referring to fig. 8, the preset height difference may be controlled within a range of 5 μm. The electroplated copper layer 40 may be higher than the base copper of the multiwall sheet 001 relative to the multiwall sheet 001, or the base copper of the multiwall sheet 001 may be higher than the electroplated copper layer 40. In the process of performing the copper reduction treatment on the electroplated copper layer 40 using the second dry film 30 as a mask pattern, the copper reduction treatment may be stopped and the second dry film 30 may be removed as long as the difference in height between the electroplated copper layer 40 and the base copper of the multilayer board 001 is less than or equal to a preset difference in height.
On the basis of the technical scheme, after blind hole electroplating, the technical scheme provided by the embodiment has the advantages that the second dry film is used for reducing copper, and on the basis that the height difference of base copper of an electroplated copper layer and a multilayer board is controlled in a reasonable range, the printed circuit board at the covering position of the second dry film is protected during copper reduction, so that the yield of the printed circuit board is improved.
The embodiment of the invention also provides a printed circuit board, which is prepared by adopting the preparation method of the printed circuit board according to any one of the embodiments of the invention.
In the preparation process of the printed circuit board provided by the embodiment, the copper foil with the thickness smaller than or equal to the preset thickness is laminated on the surface of the multilayer board before the blind holes are formed, the thickness of the copper foil is relatively thin, the flatness and the surface uniformity of the copper foil are high, and an outer layer circuit with a small size can be formed through patterning. The method is characterized in that bonding pads with the minimum spacing smaller than or equal to the preset spacing can be formed, the spacing between the two bonding pads connected with the electrodes of the miniature luminous unit is reduced, and the bonding pad spacing of the outer layer circuit of the printed circuit board is matched with the size of the miniature luminous unit. The method comprises the steps of forming an outer layer circuit before forming a blind hole, and forming the outer layer circuit after electroplating to fill the blind hole and reducing copper, so that the problem of low uniformity of electroplating and copper reduction can be avoided, bonding pads with minimum spacing smaller than or equal to preset spacing can be formed, the spacing between two bonding pads connected with electrodes of a miniature light-emitting unit and a printed circuit board is reduced, and the size matching degree of the bonding pad spacing of the outer layer circuit of the printed circuit board and the miniature light-emitting unit is further increased. In addition, the technical scheme does not need to adopt an expensive MSAP or SAP technology to prepare the printed circuit board, so that the preparation cost of the printed circuit board is reduced.
The embodiment of the invention also provides a miniature light-emitting device. The micro light emitting device includes: the back plate comprises the printed circuit board according to any one of the embodiments of the invention, the surface of the back plate is provided with a first bonding pad and a second bonding pad, and the distance between the first bonding pad and the second bonding pad is smaller than or equal to the preset distance; the micro light-emitting units are provided with first electrodes and second electrodes, the micro light-emitting units are positioned on the surface of the backboard, the first electrodes are positioned on the surface of the first bonding pads, which is away from the backboard, and the second electrodes are positioned on the surface of the second bonding pads, which is away from the backboard; the spacing between the first pad and the second pad matches the size of the micro light emitting unit.
According to the miniature light-emitting device provided by the embodiment, before the blind holes are formed in the back plate, the copper foil with the thickness smaller than or equal to the preset thickness is laminated on the surface of the multilayer plate, the thickness of the copper foil is relatively thin, the flatness and the surface uniformity of the copper foil are high, and an outer layer circuit with a small size can be formed through patterning. The method is characterized in that bonding pads with the minimum spacing smaller than or equal to the preset spacing can be formed, the spacing between the two bonding pads connected with the electrodes of the miniature light-emitting unit and the back plate is reduced, and the bonding pad spacing of the outer layer circuit of the back plate is matched with the size of the miniature light-emitting unit. The method comprises the steps of forming an outer layer circuit before forming a blind hole, and forming the outer layer circuit after electroplating to fill the blind hole and reducing copper, so that the problem of low uniformity of electroplating and copper reduction can be avoided, bonding pads with minimum spacing smaller than or equal to preset spacing can be formed, the spacing between two bonding pads connected with the electrode of a miniature light-emitting unit and the back plate is reduced, and the size matching degree of the bonding pad spacing of the outer layer circuit of the back plate and the miniature light-emitting unit is further increased. In addition, the technical scheme does not need to adopt an expensive MSAP or SAP technology to prepare the printed circuit board, thereby reducing the preparation cost of the miniature luminescent device.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (8)
1. A method of manufacturing a printed circuit board, comprising:
Laminating a copper foil on the surface of the multilayer board, wherein the thickness of the copper foil is smaller than or equal to a preset thickness;
Patterning the copper foil to form an outer layer circuit, wherein the outer layer circuit at least comprises a plurality of bonding pads and circuits connected with the bonding pads, and the minimum spacing between the bonding pads is smaller than or equal to a preset spacing;
Forming a plurality of blind holes, wherein the orthographic projection of the blind holes on the multilayer board is positioned in the orthographic projection of the bonding pads on the multilayer board, and the blind holes are arranged in one-to-one correspondence with the bonding pads;
Copper deposition treatment is carried out on the surface of the multilayer board so as to form a copper deposition layer covering the multilayer board;
electroplating the blind holes to form an electroplated copper layer covering the blind holes, wherein the height difference between the electroplated copper layer and the base copper of the multilayer board is smaller than or equal to a preset height difference, and the base copper of the multilayer board is the part of the bonding pad, from which the blind holes are removed, and the copper deposition layer on the base copper of the multilayer board;
Microetching the outer layer circuit to remove a copper deposition layer in the outer layer circuit insulation groove;
wherein the copper foil has a thickness of less than or equal to 1/4 ounce; the minimum spacing between the pads is less than or equal to 30 microns.
2. The method of manufacturing a printed circuit board of claim 1, wherein patterning the copper foil to form an outer layer of circuitry comprises:
Forming a first dry film on the surface of the copper foil, which is away from the multilayer board;
Patterning the copper foil by taking the first dry film as a mask pattern to form an outer layer circuit;
and removing the first dry film.
3. The method of manufacturing a printed circuit board of claim 1, wherein performing an electroplating process on the blind via to form an electroplated copper layer covering the blind via comprises:
forming a second dry film on the surface of the copper deposition layer, which is away from the multilayer board;
electroplating the blind holes by taking the second dry film as a mask pattern to form an electroplated copper layer covering the multilayer board;
taking the second dry film as a mask pattern, and performing copper reduction treatment on the electroplated copper layer;
And the height difference of the base copper of the electroplated copper layer and the multilayer board is smaller than or equal to a preset height difference, stopping copper reduction treatment, and removing the second dry film.
4. The method of manufacturing a printed circuit board of claim 3, wherein forming a second dry film on a surface of the copper deposit facing away from the multilayer board comprises:
The surface of the copper deposition layer, which is away from the multilayer board, is provided with a second dry film comprising a plurality of windows, wherein the windows are arranged in one-to-one correspondence with the blind holes, and the blind holes and orifices of the blind holes are exposed.
5. The method of manufacturing a printed circuit board according to claim 3, wherein the step of performing the copper reduction treatment on the electroplated copper layer by using the second dry film as a mask pattern further comprises:
and determining the height difference of the electroplated copper layer and the base copper of the multilayer board by slicing the blind holes.
6. The method for manufacturing a printed circuit board according to claim 1, wherein the step of microetching the outer layer circuit to remove the copper deposition layer in the outer layer circuit insulation groove further comprises:
And carrying out optical detection on the outer layer circuit of the printed circuit board.
7. A printed circuit board prepared by the method of any one of claims 1-6.
8. A micro light emitting device, comprising: a back plate comprising the printed circuit board of claim 7, the surface of the back plate being provided with a first pad and a second pad, the spacing between the first pad and the second pad being less than or equal to a preset spacing;
The micro light-emitting units are provided with first electrodes and second electrodes, the micro light-emitting units are located on the surface of the backboard, the first electrodes are located on the surface, away from the backboard, of the first bonding pads, and the second electrodes are located on the surface, away from the backboard, of the second bonding pads;
the space between the first bonding pad and the second bonding pad is matched with the size of the miniature light-emitting unit.
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---|---|---|---|---|
CN106332442A (en) * | 2015-06-26 | 2017-01-11 | 富葵精密组件(深圳)有限公司 | Circuit board and manufacturing method thereof |
CN109195341A (en) * | 2018-09-12 | 2019-01-11 | 安捷利(番禺)电子实业有限公司 | A kind of preparation method for the precise printed circuit board improving route copper layer thickness and width |
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US5733468A (en) * | 1996-08-27 | 1998-03-31 | Conway, Jr.; John W. | Pattern plating method for fabricating printed circuit boards |
GB9828656D0 (en) * | 1998-12-23 | 1999-02-17 | Northern Telecom Ltd | High density printed wiring board having in-via surface mounting pads |
JP4170137B2 (en) * | 2003-04-24 | 2008-10-22 | 新光電気工業株式会社 | Wiring board and electronic component mounting structure |
JP2009206154A (en) * | 2008-02-26 | 2009-09-10 | Nec Electronics Corp | Wiring board, and manufacturing method thereof |
CN112954903A (en) * | 2021-01-19 | 2021-06-11 | 江门崇达电路技术有限公司 | Ultrathin high-density printed board and manufacturing method thereof |
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CN106332442A (en) * | 2015-06-26 | 2017-01-11 | 富葵精密组件(深圳)有限公司 | Circuit board and manufacturing method thereof |
CN109195341A (en) * | 2018-09-12 | 2019-01-11 | 安捷利(番禺)电子实业有限公司 | A kind of preparation method for the precise printed circuit board improving route copper layer thickness and width |
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