CN114978054A - Self-stabilizing zero operational amplifier - Google Patents
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- H—ELECTRICITY
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- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/38—DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers
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- H—ELECTRICITY
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Abstract
The embodiment of the disclosure provides a self-stabilizing zero operational amplifier, which comprises four choppers, two first-stage amplifiers, a second-stage amplifier, two zero-setting amplifiers, four storage capacitors and six switches, wherein a ping-pong architecture is used in the self-stabilizing zero operational amplifier, a large off-chip capacitor is not needed, and on the basis of the self-stabilizing zero operational amplifier, a chopping technology is used for modulating low-frequency aliasing noise to a chopping frequency, so that the low-frequency aliasing noise is obtained in a direct current to chopping frequency range, an additional filter circuit is not needed, the area is smaller, and the precision is higher.
Description
Technical Field
Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to a self-stabilizing zero operational amplifier.
Background
At present, for the field of high-precision signal detection, an amplifier is generally required to have very low offset voltage and lower noise characteristic within a certain signal bandwidth (< kHz), and common methods are a chopping technology and a self-stabilizing zero technology.
The chopping technique is a modulation technique, which can modulate low-frequency noise and offset voltage to a chopping frequency, but the noise energy at the chopping frequency is high, and in order to eliminate the effect, a low-pass filter circuit is generally required. The self-zeroing technology is a sampling technology, and is to sample offset voltage and low-frequency noise and then subtract the sampled offset voltage in the next clock cycle, so that the offset voltage is eliminated, aliasing of thermal noise is caused, the low-frequency noise is increased, and sampling capacitance and power consumption are increased in order to reduce the low-frequency noise. In summary, current solutions to implement amplifiers with very low offset voltages and lower noise characteristics within a certain signal bandwidth increase circuit area and power consumption.
Disclosure of Invention
Embodiments described herein provide a self-standing zero operational amplifier in order to provide an amplifier with a very low offset voltage and low noise characteristics within a certain signal bandwidth.
According to a first aspect of the present disclosure, there is provided a self-stabilizing zero operational amplifier, comprising: the four choppers, two first-stage amplifiers, a second-stage amplifier, two zeroing amplifiers, four storage capacitors and six switches, wherein input signals are alternately modulated by the first chopper and the third chopper through the switching of the six switches, the input signals passing through the first chopper are amplified by the first-stage amplifier, demodulated by the second chopper and then output by the second-stage amplifier, the input signals passing through the third chopper are amplified by the second first-stage amplifier, amplified by the fourth chopper and demodulated by the second-stage amplifier; the input signal is a low-frequency differential signal; the first zeroing amplifier alternately stores and offsets the offset voltage of the first-stage amplifier through a first storage capacitor and a second storage capacitor, and the second zeroing amplifier alternately stores and offsets the offset voltage of the second first-stage amplifier through a third storage capacitor and a fourth storage capacitor; the second chopper and the fourth chopper alternately modulate low-frequency aliasing noise of the self-stabilizing zero operational amplifier in the self-stabilizing zero sampling process to a chopping frequency.
Optionally, an input end of the first chopper is connected to an input signal, two output ends of the first chopper are respectively connected to a positive input end and a negative input end of the first-stage amplifier, a positive output end of the first-stage amplifier is sequentially connected to the second chopper and the second switch and then connected to a positive input end of the first zeroing amplifier, a negative output end of the first-stage amplifier is sequentially connected to the second chopper and the third switch and then connected to a negative input end of the first zeroing amplifier, a positive output end and a negative output end of the first zeroing amplifier are respectively feedback-connected to a negative output end and a positive output end of the first-stage amplifier, and one end of the first switch is connected between one output end of the first chopper and the positive input end of the first-stage amplifier, the other end of the first switch is connected between the other output end of the first chopper and the inverting input end of the first-stage amplifier, one ends of the first storage capacitor and the second storage capacitor are grounded, the other end of the first storage capacitor is connected between the second switch and the non-inverting input end of the first zeroing amplifier, and the other end of the second storage capacitor is connected between the third switch and the inverting input end of the first zeroing amplifier; the input end of the third chopper is connected with an input signal, two output ends of the third chopper are respectively connected with the positive phase input end and the negative phase input end of the second first-stage amplifier, the positive phase output end of the second first-stage amplifier is sequentially connected with the fourth chopper and the fifth switch and then is connected with the positive phase input end of the second zeroing amplifier, the negative phase output end of the second first-stage amplifier is sequentially connected with the fourth chopper and the sixth switch and then is connected with the negative phase input end of the second zeroing amplifier, the positive phase output end and the negative phase output end of the second zeroing amplifier are respectively connected with the negative phase output end and the positive phase output end of the second first-stage amplifier in a feedback way, and one end of the fourth switch is connected between one output end of the third chopper and the positive phase input end of the second first-stage amplifier, the other end of the fourth switch is connected between the other output end of the third chopper and the inverting input end of the second first-stage amplifier, one ends of the third storage capacitor and the fourth storage capacitor are grounded, the other end of the third storage capacitor is connected between the fifth switch and the non-inverting input end of the second zeroing amplifier, and the other end of the fourth storage capacitor is connected between the sixth switch and the inverting input end of the second zeroing amplifier; the output end of the second-stage amplifier is a signal output end, the positive phase input end of the second-stage amplifier is respectively connected between one output end of the second chopper and the second switch, one output end of the fourth chopper and the fifth switch, the negative phase input end of the second-stage amplifier is respectively connected between the other output end of the second chopper and the third switch, the other output end of the fourth chopper and the sixth switch, and the output end of the second-stage amplifier is connected with a compensation capacitor and then is connected to the negative phase input end of the second-stage amplifier in a feedback mode.
Optionally, the clock control signals of the first switch, the second switch, and the third switch are first clock signals, the clock control signals of the fourth switch, the fifth switch, and the sixth switch are second clock signals, and the first clock signal and the second clock signal are two-phase clock signals that are not overlapped.
Optionally, the clock control signals of the first chopper and the second chopper are third clock signals, the clock control signals of the third chopper and the fourth chopper are fourth clock signals, the periods of the third clock signal, the fourth clock signal, the first clock signal and the second clock signal are the same, the first clock signal and the fourth clock signal arrive at the same time, the duration of the first clock signal is twice the duration of the fourth clock signal, the second clock signal and the third clock signal arrive at the same time, and the duration of the second clock signal is twice the duration of the third clock signal.
Optionally, the difference between the voltages stored in the first storage capacitor and the second storage capacitor is equal to the transconductance of the first-stage amplifier multiplied by the offset voltage of the first-stage amplifier and divided by the transconductance of the first nulling amplifier; the difference between the voltages stored on the third storage capacitor and the fourth storage capacitor is equal to the transconductance of the second first-stage amplifier multiplied by the offset voltage of the second first-stage amplifier divided by the transconductance of the second nulling amplifier.
Optionally, the transconductance of the first-stage amplifier is greater than the transconductance of the first nulling amplifier; the transconductance of the second first-stage amplifier is greater than the transconductance of the second nulling amplifier.
Optionally, the transconductance of the first-stage amplifier is ten times that of the first nulling amplifier; the transconductance of the second first-stage amplifier is ten times that of the second nulling amplifier.
Optionally, the capacitance ranges of the first storage capacitor, the second storage capacitor, the third storage capacitor and the fourth storage capacitor are greater than or equal to 10 picofarads and less than or equal to 20 picofarads.
Optionally, the input signal is a high-precision sensor signal.
According to a second aspect of the present disclosure, a gain-adjustable amplifier is provided, where the gain-adjustable amplifier includes the self-zeroing operational amplifier and an external resistor of any one of the first aspect, and the self-zeroing operational amplifier is connected to the external resistors with different resistances to adjust a gain.
The self-stabilizing zero operational amplifier of the embodiment of the present disclosure includes: the four choppers, two first-stage amplifiers, a second-stage amplifier, two zeroing amplifiers, four storage capacitors and six switches, wherein input signals are alternately modulated by the first chopper and the third chopper through the switching of the six switches, the input signals passing through the first chopper are amplified by the first-stage amplifier, demodulated by the second chopper and then output by the second-stage amplifier, the input signals passing through the third chopper are amplified by the second first-stage amplifier, demodulated by the fourth chopper and then output by the second-stage amplifier; the input signal is a low-frequency differential signal; the first zeroing amplifier alternately stores and offsets the offset voltage of the first-stage amplifier through a first storage capacitor and a second storage capacitor, and the second zeroing amplifier alternately stores and offsets the offset voltage of the second first-stage amplifier through a third storage capacitor and a fourth storage capacitor; the second chopper and the fourth chopper alternately modulate low-frequency aliasing noise of the self-stabilizing zero operational amplifier in the self-stabilizing zero sampling process to a chopping frequency. It can be seen that the self-stabilizing zero operational amplifier in the embodiment of the present disclosure adopts the self-stabilizing zero technique and the chopping technique at the same time, and on the basis of the self-stabilizing zero technique, the chopping technique is used to modulate the low-frequency aliasing noise to the chopping frequency, so as to obtain the low noise characteristic in the range from the direct current to the chopping frequency, and no additional filter circuit is needed, and the self-stabilizing zero employs the ping-pong architecture, so that no large off-chip capacitor is needed. Thus, the area is smaller and the power consumption is lower compared to existing solutions.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, it being understood that the drawings described below relate only to some embodiments of the present disclosure, and not to limit the present disclosure, wherein:
fig. 1 is an exemplary circuit diagram of a self-zeroing operational amplifier according to an embodiment of the present disclosure;
fig. 2 is a timing diagram for switches and choppers according to an embodiment of the disclosure.
The elements in the drawings are schematic and not drawn to scale.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below in detail and completely with reference to the accompanying drawings. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are also within the scope of protection of the disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate components.
In all embodiments of the present disclosure, in addition, terms such as "first" and "second" are used only to distinguish one component (or a part of a component) from another component (or another part of a component).
First, it should be noted that the self-zeroing operational amplifier in the embodiment of the present disclosure is a ping-pong operational amplifier that uses a chopping technique to reduce low-frequency aliasing noise. The low frequency aliasing noise is mainly caused by the difference between the sampling frequency and the bandwidth, and the specific input signal targeted by the embodiment of the present disclosure is a low frequency (Kb level) input signal, which is greatly different from the bandwidth frequency (Gb level) of the thermal noise, so that the thermal noise of a high frequency is aliased to a low frequency when sampling. The auto-zero operational amplifier of the embodiment of the disclosure specifically combines the advantages of the chopping technology and the auto-zero technology, wherein the auto-zero technology of the sampling ping-pang structure does not need a large off-chip capacitor, and on the basis of the auto-zero technology, the chopping technology is used for modulating low-frequency aliasing noise to the chopping frequency, so that the low noise characteristic in the range from direct current to the chopping frequency is obtained, and an additional filter circuit is not needed. The following description will be made in detail with reference to specific circuit configurations.
Fig. 1 shows an exemplary circuit diagram of a self-zeroing operational amplifier 10. In the example of fig. 1, the self-zeroing operational amplifier 10 includes: the main structure of the ping-pang self-stabilizing zero-setting amplifier comprises six switches S1, S2, S3, S4, S5 and S6, wherein the two first-stage amplifiers (A1 and A2) are also input stages, the second-stage amplifier A0 is also an output stage, and the ping-pang self-stabilizing zero-setting amplifier consists of two zero-setting amplifiers (A3 and A4). The four choppers (CH1, CH2, CH3, CH4) are to eliminate the increase of low frequency noise caused by the self-standing zero technique.
Specifically, as shown in fig. 1, an input end of a first chopper CH1 is connected to input signals (INN, INP), two output ends of a first chopper CH1 are connected to a non-inverting input end and an inverting input end of a first-stage amplifier a1, respectively, a non-inverting output end of the first-stage amplifier a1 is connected to a non-inverting input end of a first zeroing amplifier A3 after being connected to a second chopper CH2 and a second switch S2 in sequence, an inverting output end and an inverting output end of the first-stage amplifier a1 are connected to a second chopper CH2 and a third switch S3 in sequence, respectively, and are connected to an inverting input end of the first zeroing amplifier A3, a non-inverting output end and an inverting output end of the first zeroing amplifier A3 are feedback-connected to an inverting output end and a non-inverting output end of the first-stage amplifier a1, one end of a first switch S1 is connected between an output end of the first chopper CH1 and a non-inverting input end of the first-stage amplifier a1, the other end of the first switch S1 is connected between the other output end of the first chopper CH1 and the inverting input end of the first-stage amplifier A1, a first storage capacitor C1,One end of the second storage capacitor C2 is grounded, the other end of the first storage capacitor C1 is connected between the second switch S2 and the non-inverting input terminal of the first nulling amplifier A3, and the other end of the second storage capacitor C2 is connected between the third switch S3 and the inverting input terminal of the first nulling amplifier A3; the input end of a third chopper CH3 is connected with an input signal, two output ends of a third chopper CH3 are respectively connected with the non-inverting input end and the inverting input end of a second first-stage amplifier A2, the non-inverting output end of the second first-stage amplifier A2 is connected with a fourth chopper CH4 and a fifth switch S5 in sequence and then is connected with the non-inverting input end of a second zeroing amplifier A4, the inverting output end of the second first-stage amplifier A2 is connected with a fourth chopper CH4 and a sixth switch S6 in sequence and then is connected with the inverting input end of the second zeroing amplifier A4, the non-inverting output end and the inverting output end of a second zeroing amplifier A4 are respectively connected with the inverting output end and the non-inverting output end of the second first-stage amplifier A2 in a feedback manner, one end of a fourth switch S4 is connected between one output end of the third chopper CH3 and the non-inverting input end of the second first-stage amplifier A2, the other end of the fourth switch S4 is connected between the other output end of the third chopper CH3 and the inverting input end of the second first-stage amplifier a2, one ends of a third storage capacitor C3 and a fourth storage capacitor C4 are grounded, the other end of the third storage capacitor C3 is connected between the fifth switch S5 and the non-inverting input end of the second zeroing amplifier a4, and the other end of the fourth storage capacitor C4 is connected between the sixth switch S6 and the inverting input end of the second zeroing amplifier a 4; the output end of the second-stage amplifier A0 is a signal output end (V) OUT ) The non-inverting input terminal of the second stage amplifier a0 is connected between one output terminal of the second chopper CH2 and the second switch S2, one output terminal of the fourth chopper CH4 and the fifth switch S5, the inverting input terminal of the second stage amplifier a0 is connected between the other output terminal of the second chopper CH2 and the third switch S3, the other output terminal of the fourth chopper CH4 and the sixth switch S6, the output terminal of the second stage amplifier a0 is connected with the compensation capacitor C0 and then feedback-connected to the inverting input terminal of the second stage amplifier a0。
With reference to the circuit diagram of fig. 1, by switching the six switches, differential input signals are alternately modulated by the first chopper CH1 and the third chopper CH3, an input signal passing through the first chopper CH1 is amplified by the first-stage amplifier a1, demodulated by the second chopper CH2, output by the second-stage amplifier a0 after demodulation, an input signal passing through the third chopper CH3 is amplified by the second first-stage amplifier a2, demodulated by the fourth chopper CH4, and output by the second-stage amplifier a0 after demodulation; the input signal is a low-frequency differential signal; the first zeroing amplifier A3 alternatively stores and cancels the offset voltage of the first-stage amplifier A1 through a first storage capacitor C1 and a second storage capacitor C2, and the second zeroing amplifier A4 alternatively stores and cancels the offset voltage of the second first-stage amplifier A2 through a third storage capacitor C3 and a fourth storage capacitor C4; the second chopper CH2 and the fourth chopper CH4 alternately modulate low-frequency aliasing noise of the self-stabilizing zero operational amplifier during self-stabilizing zero sampling to a chopping frequency.
In the disclosed embodiment, for the open and close setting of six switches, refer specifically to the timing diagram of the switches provided in fig. 2. Specifically, the clock control signals of the first switch S1, the second switch S2 and the third switch S3 are the first clock signal Φ 1, the clock control signals of the fourth switch S4, the fifth switch S5 and the sixth switch S6 are the second clock signal Φ 2, and the first clock signal Φ 1 and the second clock signal Φ 2 are two-phase clock signals which are not overlapped. In addition, the four choppers also need to be controlled by a clock, specifically, a timing chart of the four choppers is shown in fig. 2, the clock control signals of the first chopper CH1 and the second chopper CH2 are a third clock signal Φ 3, the clock control signals of the third chopper CH3 and the fourth chopper CH4 are a fourth clock signal Φ 4, the periods of the third clock signal Φ 3, the fourth clock signal Φ 4, the first clock signal Φ 1, and the second clock signal Φ 2 are the same, the first clock signal Φ 1 and the fourth clock signal Φ 4 arrive at the same time, the duration of the first clock signal Φ 1 is twice the duration of the fourth clock signal Φ 4, the second clock signal Φ 2 and the third clock signal Φ 3 arrive at the same time, and the duration of the second clock signal Φ 2 is twice the duration of the third clock signal Φ 3.
The operation principle of the self-zeroing operational amplifier in the embodiment of the present disclosure is further explained with reference to the circuit diagram of fig. 1 and the timing diagram of fig. 2. When the switches S1, S2, and S3 are at high level, the input terminal of the input stage a1 is shorted, the output terminal thereof is connected to the input terminal of A3, and the output terminal of A3 is fed back to the output terminal of a1, so that the offset voltage (input offset voltage) of a1 is stored on the storage capacitors C1 and C2, so as to subtract in the next cycle, when the switches S1, S2, and S3 are at high level, S4, S5, and S6 are at low level, a2, a4, and a0 constitute an amplifier circuit (where the amplification of the signal is mainly due to a2 and a0, and a4 is used for zero adjustment, that is to cancel the offset voltage), the input signal is normally amplified, and the offset voltage (input offset voltage) of a2 is also cancelled by the offset voltage of a2 stored in C3 and C4 in the previous cycle; similarly, when the switches S4, S4 and S6 are at high level, the input terminal of the input stage a2 is shorted, the output terminal thereof is connected to the input terminal of a4, and the output terminal of a4 is fed back to the output terminal of a2, so that the offset voltage (input offset voltage) of a2 is stored in the storage capacitors C3 and C4, so as to be subtracted in the next cycle, and when the switches S4, S5 and S6 are at high level, S1, S2 and S3 are at low level, a1, A3 and a0 form an amplifier circuit (where the amplification of signals is mainly due to a1 and a0, and the function of A3 is to be zero adjustment, i.e. to cancel the offset voltage), and the input signal is normally amplified, and the offset voltage (input offset voltage) of a1 is also cancelled by the offset voltage of a1 stored in C1 and C2 in the previous cycle. This achieves a continuous time ping-pong self-zeroing amplifier and does not require a large off-chip capacitance. According to the timing diagram of the chopper in fig. 2, four choppers, wherein the clock signals of CH1 and CH2 are the same, CH1 and CH2 are operated when the switches S1, S2 and S3 are low, and the input signal is modulated and demodulated through CH1 and CH2 respectively; similarly, the clock signals of CH3 and CH4 are the same, when the switches S4, S5 and S6 are at low level, CH3 and CH4 operate, and the input signals are modulated and demodulated through CH3 and CH4 respectively; the elimination of the low-frequency aliasing noise is mainly realized by CH2 and CH4, and in addition, as can be seen from fig. 2, the chopping frequency is twice as high as the self-stabilizing zero frequency, so the aliasing noise with the low frequency is modulated at the chopping frequency, and the noise energy characteristic from direct current to the chopping frequency is very low. Since the self-zeroing technique has already eliminated most of the noise energy, the noise energy modulated at the chopping frequency is also relatively low here, so that no additional low-pass filter can be used.
In addition, it should be noted that, the difference between the voltages stored in the first storage capacitor C1 and the second storage capacitor C2 is equal to the transconductance of the first-stage amplifier a1 multiplied by the offset voltage of the first-stage amplifier a1 divided by the transconductance of the first zeroing amplifier A3, and a specific example is given for explanation: suppose the offset voltage of A1 is V os1 Then the difference between the voltages stored at C1, C2 is: (g) m1 *V os1 )/g m3 Wherein g is m1 ，g m3 Transconductance a1, A3.
Similarly, the difference between the voltages stored in the third storage capacitor C3 and the fourth storage capacitor C4 is equal to the transconductance of the second first-stage amplifier a2 multiplied by the offset voltage of the second first-stage amplifier a2 divided by the transconductance of the second zeroing amplifier a4, and a specific example is given for illustration: suppose the offset voltage of A2 is V os2 Then the difference between the voltages stored at C3, C4 is: (g) m2 *V os2 )/g m4 Wherein g is m2 ，g m4 Transconductance a2, a 4.
It should be further noted that, in order to make the capacitance stored in the storage capacitor more accurate and ensure the accuracy, it is necessary to satisfy that the transconductance of the first-stage amplifier a1 is greater than that of the first zeroing amplifier A3; similarly, the transconductance of the second first stage amplifier a2 is greater than the transconductance of the second nulling amplifier a 4. Preferably, the transconductance of the first-stage amplifier a1 is ten times that of the first nulling amplifier A3; the transconductance of the second first stage amplifier a2 is ten times that of the second nulling amplifier a 4.
In the embodiment of the present disclosure, in order to prevent excessive leakage and increase of circuit area, the capacitance values of the first storage capacitor, the second storage capacitor, the third storage capacitor, and the fourth storage capacitor cannot be too small or too large, and the capacitance ranges of the four storage capacitors in the preferred embodiment are greater than or equal to 10 picofarads and less than or equal to 20 picofarads.
Based on the above description of the self-stabilizing zero amplifier of the embodiments of the present disclosure, the embodiments of the present disclosure are applicable to sensor signals with high-precision and low-frequency input signals. The specific application can be in pressure sensors, temperature sensors and other applications requiring amplifiers with accurate current induction.
In summary, according to the self-stabilizing zero operational amplifier of the embodiment of the present disclosure, the chopping technique is used to reduce the low-frequency aliasing noise, no additional low-pass filter is needed, no large off-chip capacitor is needed, and the area is smaller.
According to the second aspect of the present disclosure, there is also provided a gain adjustable amplifier, which includes the self-zeroing operational amplifier 10 shown in fig. 1 and an external resistor, wherein the self-zeroing operational amplifier is connected to the external resistor with different resistance values (the external resistor is an external resistor relative to the self-zeroing operational amplifier) to adjust the gain. The self-stabilizing zero operational amplifier in fig. 1 is different from the instrumentation amplifier, and the instrumentation amplifier has a fixed gain, but the self-stabilizing zero operational amplifier in the embodiment of the present disclosure needs to be used in cooperation with an external resistor, so that a user can configure the gain according to the own requirement, and the configuration is very flexible.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when reference is made to the singular, it is generally intended to include the plural of the corresponding term. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "include" and "or" should be construed as inclusive unless such an interpretation is explicitly prohibited herein. Where the term "example" is used herein, particularly when it comes after a set of terms, it is merely exemplary and illustrative and should not be considered exclusive or extensive.
Further aspects and ranges of adaptability will become apparent from the description provided herein. It should be understood that various aspects of the present disclosure may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
Several embodiments of the present disclosure have been described in detail above, but it is apparent that various modifications and variations can be made to the embodiments of the present disclosure by those skilled in the art without departing from the spirit and scope of the present disclosure. The scope of the present disclosure is defined by the appended claims.
Claims (10)
1. A self-zeroing operational amplifier, comprising: the four choppers, two first-stage amplifiers, a second-stage amplifier, two zeroing amplifiers, four storage capacitors and six switches, wherein input signals are alternately modulated by the first chopper and the third chopper through the switching of the six switches, the input signals passing through the first chopper are amplified by the first-stage amplifier, demodulated by the second chopper and then output by the second-stage amplifier, the input signals passing through the third chopper are amplified by the second first-stage amplifier, amplified by the fourth chopper and demodulated by the second-stage amplifier; the input signal is a low-frequency differential signal;
the first zeroing amplifier alternately stores and offsets the offset voltage of the first-stage amplifier through a first storage capacitor and a second storage capacitor, and the second zeroing amplifier alternately stores and offsets the offset voltage of the second first-stage amplifier through a third storage capacitor and a fourth storage capacitor;
the second chopper and the fourth chopper alternately modulate low-frequency aliasing noise of the self-stabilizing zero operational amplifier in the self-stabilizing zero sampling process to a chopping frequency.
2. The self-stabilizing operational amplifier as claimed in claim 1, wherein the input terminal of the first chopper is connected to an input signal, the two output terminals of the first chopper are respectively connected to the non-inverting input terminal and the inverting input terminal of the first stage amplifier, the non-inverting output terminal of the first stage amplifier is connected to the non-inverting input terminal of the first zeroing amplifier after being sequentially connected to the second chopper and the second switch, the inverting output terminal of the first stage amplifier is connected to the inverting input terminal of the first zeroing amplifier after being sequentially connected to the second chopper and the third switch, the non-inverting output terminal and the inverting output terminal of the first zeroing amplifier are respectively feedback-connected to the inverting output terminal and the non-inverting output terminal of the first stage amplifier, and one terminal of the first switch is connected to one output terminal of the first chopper and the first stage amplifier The other end of the first switch is connected between the other output end of the first chopper and the inverting input end of the first-stage amplifier, one ends of the first storage capacitor and the second storage capacitor are grounded, the other end of the first storage capacitor is connected between the second switch and the non-inverting input end of the first zeroing amplifier, and the other end of the second storage capacitor is connected between the third switch and the inverting input end of the first zeroing amplifier;
the input end of the third chopper is connected with an input signal, two output ends of the third chopper are respectively connected with the positive phase input end and the negative phase input end of the second first-stage amplifier, the positive phase output end of the second first-stage amplifier is sequentially connected with the fourth chopper and the fifth switch and then is connected with the positive phase input end of the second zeroing amplifier, the negative phase output end of the second first-stage amplifier is sequentially connected with the fourth chopper and the sixth switch and then is connected with the negative phase input end of the second zeroing amplifier, the positive phase output end and the negative phase output end of the second zeroing amplifier are respectively connected with the negative phase output end and the positive phase output end of the second first-stage amplifier in a feedback way, and one end of the fourth switch is connected between one output end of the third chopper and the positive phase input end of the second first-stage amplifier, the other end of the fourth switch is connected between the other output end of the third chopper and the inverting input end of the second first-stage amplifier, one ends of the third storage capacitor and the fourth storage capacitor are grounded, the other end of the third storage capacitor is connected between the fifth switch and the non-inverting input end of the second zeroing amplifier, and the other end of the fourth storage capacitor is connected between the sixth switch and the inverting input end of the second zeroing amplifier;
the output end of the second-stage amplifier is a signal output end, the positive phase input end of the second-stage amplifier is respectively connected between one output end of the second chopper and the second switch, one output end of the fourth chopper and the fifth switch, the negative phase input end of the second-stage amplifier is respectively connected between the other output end of the second chopper and the third switch, the other output end of the fourth chopper and the sixth switch, and the output end of the second-stage amplifier is connected with a compensation capacitor and then is connected to the negative phase input end of the second-stage amplifier in a feedback mode.
3. The self-stabilizing operational amplifier of claim 2, wherein the clock control signals of the first switch, the second switch and the third switch are first clock signals, the clock control signals of the fourth switch, the fifth switch and the sixth switch are second clock signals, and the first clock signal and the second clock signal are two non-overlapping clock signals.
4. The operational amplifier of claim 3, wherein the clock control signals of the first chopper and the second chopper are a third clock signal, the clock control signals of the third chopper and the fourth chopper are a fourth clock signal, the periods of the third clock signal, the fourth clock signal, the first clock signal and the second clock signal are the same, the first clock signal and the fourth clock signal arrive at the same time, the duration of the first clock signal is twice the duration of the fourth clock signal, the second clock signal and the third clock signal arrive at the same time, and the duration of the second clock signal is twice the duration of the third clock signal.
5. An auto-zeroed operational amplifier according to claim 2, wherein the difference between the voltages stored on the first storage capacitor and the second storage capacitor is equal to the transconductance of the first stage amplifier multiplied by the offset voltage of the first stage amplifier divided by the transconductance of the first zeroing amplifier; the difference between the voltages stored on the third storage capacitor and the fourth storage capacitor is equal to the transconductance of the second first-stage amplifier multiplied by the offset voltage of the second first-stage amplifier divided by the transconductance of the second nulling amplifier.
6. The self-stabilizing operational amplifier of claim 5, wherein the transconductance of the first stage amplifier is greater than the transconductance of the first nulling amplifier; the transconductance of the second first-stage amplifier is greater than the transconductance of the second nulling amplifier.
7. The self-zeroing operational amplifier of claim 6, wherein the transconductance of the first stage amplifier is ten times the transconductance of the first nulling amplifier; the transconductance of the second first-stage amplifier is ten times that of the second nulling amplifier.
8. The self-stabilizing operational amplifier of claim 2, wherein the capacitance ranges of the first storage capacitor, the second storage capacitor, the third storage capacitor and the fourth storage capacitor are greater than or equal to 10 picofarads and less than or equal to 20 picofarads.
9. The self-standing zero operational amplifier of claim 1, wherein the input signal is a high precision sensor signal.
10. A gain-adjustable amplifier, characterized in that the gain-adjustable amplifier comprises the self-zeroing operational amplifier of any one of claims 1 to 9 and an external resistor, and the self-zeroing operational amplifier is connected to the external resistors with different resistance values to adjust the gain.
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