CN114977972A - Motor control method and device and vehicle - Google Patents

Abstract

The invention discloses a motor control method, a motor control device and a vehicle. Acquiring a torque instruction obtained on a communication bus; determining a voltage vector instruction according to the torque instruction and the three-phase current of the motor; determining a pulse width modulation signal waveform according to the voltage vector instruction; and filtering narrow pulses in the pulse width modulation signal according to the pulse width modulation signal waveforms of two continuous periods. On the basis of not increasing the hardware cost, narrow pulses in all periodic pulse width modulation signals are filtered, the power loss of a motor driving system is reduced, larger surge voltage peak and oscillation are avoided, and the service life of the motor is prolonged.

Description

A motor control method, device and vehicle

technical field

The present invention relates to the technical field of motor control, and in particular, to a motor control method, device and vehicle.

Background technique

With the rapid development of the electric vehicle industry and the increasingly mature inverter technology, the requirements for the efficiency and energy density of the electric drive system are also getting higher and higher. At present, the mainstream of the inverter of the electric drive system adopts the insulated gate bipolar transistor IGBT module as the switching device. Both the turn-on and turn-off processes of the IGBT take a certain amount of time. In order to protect the IGBT from the pass-through of the upper and lower bridge arms, the dead time is usually increased. In addition, the turn-on and turn-off pulses with too short duration will not only fail to generate effective turn-on or turn-off, resulting in additional power loss, but also cause large surge voltage spikes and oscillations in the IGBT switching devices, threatening the reliable operation of the IGBT. , reduce the life of IGBT, and even cause electrical damage directly. In order to protect the IGBT and increase the life of the device, the narrow pulse suppression function is generally added.

There are two main methods for filtering out narrow pulses in the prior art:

1. The use of CPLD (Complex Programmable Logic Device) to suppress narrow pulse signals requires the use of more CPLD resources. If the CPLD resource capacity is not enough to filter out small pulse signals, the large-capacity CPLD chip needs to be replaced, which increases the system cost;

2. The DSP software forces the PWM module to output 100% or 0% duty cycle when the duty cycle is less than or greater than the duty cycle corresponding to the minimum pulse width; when the duty cycle is 100% or 0%, the output pulse width is Half of the maximum pulse width of the two pulses before and after the cycle, the output pulse width is still less than the minimum pulse width recommended by the manufacturer; DSP software is required to control the duty cycle value corresponding to twice the minimum pulse width to filter out, and the filter pulse width is large, which affects the inverter. performance; and TI's C2000 series digital signal processor cannot output 100% or 0% duty cycle, which affects the realization of software control.

SUMMARY OF THE INVENTION

The present invention provides a motor control method, device and vehicle to solve the problem that narrow pulses of all periods cannot be suppressed on the basis of not increasing the hardware cost when suppressing narrow pulses in the prior art.

According to an aspect of the present invention, there is provided a motor control method, the method comprising:

Get the torque command obtained on the communication bus;

Determine the voltage vector command according to the torque command and the three-phase current of the motor;

According to the voltage vector command, determine the pulse width modulation signal waveform;

The narrow pulses in the pulse width modulation signal are filtered out according to the waveform of the pulse width modulation signal for two consecutive cycles.

Optionally, the motor controller includes a three-phase bridge circuit, and the three-phase bridge circuit includes an upper bridge arm and a lower bridge arm;

Filtering out narrow pulses in the PWM signal according to the PWM signal waveform of two consecutive cycles includes:

determining a first waveform corresponding to the upper bridge arm and a second waveform corresponding to the lower bridge arm according to the PWM signal waveform of each cycle;

determining the interval where the pulse width modulation command is located according to the first waveform and the second waveform;

Filter out the narrow pulses in the pulse width modulation signal according to the interval in which the pulse width modulation command of the previous cycle and the current cycle is located and the preset duty cycle condition.

Optionally, according to the first waveform and the second waveform, determine the interval where the pulse width modulation instruction is located, including:

When 0≤Dm<0.5Dp, Dt=0, Db=1, the pulse width modulation command is in the first interval;

When 0.5Dp≤Dm<Dd, Dt=0, Db=1-2Dm, the pulse width modulation command is in the second interval;

When Dd≤Dm<1-Dd, Dt=Dm-Dd, Db=1-Dm-Dd, the pulse width modulation command is in the third interval;

When 1-Dd≤Dm<1, Dt=2Dm-1, Db=0, the pulse width modulation command is in the fourth interval;

When Dm=1, Dt=1, Db=0, the pulse width modulation command is in the fifth interval;

Among them, Dt represents the duty cycle of the first level of the upper bridge arm, Db represents the duty cycle of the first level of the lower bridge arm, Dm represents the duty cycle command from the space vector pulse width modulation module, Dd represents the dead time, Dp Indicates the narrow pulse time.

Optionally, filter out narrow pulses in the pulse width modulation signal according to the interval where the pulse width modulation commands of the previous cycle and the current cycle are located and the preset duty cycle conditions, including:

When the duty cycle of the previous cycle is in the first interval and the duty cycle of the current cycle is in the first interval or the duty cycle of the previous cycle is in the first interval and the duty cycle of the current cycle is in the second interval or the duty cycle of the previous cycle is in the first interval and the duty cycle of the current cycle is in the third interval or the duty cycle of the previous cycle is in the second interval and the duty cycle of the current cycle is in the first interval or the duty cycle of the previous cycle is in the second interval and the duty cycle of the current cycle is in the second interval or the duty cycle of the previous cycle is in the second interval and the duty cycle of the current cycle is in the third interval or the duty cycle of the previous cycle is in the third interval and the duty cycle of the current cycle is in the first interval or the duty cycle of the previous cycle is in the third interval and the duty cycle of the current cycle is in the second interval or the duty cycle of the previous cycle is in the third interval and the duty cycle of the current cycle is in the third interval and Db1+Db2≥2Dp or the duty cycle of the previous cycle is in the fifth interval and the duty cycle of the current cycle When in the fourth interval and 1-Dm2<Dp or the duty cycle of the previous cycle is in the fifth interval and the duty cycle of the current cycle is in the fifth interval, the original signal is directly output;

When the duty cycle of the previous cycle is in the first interval and the duty cycle of the current cycle is in the fourth interval or the duty cycle of the previous cycle is in the first interval and the duty cycle of the current cycle is in the fifth interval or the duty cycle of the previous cycle is in the second interval and the duty cycle of the current cycle is in the fourth interval or the duty cycle of the previous cycle is in the second interval and the duty cycle of the current cycle is in the fifth interval Or the duty cycle of the previous cycle is in the third interval and the duty cycle of the current cycle is in the fourth interval and 1-Dm1-Dd1≥2Dp or the duty cycle of the previous cycle is in the third interval and the current cycle occupies The duty cycle is in the fifth interval and 1-Dm1-Dd1≥2Dp or the previous cycle duty cycle is in the fourth interval and the current cycle duty cycle is in the fourth interval and 2-Dm1-Dm2≥Dp or When the duty cycle of the previous cycle is in the fourth interval and the duty cycle of the current cycle is in the fifth interval and 1-Dm1≥Dp, after increasing the upper bridge arm of the current cycle by a second level of dead time, then set the level to the first level;

When the duty cycle of the previous cycle is in the third interval and the duty cycle of the current cycle is in the third interval and Db1+Db2<2Dp, the first level formed by splicing the middle two cycles of the lower bridge arm cancel, continue to output the second level;

When the duty cycle of the previous cycle is in the third interval and the duty cycle of the current cycle is in the fourth interval and 1-Dm1-Dd1<2Dp or the duty cycle of the previous cycle is in the third interval and the current cycle is in the fourth interval When the duty ratio is in the fifth interval and 1-Dm1-Dd1<2Dp, cancel the first level in the middle of the lower bridge arm in the previous cycle, and continuously output the second level;

When the duty cycle of the previous cycle is in the fourth interval and the duty cycle of the current cycle is in the first interval or the duty cycle of the previous cycle is in the fourth interval and the duty cycle of the current cycle is in the second interval Or the duty cycle of the previous cycle is in the fourth interval and the duty cycle of the current cycle is in the third interval and 1-Dm2-Dd2≥2Dp or the duty cycle of the previous cycle is in the fifth interval and the current cycle occupies The duty cycle is in the first interval or the duty cycle of the previous cycle is in the fifth interval and the duty cycle of the current cycle is in the second interval or the duty cycle of the previous cycle is in the fifth interval and the duty cycle of the current cycle is in the fifth interval. When the duty ratio is in the third interval and 1-Dm2-Dd2 ≥ 2Dp, advance the turn-off time of the upper bridge arm in the previous cycle to the second level state of the dead time;

When the duty cycle of the previous cycle is in the fourth interval and the duty cycle of the current cycle is in the third interval and 1-Dm2-Dd2<2Dp or the duty cycle of the previous cycle is in the fifth interval and the current cycle is in the third interval When the duty ratio is in the third interval and 1-Dm2-Dd2<2Dp, cancel the first level in the middle of the bridge arm in the current cycle, and continue to output the second level;

When the duty cycle of the previous cycle is in the fourth interval and the duty cycle of the current cycle is in the fourth interval and 2-Dm1-Dm2<Dp, the second cycle formed by splicing the middle two cycles of the upper bridge arm The level is canceled, and the first level is continuously output;

When the duty cycle of the previous cycle is in the fourth interval and the duty cycle of the current cycle is in the fifth interval and 1-Dm1<Dp, the turn-off time of the upper bridge arm of the previous cycle is delayed, and the output the first level until the current cycle;

When the duty cycle of the previous cycle is in the fifth interval and the duty cycle of the current cycle is in the fourth interval and 1-Dm2<Dp, advance the turn-off time of the upper bridge arm of the current cycle, from the end of the previous cycle and then continuously outputting the first level;

Wherein, the voltage of the first level is greater than the voltage of the second level.

Optionally, before determining the voltage vector command according to the torque command and the three-phase current of the motor, the method further includes:

Data processing is performed on the torque command.

Optionally, performing data processing on the torque command includes:

Debounce the torque command, limit the slope, and smoothly switch between different control modes.

Optionally, the width of the narrow pulse is less than or equal to 2 μs.

Optionally, the width of the dead time is 2 μs˜5 μs.

According to another aspect of the present invention, a motor device is provided, the motor device comprising: an acquisition module for acquiring a torque command obtained on a communication bus;

a voltage vector command determination module, configured to determine the voltage vector command according to the torque command and the three-phase current of the motor;

a waveform determination module, configured to determine the pulse width modulation signal waveform according to the voltage vector instruction;

The processing module is configured to filter out narrow pulses in the pulse width modulation signal according to the pulse width modulation signal waveform of two consecutive cycles.

According to another aspect of the present invention, there is provided a vehicle equipped with the above-described motor device.

According to the technical scheme of the embodiment of the present invention, the torque command obtained on the communication bus is obtained; the voltage vector command is determined according to the torque command and the three-phase current of the motor; the pulse width modulation signal waveform is determined according to the voltage vector command; PWM signal waveform, filtering out narrow pulses in the PWM signal. On the basis of not increasing the hardware cost, the narrow pulses in all periodic PWM signals are filtered out, which reduces the power loss of the motor drive system, avoids large surge voltage peaks and oscillations, and increases the life of the motor.

It should be understood that the content described in this section is not intended to identify key or critical features of the embodiments of the invention, nor is it intended to limit the scope of the invention. Other features of the present invention will become readily understood from the following description.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

1 is a schematic structural diagram of a vehicle motor system according to Embodiment 1 of the present invention;

FIG. 2 is a flowchart of a motor control method provided in Embodiment 1 of the present invention;

3 is a schematic diagram of a three-phase bridge circuit according to Embodiment 2 of the present invention;

FIG. 4 is a flowchart of a motor control method provided in Embodiment 2 of the present invention;

5A-5E are pulse width modulation command interval diagrams provided by Embodiment 2 of the present invention;

6A-6H are schematic diagrams of comparison before and after narrow pulse suppression in the pulse width modulated signal provided by Embodiment 2 of the present invention;

FIG. 7 is a schematic structural diagram of a motor device according to Embodiment 3 of the present invention.

Detailed ways

In order to make those skilled in the art better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only Embodiments are part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

It should be noted that the terms "first", "second" and the like in the description and claims of the present invention and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used may be interchanged under appropriate circumstances such that the embodiments of the invention described herein can be practiced in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having" and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those expressly listed Rather, those steps or units may include other steps or units not expressly listed or inherent to these processes, methods, products or devices.

Example 1

Embodiment 1 of the present invention provides a motor control method, and the method can be executed by a motor device, and the motor device can be provided in a vehicle.

Optionally, FIG. 1 is a schematic structural diagram of a vehicle motor system according to Embodiment 1 of the present invention.

As shown in Figure 1, the vehicle motor control system includes the following parts: a motor controller 1, a motor under test equipped with a resolver 2 (resolver) as a position sensor 3, a high-voltage power supply 4, a low-voltage power supply 5, CAN control command 6 (Controller Area Network, CAN), IG signal 7 (ignition signal) and so on. Among them, the motor controller is composed of a control board, a drive board and an IGBT, which is connected to all other parts; the high-voltage power supply 4 provides high-voltage power supply for the entire system to control the rotation of the motor 3 under test; the low-voltage control power supply 5 is the motor controller 1. The internal control board supplies power, performs signal calculation, and provides corresponding drive signals; CAN control command 6 refers to the CAN signal from other controllers of the vehicle. When the motor system is on the test bench, this part can also refer to the signal from the upper IG signal 7, etc. refer to all other signals required for the operation of other motor systems, such as the IG switch signal from the vehicle, the airbag collision signal, and the like.

FIG. 2 is a flowchart of a motor control method according to Embodiment 1 of the present invention.

With reference to FIG. 1 and FIG. 2 , the motor control method provided by the embodiment of the present invention includes the following steps:

S110. Acquire the torque command obtained on the communication bus.

Specifically, the communication bus may be a CAN bus (Controller Area Network), and the control board on the motor controller obtains the torque command signal on the CAN bus.

S120: Determine the voltage vector command according to the torque command and the three-phase current of the motor.

Specifically, the three-phase current of the motor is obtained by actual measurement. When the motor controller works in the non-weakening region, the MTPA (maximum torque current ratio control) control method is adopted at this time, and the id and iq commands are obtained by looking up the table according to the torque command, and closed-loop control is performed respectively. With the increase of the motor speed or the increase of the torque command or the decrease of the bus voltage, the working point of the motor will gradually approach the field weakening area. When the difference between the calculated voltage vector and the bus voltage/sqrt(3) is less than a certain value (eg 5V, different systems are selected according to the test effect), the control mode is switched from MTPA current control to voltage vector control. When in the voltage vector control mode, the voltage vector command amplitude set by the inverter is the bus voltage/sqrt(3), and the phase angle of the voltage vector command is obtained according to the closed-loop control of the command torque and the actual torque. The actual torque used for closed-loop control is calculated from information such as motor three-phase current, rotor position angle, and motor parameters.

S130. Determine the pulse width modulation signal waveform according to the voltage vector command.

Specifically, the control board obtains 6-channel pulse width modulation signal waveform signals through calculation according to the voltage vector command, and transmits it to the driving board.

S140. Filter out narrow pulses in the pulse width modulation signal according to the pulse width modulation signal waveforms of two consecutive cycles.

Specifically, according to the characteristics of the IGBT, the driver board performs level conversion and necessary signal processing on the 6-channel pulse width modulation signal waveform signal output by the control board for two consecutive cycles, which is used to drive the IGBT, so that the output waveform of the IGBT is consistent with the control board. The output pulse width modulation signal has the same waveform, thereby filtering out the narrow pulses in the pulse width modulation signal.

Optionally, the width of the narrow pulse is less than or equal to 2 μs.

According to the technical scheme of the embodiment of the present invention, the torque command obtained on the communication bus is obtained; the voltage vector command is determined according to the torque command and the three-phase current of the motor; the pulse width modulation signal waveform is determined according to the voltage vector command; The pulse width modulation signal waveform, filtering out the narrow pulses in the pulse width modulation signal. On the basis of not increasing the hardware cost, the narrow pulses in all periodic PWM signals are filtered out, which reduces the power loss of the motor drive system, avoids large surge voltage peaks and oscillations, and increases the life of the motor.

Embodiment 2

Optionally, FIG. 3 is a schematic diagram of a three-phase bridge circuit provided in Embodiment 2 of the present invention. The three-phase bridge circuit is set in the vehicle motor system in Embodiment 1, wherein A, B, and C represent three-phase power supplies, VT means thyristor, PMSM means motor, and U _d means voltage. As shown in FIG. 3 , the three-phase bridge circuit includes an upper bridge arm and a lower bridge arm.

FIG. 4 is a flowchart of a motor control method provided by the second embodiment of the present invention. On the basis of the above-mentioned embodiment, it exemplarily shows a method for filtering out pulses according to the pulse width modulation signal waveform of two consecutive cycles. Embodiments of Narrow Pulses in Width Modulated Signals.

With reference to FIG. 3 and FIG. 4 , the motor control method provided by the embodiment of the present invention includes the following steps:

S210. Acquire the torque command obtained on the communication bus.

S220: Determine the voltage vector command according to the torque command and the three-phase current of the motor.

S230. Determine the pulse width modulation signal waveform according to the voltage vector command.

S241. Determine the first waveform corresponding to the upper bridge arm and the second waveform corresponding to the lower bridge arm according to the pulse width modulation signal waveform of each cycle.

S242. Determine the interval where the pulse width modulation instruction is located according to the first waveform and the second waveform.

Specifically, FIGS. 5A-5E are the pulse width modulation command interval diagrams provided by the second embodiment of the present invention, wherein H and L represent high level and low level respectively. In one embodiment, H and L represent the first power level respectively. level and second level.

As shown in FIG. 5A, when 0≤Dm<0.5Dp, Dt=0, Db=1, and the pulse width modulation command is in the first interval;

As shown in FIG. 5B, when 0.5Dp≤Dm<Dd, Dt=0, Db=1-2Dm, and the pulse width modulation command is in the second interval;

As shown in FIG. 5C, when Dd≤Dm<1-Dd, Dt=Dm-Dd, Db=1-Dm-Dd, and the pulse width modulation command is in the third interval;

As shown in FIG. 5D, when 1-Dd≤Dm<1, Dt=2Dm-1, Db=0, and the pulse width modulation command is in the fourth interval;

As shown in FIG. 5E, when Dm=1, Dt=1, Db=0, the pulse width modulation command is in the fifth interval;

Among them, Dt represents the duty cycle of the first level of the upper bridge arm, Db represents the duty cycle of the first level of the lower bridge arm, Dm represents the duty cycle command from the space vector pulse width modulation module, Dd represents the dead time, Dp Indicates the narrow pulse time.

Optionally, the width of the dead time is 2 μs˜5 μs.

S243. Filter out narrow pulses in the pulse width modulation signal according to the interval in which the pulse width modulation command of the previous cycle and the current cycle is located and the preset duty cycle condition.

Specifically, FIGS. 6A-6H are schematic diagrams of comparison before and after narrow pulse suppression in the pulse width modulated signal provided by Embodiment 2 of the present invention, wherein H and L represent the first level (high level) and the second level ( low level).

When the duty cycle of the previous cycle is in the first interval and the duty cycle of the current cycle is in the first interval or the duty cycle of the previous cycle is in the first interval and the duty cycle of the current cycle is in the second interval or the duty cycle of the previous cycle is in the first interval The first interval and the duty cycle of the current cycle is in the third interval or the duty cycle of the previous cycle is in the second interval and the duty cycle of the current cycle is in the first interval or the duty cycle of the previous cycle is in the second interval and the duty cycle of the current cycle is in the second interval The ratio is in the second interval or the duty cycle of the previous cycle is in the second interval and the duty cycle of the current cycle is in the third interval or the duty cycle of the previous cycle is in the third interval and the duty cycle of the current cycle is in the first interval or the previous cycle The duty cycle of the cycle is in the third interval and the duty cycle of the current cycle is in the second interval or the duty cycle of the previous cycle is in the third interval and the duty cycle of the current cycle is in the third interval and Db1+Db2≥2Dp or the duty cycle of the previous cycle is in the third interval When the duty cycle is in the fifth interval and the current cycle duty cycle is in the fourth interval and 1-Dm2<Dp or the previous cycle duty cycle is in the fifth interval and the current cycle duty cycle is in the fifth interval, no post-processing is required. The original signal is output directly.

As shown in FIG. 6A , when the duty cycle of the previous cycle is in the first interval and the duty cycle of the current cycle is in the fourth interval or the duty cycle of the previous cycle is in the first interval and the duty cycle of the current cycle is in the fifth interval or above The duty cycle of one cycle is in the second interval and the duty cycle of the current cycle is in the fourth interval or the duty cycle of the previous cycle is in the second interval and the duty cycle of the current cycle is in the fifth interval or the duty cycle of the previous cycle is in the third interval interval and the duty cycle of the current cycle is in the fourth interval and 1-Dm1-Dd1≥2Dp or the duty cycle of the previous cycle is in the third interval and the duty cycle of the current cycle is in the fifth interval and 1-Dm1-Dd1≥2Dp or above One cycle duty cycle is in the fourth interval and the current cycle duty cycle is in the fourth interval and 2-Dm1-Dm2≥Dp or the previous cycle duty cycle is in the fourth interval and the current cycle duty cycle is in the fifth interval and 1 When -Dm1≥Dp, the upper bridge arm of the current cycle is increased by a second level of dead time, and then the level is set to the first level.

As shown in FIG. 6B, when the duty cycle of the previous cycle is in the third interval and the duty cycle of the current cycle is in the third interval and Db1+Db2<2Dp, the first level formed by splicing the middle two cycles of the lower bridge arm Cancel, continue to output the second level.

As shown in FIG. 6C , when the duty cycle of the previous cycle is in the third interval and the duty cycle of the current cycle is in the fourth interval and 1-Dm1-Dd1<2Dp or the duty cycle of the previous cycle is in the third interval and the current cycle occupies When the duty ratio is in the fifth interval and 1-Dm1-Dd1<2Dp, the first level in the middle of the lower bridge arm of the previous cycle is canceled, and the second level is continuously output.

As shown in FIG. 6D , when the duty cycle of the previous cycle is in the fourth interval and the duty cycle of the current cycle is in the first interval or the duty cycle of the previous cycle is in the fourth interval and the duty cycle of the current cycle is in the second interval or above The duty cycle of one cycle is in the fourth interval and the duty cycle of the current cycle is in the third interval and 1-Dm2-Dd2≥2Dp or the duty cycle of the previous cycle is in the fifth interval and the duty cycle of the current cycle is in the first interval or above When the duty cycle of one cycle is in the fifth interval and the duty cycle of the current cycle is in the second interval or the duty cycle of the previous cycle is in the fifth interval and the duty cycle of the current cycle is in the third interval and 1-Dm2-Dd2≥2Dp, A second level state that advances the turn-off time of the upper arm of the previous cycle by one dead time.

As shown in FIG. 6E , when the duty cycle of the previous cycle is in the fourth interval and the duty cycle of the current cycle is in the third interval and 1-Dm2-Dd2<2Dp or the duty cycle of the previous cycle is in the fifth interval and the current cycle is in the third interval When the duty ratio is in the third interval and 1-Dm2-Dd2<2Dp, the first level in the middle of the bridge arm in the current cycle is canceled, and the second level is continuously output.

As shown in FIG. 6F , when the duty cycle of the previous cycle is in the fourth interval and the duty cycle of the current cycle is in the fourth interval and 2-Dm1-Dm2<Dp, the second cycle formed by splicing the middle two cycles of the upper bridge arm The level is canceled, and the first level is continuously output.

As shown in FIG. 6G , when the duty cycle of the previous cycle is in the fourth interval and the duty cycle of the current cycle is in the fifth interval and 1-Dm1<Dp, the turn-off time of the upper bridge arm of the previous cycle is delayed for a continuous period of time. The first level is output until the current cycle.

As shown in Fig. 6H, when the duty cycle of the previous cycle is in the fifth interval and the duty cycle of the current cycle is in the fourth interval and 1-Dm2<Dp, the turn-off time of the upper bridge arm of the current cycle is advanced, and from the previous cycle After the end, the first level is continuously output.

Further, when determining the voltage vector command according to the torque command and the three-phase current of the motor, the method further includes: performing data processing on the torque command. Wherein, performing data processing on the torque command includes, but is not limited to, performing debounce, slope limitation, and smooth switching between different control modes on the torque command.

In the embodiment of the present invention, the torque command obtained on the communication bus is obtained, the voltage vector command is determined according to the torque command and the three-phase current of the motor, the pulse width modulation signal waveform is determined according to the voltage vector command, and the pulse width modulation signal waveform is determined according to the pulse width modulation signal of each cycle. Waveform, determine the first waveform corresponding to the upper bridge arm and the second waveform corresponding to the lower bridge arm, determine the interval where the pulse width modulation command is located according to the first waveform and the second waveform, and determine the interval where the pulse width modulation command is located according to the pulse width modulation of the previous cycle and the current cycle The interval in which the command is located and the preset duty cycle condition filter out the narrow pulses in the PWM signal. By determining the interval where the pulse width modulation command is located according to the waveform of the pulse width modulation signal of each cycle, the dead time is added in different intervals according to different rules. The narrow pulse reduces the power loss of the motor drive system, avoids large surge voltage peaks and oscillations, and increases the life of the motor.

Embodiment 3

FIG. 7 is a schematic structural diagram of a motor device according to Embodiment 3 of the present invention. As shown in Figure 7, the device 10 includes:

an acquisition module 11 for acquiring the torque command obtained on the communication bus;

The voltage vector command determination module 12 is used for determining the voltage vector command according to the torque command and the three-phase current of the motor;

The waveform determination module 13 is used for determining the pulse width modulation signal waveform according to the voltage vector command;

The processing module 14 is configured to filter out narrow pulses in the pulse width modulation signal according to the pulse width modulation signal waveform of two consecutive cycles.

Optionally, the device further includes an interval determination module, configured to determine an interval in which the pulse width modulation instruction is located according to the first waveform and the second waveform.

Specifically, when 0≤Dm<0.5Dp, Dt=0, Db=1, and the pulse width modulation command is in the first interval;

When 0.5Dp≤Dm<Dd, Dt=0, Db=1-2Dm, the pulse width modulation command is in the second interval;

When Dd≤Dm<1-Dd, Dt=Dm-Dd, Db=1-Dm-Dd, the pulse width modulation command is in the third interval;

When 1-Dd≤Dm<1, Dt=2Dm-1, Db=0, the pulse width modulation command is in the fourth interval;

When Dm=1, Dt=1, Db=0, the pulse width modulation command is in the fifth interval;

Among them, Dt represents the duty cycle of the first level of the upper bridge arm, Db represents the duty cycle of the first level of the lower bridge arm, Dm represents the duty cycle command from the space vector pulse width modulation module, Dd represents the dead time, Dp Indicates the narrow pulse time.

Optionally, the processing module 14 may also be configured to filter out narrow pulses in the pulse width modulation signal according to the interval in which the pulse width modulation command of the previous cycle and the current cycle is located and the preset duty cycle condition.

Specifically, when the duty cycle of the previous cycle is in the first interval and the duty cycle of the current cycle is in the first interval or the duty cycle of the previous cycle is in the first interval and the duty cycle of the current cycle is in the second interval or the duty cycle of the previous cycle is in the second interval The duty cycle is in the first interval and the duty cycle of the current cycle is in the third interval or the duty cycle of the previous cycle is in the second interval and the duty cycle of the current cycle is in the first interval or the duty cycle of the previous cycle is in the second interval and the current cycle is in the second interval. The duty cycle of the cycle is in the second interval or the duty cycle of the previous cycle is in the second interval and the duty cycle of the current cycle is in the third interval or the duty cycle of the previous cycle is in the third interval and the duty cycle of the current cycle is in the first interval Or the duty cycle of the previous cycle is in the third interval and the duty cycle of the current cycle is in the second interval or the duty cycle of the previous cycle is in the third interval and the duty cycle of the current cycle is in the third interval and Db1+Db2≥2Dp or above When the duty cycle of one cycle is in the fifth interval and the duty cycle of the current cycle is in the fourth interval and 1-Dm2<Dp or the duty cycle of the previous cycle is in the fifth interval and the duty cycle of the current cycle is in the fifth interval, no need for any After processing, the original signal is directly output.

When the duty cycle of the previous cycle is in the first interval and the duty cycle of the current cycle is in the fourth interval or the duty cycle of the previous cycle is in the first interval and the duty cycle of the current cycle is in the fifth interval or the duty cycle of the previous cycle is in the The second interval and the duty cycle of the current cycle is in the fourth interval or the duty cycle of the previous cycle is in the second interval and the duty cycle of the current cycle is in the fifth interval or the duty cycle of the previous cycle is in the third interval and the duty cycle of the current cycle is in the third interval The ratio is in the fourth interval and 1-Dm1-Dd1≥2Dp or the duty cycle of the previous cycle is in the third interval and the duty cycle of the current cycle is in the fifth interval and 1-Dm1-Dd1≥2Dp or the duty cycle of the previous cycle is in the The fourth interval and the current cycle duty cycle is in the fourth interval and 2-Dm1-Dm2≥Dp or when the previous cycle duty cycle is in the fourth interval and the current cycle duty cycle is in the fifth interval and 1-Dm1≥Dp, After adding a second level of dead time to the upper bridge arm of the current cycle, the level is set to the first level.

When the duty cycle of the previous cycle is in the third interval and the duty cycle of the current cycle is in the third interval and Db1+Db2<2Dp, the first level formed by splicing the middle two cycles of the lower arm is cancelled, and the second level is continuously output. level.

When the duty cycle of the previous cycle is in the third interval and the duty cycle of the current cycle is in the fourth interval and 1-Dm1-Dd1<2Dp or the duty cycle of the previous cycle is in the third interval and the duty cycle of the current cycle is in the fifth interval And when 1-Dm1-Dd1<2Dp, the first level in the middle of the lower bridge arm in the previous cycle is canceled, and the second level is continuously output.

When the duty cycle of the previous cycle is in the fourth interval and the duty cycle of the current cycle is in the first interval or the duty cycle of the previous cycle is in the fourth interval and the duty cycle of the current cycle is in the second interval or the duty cycle of the previous cycle is in the The fourth interval and the duty cycle of the current cycle is in the third interval and 1-Dm2-Dd2≥2Dp or the duty cycle of the previous cycle is in the fifth interval and the duty cycle of the current cycle is in the first interval or the duty cycle of the previous cycle is in the When the fifth interval and the duty cycle of the current cycle is in the second interval or the duty cycle of the previous cycle is in the fifth interval and the duty cycle of the current cycle is in the third interval and 1-Dm2-Dd2≥2Dp, the upper The second level state in which the off-time of the bridge arm is advanced by a dead time.

When the duty cycle of the previous cycle is in the fourth interval and the duty cycle of the current cycle is in the third interval and 1-Dm2-Dd2<2Dp or the duty cycle of the previous cycle is in the fifth interval and the duty cycle of the current cycle is in the third interval And when 1-Dm2-Dd2<2Dp, cancel the first level in the middle of the bridge arm in the current cycle, and continuously output the second level.

When the duty cycle of the previous cycle is in the fourth interval and the duty cycle of the current cycle is in the fourth interval and 2-Dm1-Dm2<Dp, cancel the second level formed by splicing the middle two cycles of the upper bridge arm, and continue to output first level.

When the duty cycle of the previous cycle is in the fourth interval and the duty cycle of the current cycle is in the fifth interval and 1-Dm1<Dp, the turn-off time of the upper bridge arm of the previous cycle is delayed, and the first level is continuously output until current cycle.

When the duty cycle of the previous cycle is in the fifth interval and the duty cycle of the current cycle is in the fourth interval and 1-Dm2<Dp, advance the turn-off time of the upper arm of the current cycle, and continue to output the first cycle since the end of the previous cycle. level.

The motor device provided by the embodiment of the present invention can execute the motor control method provided by any embodiment of the present invention, and has functional modules and beneficial effects corresponding to the execution method.

Embodiment 4

Embodiment 4 of the present invention provides a vehicle. The vehicle is equipped with the motor device of Embodiment 3 above, can execute the motor control method provided by any embodiment of the present invention, and has functional modules and beneficial effects corresponding to the execution method.

It should be understood that steps may be reordered, added or deleted using the various forms of flow shown above. For example, the steps described in the present invention can be performed in parallel, sequentially or in different orders, and as long as the desired results of the technical solutions of the present invention can be achieved, no limitation is imposed herein.

The above-mentioned specific embodiments do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may occur depending on design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. A motor control method, characterized by comprising:

acquiring a torque instruction obtained on a communication bus;

determining a voltage vector instruction according to the torque instruction and the three-phase current of the motor;

determining a pulse width modulation signal waveform according to the voltage vector instruction;

and filtering narrow pulses in the pulse width modulation signal according to the pulse width modulation signal waveforms of two continuous periods.

2. The motor control method of claim 1, wherein the motor controller comprises a three-phase bridge circuit comprising an upper leg and a lower leg;

according to the pulse width modulation signal waveform of two continuous periods, filtering out narrow pulses in the pulse width modulation signal comprises:

determining a first waveform corresponding to the upper bridge arm and a second waveform corresponding to the lower bridge arm according to the pulse width modulation signal waveform of each period;

determining an interval where a pulse width modulation command is located according to the first waveform and the second waveform;

and filtering narrow pulses in the pulse width modulation signals according to the interval where the pulse width modulation instructions of the previous period and the current period are located and the preset duty ratio condition.

3. The motor control method according to claim 2, wherein determining the section in which the pulse width modulation command is located according to the first waveform and the second waveform comprises:

when Dm is more than or equal to 0 and less than 0.5Dp, Dt is 0, Db is 1, and the pulse width modulation command is in a first interval;

when Dm is more than or equal to 0.5Dp and less than Dd, Dt is 0, Db is 1-2Dm, and the pulse width modulation command is in a second interval;

when Dd is less than or equal to Dm and less than 1-Dd, Dt is Dm-Dd, Db is 1-Dm-Dd, and the pulse width modulation command is in a third interval;

when Dm is less than 1-Dd and less than 1, Dt is 2Dm-1, Db is 0, and the pulse width modulation command is in a fourth interval;

when Dm is equal to 1, Dt is equal to 1, Db is equal to 0, and the pwm command is in a fifth interval;

wherein Dt represents an upper bridge arm first level duty ratio, Db represents a lower bridge arm first level duty ratio, Dm represents a duty ratio command from the space vector pulse width modulation module, Dd represents a dead time, and Dp represents a narrow pulse time.

4. The motor control method of claim 3, wherein filtering the narrow pulses in the PWM signal according to the interval where the PWM command of the previous cycle and the current cycle is located and a preset duty ratio condition, comprises:

when the last period duty cycle is in the first interval and the current period duty cycle is in the second interval or the last period duty cycle is in the first interval and the current period duty cycle is in the third interval or the last period duty cycle is in the second interval and the current period duty cycle is in the first interval or the last period duty cycle is in the second interval and the current period duty cycle is in the second interval or the last period duty cycle is in the second interval and the current period duty cycle is in the third interval or the last period duty cycle is in the third interval and the current period duty cycle is in the first interval or the last period duty cycle is in the third interval and the current period duty cycle is in the second interval or the last period duty cycle is in the third interval and the current period duty cycle is in the second interval or the last period duty cycle Db1+ Db2 is more than or equal to 2Dp, or the duty ratio of the last period is in the fifth interval, the duty ratio of the current period is in the fourth interval, 1-Dm2< Dp, or the duty ratio of the last period is in the fifth interval, and the duty ratio of the current period is in the fifth interval, the original signal is directly output;

when the last period duty cycle is in the first interval, the current period duty cycle is in the fourth interval or the last period duty cycle is in the first interval, the current period duty cycle is in the fifth interval or the last period duty cycle is in the second interval, the current period duty cycle is in the fourth interval or the last period duty cycle is in the second interval, the current period duty cycle is in the fifth interval or the last period duty cycle is in the third interval, the current period duty cycle is in the fourth interval, the 1-Dm1-Dd1 is not less than 2Dp, the last period duty cycle is in the third interval, the current period duty cycle is in the fifth interval, the 1-Dm1-Dd1 is not less than 2Dp, the last period duty cycle is in the fourth interval, the current period duty cycle is in the fourth interval, the 2-Dm1-Dm2 is not less than Dp, or the last period duty cycle is in the fourth interval, the current period duty cycle is in the fourth interval When the fifth interval is more than or equal to Dp from 1-Dm1, adding a second level of dead time to the upper bridge arm in the current period, and setting the level as the first level;

when the duty ratio of the last period is in the third interval, the duty ratio of the current period is in the third interval, and Db1+ Db2 is less than 2Dp, the first level formed by splicing the middle two periods of the lower bridge arm is cancelled, and the second level is continuously output;

when the duty ratio of the last period is in the third interval, the duty ratio of the current period is in the fourth interval and 1-Dm1-Dd1 is less than 2Dp, or the duty ratio of the last period is in the third interval and the duty ratio of the current period is in the fifth interval and 1-Dm1-Dd1 is less than 2Dp, the first level in the middle of the lower bridge arm of the last period is cancelled, and the second level is continuously output;

when the last cycle duty cycle is in the fourth interval and the current cycle duty cycle is in the first interval or the last cycle duty cycle is in the fourth interval and the current cycle duty cycle is in the second interval or the last cycle duty cycle is in the fourth interval and the current cycle duty cycle is in the third interval and 1-Dm2-Dd2 is ≧ 2Dp or the last cycle duty cycle is in the fifth interval and the current cycle duty cycle is in the first interval or the last cycle duty cycle is in the fifth interval and the current cycle duty cycle is in the second interval or the last cycle duty cycle is in the fifth interval and the current cycle duty cycle is in the third interval and 1-Dm2-Dd2 is ≧ 2Dp, advancing the upper arm turn-off time of the last cycle by the second level state of one dead zone time;

when the duty ratio of the last period is in the fourth interval, the duty ratio of the current period is in the third interval and 1-Dm2-Dd2<2Dp or the duty ratio of the last period is in the fifth interval and the duty ratio of the current period is in the third interval and 1-Dm2-Dd2<2Dp, the first level in the middle of the lower bridge arm of the current period is cancelled, and the second level is continuously output;

when the duty ratio of the last period is in the fourth interval, the duty ratio of the current period is in the fourth interval, and 2-Dm1-Dm2< Dp, the second level formed by splicing the middle two periods of the upper bridge arm is cancelled, and the first level is continuously output;

when the duty ratio of the previous period is in the fourth interval and the duty ratio of the current period is in the fifth interval and 1-Dm1< Dp, delaying the turn-off time of the upper bridge arm of the previous period, and continuously outputting the first level until the current period;

when the duty ratio of the last period is in the five intervals, the duty ratio of the current period is in the fourth interval, and 1-Dm2 is smaller than Dp, the turn-off time of an upper bridge arm of the current period is advanced, and the first level is continuously output after the last period is finished;

wherein the voltage of the first level is greater than the voltage of the second level.

5. The method of claim 1, further comprising, prior to determining a voltage vector command based on the torque command and three phase currents of the motor:

and carrying out data processing on the torque instruction.

6. The motor control method according to claim 5, wherein the data processing of the torque command includes:

debounce, slope limit, and smooth switching between different control modes for the torque command.

7. The motor control method according to claim 1, characterized in that the width of the narrow pulse is less than or equal to 2 μ s.

8. The motor control method according to claim 3, wherein the width of the dead time is 2 μ s to 5 μ s.

9. An electric motor apparatus, comprising:

the acquisition module is used for acquiring a torque instruction obtained on the communication bus;

the voltage vector instruction determining module is used for determining a voltage vector instruction according to the torque instruction and the three-phase current of the motor;

the waveform determining module is used for determining the waveform of the pulse width modulation signal according to the voltage vector instruction;

and the processing module is used for filtering the narrow pulse in the pulse width modulation signal according to the pulse width modulation signal waveform of two continuous periods.

10. A vehicle characterized by comprising the motor control apparatus of claim 9.

Images