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CN114944842B - Nonlinear Compensation Circuit for Input Buffer of Analog-to-Digital Converter - Google Patents

Nonlinear Compensation Circuit for Input Buffer of Analog-to-Digital Converter Download PDF

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CN114944842B
CN114944842B CN202210098209.0A CN202210098209A CN114944842B CN 114944842 B CN114944842 B CN 114944842B CN 202210098209 A CN202210098209 A CN 202210098209A CN 114944842 B CN114944842 B CN 114944842B
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sampling
input
buffer
analog
digital converter
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CN114944842A (en
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李楠楠
张韩瑞
王晓飞
张�杰
齐欢欢
张鸿
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Xian Jiaotong University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1033—Calibration over the full range of the converter, e.g. for correcting differential non-linearity

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Abstract

公开了模数转换器输入缓冲器的非线性补偿电路，模数转换器输入缓冲器的非线性补偿电路中，输入缓冲器缓冲模数转换器外的输入信号源的输入信号以隔离所述输入信号源与采样开关；共模缓冲器缓冲模数转换器的共模电压；电流复制电路输入端连接输入缓冲器的顶端晶体管的栅端与漏端，输出端连接所述共模缓冲器的顶端晶体管的栅端，使得输入缓冲器的顶端晶体管与共模缓冲器的顶端晶体管组成电流镜；采样电路由采样开关与采样电容组成，采样电容的上极板通过采样开关连接至输入缓冲器的输出，将采样电容的下极板连接至共模缓冲器的输出，在采样开关断开之后，将采样电容的上极板连接至参考电压，采样电容保持输入信号与共模信号的压差，并送进比较器。

The invention discloses a nonlinear compensation circuit of an analog-to-digital converter input buffer. In the nonlinear compensation circuit of the analog-to-digital converter input buffer, the input buffer buffers the input signal of an input signal source outside the analog-to-digital converter to isolate the input signal source from a sampling switch; the common-mode buffer buffers the common-mode voltage of the analog-to-digital converter; the input end of a current replication circuit is connected to the gate end and the drain end of a top transistor of the input buffer, and the output end is connected to the gate end of the top transistor of the common-mode buffer, so that the top transistor of the input buffer and the top transistor of the common-mode buffer form a current mirror; the sampling circuit is composed of a sampling switch and a sampling capacitor, the upper plate of the sampling capacitor is connected to the output of the input buffer through the sampling switch, the lower plate of the sampling capacitor is connected to the output of the common-mode buffer, and after the sampling switch is disconnected, the upper plate of the sampling capacitor is connected to a reference voltage, the sampling capacitor maintains the voltage difference between the input signal and the common-mode signal, and sends it to a comparator.

Description

Nonlinear compensation circuit of input buffer of analog-to-digital converter
Technical Field
The invention relates to the field of integrated circuits, in particular to a nonlinear compensation circuit of an input buffer of an analog-to-digital converter.
Background
An analog-to-digital converter (Analog to Digital Converter, ADC) is one of the most important modules in a System on Chip (SoC), and converts an analog signal in nature into a digital signal, so that the digital System can process the signal. High-speed and high-precision ADC is urgently needed in the application fields of 5G, millimeter wave communication, phased array radar and the like. The main ADC structures currently in use are mainly the following, full parallel (Flash) ADC, pipeline (PIPELINED) ADC, successive approximation (Successive Approximation Register, SAR) ADC, and Sigma-Delta ADC. In the structures, the SAR ADC has a simpler structure, lower power consumption and good compatibility with advanced processes, and PIPELINED ADC can realize higher precision while realizing high speed due to the advantage of a pipeline. With the progress of integrated circuit technology in recent years, the advantages of the SAR ADC are gradually exerted, so the implementation structure of the high-speed high-precision ADC has evolved from the conventional PIPELINED ADC to PIPELINED SAR ADC combining PIPELINED ADC with the SAR ADC, which can realize the advantages of high speed and high precision and low power consumption. PIPELINED ADC, SAR ADC, PIPELINED SAR ADC are shown in fig. 1,2, 3, respectively.
Whether conventional PIPELINED ADC or PIPELINED SAR ADC which has appeared recently, the signal source driving the ADC chip will face a great challenge when the sampling rate of the ADC is continuously increasing, especially up to 500MSPS or more. Due to parasitic inductance of the ADC package connection (bonding wire) and parasitic capacitance related to input, a kickback (kick back) phenomenon caused by continuous switching of large signals of the sampling switch in the ADC may seriously damage the input signal of the ADC, so that the performance of the whole ADC is obviously deteriorated. In order to solve the kickback problem of the high-speed and high-precision ADC, an on-chip input buffer is usually required to be inserted before a sampling switch of the ADC, so that the kickback of the sampling switch can be isolated, and the driving requirement on an input signal source can be reduced. In order to realize high speed, the current implementation scheme of the input buffer is mainly a source follower structure, and when the subsequent sampling capacitor is driven, the instantaneous current flowing into the capacitor is completely related to the input signal, so that serious nonlinear distortion occurs to the output signal of the buffer, and the linearity index of the whole ADC is greatly reduced. Another source-follower configuration based on compensation capacitors (as shown in fig. 4) can suppress the nonlinearity of the buffer to a certain extent, but the compensation capacitors are directly connected with the input, so that the signal bandwidth of the ADC is reduced, and the dc power consumption of the source-follower needs to be increased to ensure the flow direction of the compensation current.
The above information disclosed in the background section is only for enhancement of understanding of the background of the invention and therefore may contain information that does not form the prior art that is already known in the country to a person of ordinary skill in the art.
Disclosure of Invention
In view of the foregoing deficiencies or drawbacks of the prior art, a non-linearity compensation circuit for an input buffer of an analog-to-digital converter is provided, which compensates for non-linearities of a portion of the input buffer by an output of a common mode buffer in an ADC. The aim of the invention is achieved by the following technical scheme.
The non-linearity compensation circuit of the analog-to-digital converter input buffer comprises,
The input buffer is used for buffering an input signal of an input signal source outside the analog-to-digital converter so as to isolate the input signal source from the sampling switch, is of a source follower structure, and is short-circuited with a gate end and a drain end of a top transistor so as to generate current which fluctuates along with the input signal and serve as input current of the current replication circuit;
a common mode buffer for buffering common mode voltage of the analog-to-digital converter, the common mode buffer being of a source follower structure;
the input end of the current copying circuit is connected with the gate end and the drain end of the top end transistor of the input buffer, and the output end of the current copying circuit is connected with the gate end of the top end transistor of the common mode buffer, so that the top end transistor of the input buffer and the top end transistor of the common mode buffer form a current mirror;
The sampling circuit is composed of a sampling switch and a sampling capacitor, wherein an upper polar plate of the sampling capacitor is connected to the output of the input buffer through the sampling switch, a lower polar plate of the sampling capacitor is connected to the output of the common mode buffer, and after the sampling switch is disconnected, the upper polar plate of the sampling capacitor is connected to a reference voltage, and the sampling capacitor keeps the pressure difference between an input signal and a common mode signal and is fed into the comparator.
In the nonlinear compensation circuit of the input buffer of the analog-to-digital converter, the output of the input buffer is respectively connected to the upper polar plate of the sampling capacitor C 1N、C1P、C2N、C2P through the sampling switch S 1、S2、S6、S7 to sample the input signal.
In the nonlinear compensation circuit of the input buffer of the analog-to-digital converter, the output of the common mode buffer is connected to the lower polar plate of the sampling capacitor through the sampling switch S 3、S8 to sample the common mode voltage.
In the nonlinear compensation circuit of the input buffer of the analog-to-digital converter, the current replication circuit is a group of current mirrors.
In the nonlinear compensation circuit of the input buffer of the analog-to-digital converter, the sampling switch is a grid voltage bootstrap switch, the sampling capacitor is of a split capacitor structure, the two original sampling capacitors are split into four sampling capacitors C 1N、C1P、C2N、C2P with equal capacitance values, the capacitance value of the sampling capacitors C 1N、C1P、C2N、C2P is half of that of the original sampling capacitors, and the total capacitance value is kept consistent.
In the nonlinear compensation circuit of the input buffer of the analog-to-digital converter, the sampling circuit is divided into a sampling stage and a conversion stage, when the sampling stage is in, clock signals phi s and phi p are high level, clock signal phi c is low level, an upper polar plate of a sampling capacitor C 1N、C1P、C2N、C2P is connected to the output of the input buffer through a switch S 1、S2、S6、S7, and a lower polar plate is connected to the output of the common mode buffer through a sampling switch S 3、S8.
In the nonlinear compensation circuit of the input buffer of the analog-to-digital converter, when the sampling circuit is in a comparison stage, clock signals phi s and phi p are low level, clock signal phi c is high level, an upper polar plate of a sampling capacitor C 1N、C1P、C2N、C2P is connected to positive and negative reference levels REFP and REFN, a lower polar plate of the sampling capacitor is connected to a comparator of the analog-to-digital converter, and the input signal on the sampling capacitor is quantized to obtain a corresponding digital code.
In the nonlinear compensation circuit of the input buffer of the analog-to-digital converter, the analog-to-digital converter is a pipeline successive approximation analog-to-digital converter, after the analog-to-digital converter finishes input quantization, the pipeline successive approximation analog-to-digital converter enables the upper polar plate of the sampling capacitor to be continuously switched, the input of the comparator is the lower polar plate of the sampling capacitor, the input of the comparator returns to the common mode level, and then the sampling stage of the next period is repeatedly operated.
In the nonlinear compensation circuit of the input buffer of the analog-to-digital converter, the input of the comparator of the pipeline successive approximation analog-to-digital converter is the pressure difference between the upper polar plate and the lower polar plate of the sampling capacitor, and the pressure difference is the difference between the output of the input buffer and the output of the common mode buffer.
In the nonlinear compensation circuit of the input buffer of the analog-to-digital converter, the output of the input buffer comprises an input signal and nonlinear components of the input signal, the output of the common mode buffer comprises a common mode signal and nonlinear components of the input signal, the voltage difference of the upper polar plate and the lower polar plate of the sampling capacitor is carried out to obtain the input signal, and the nonlinear calibration of the input buffer is completed.
Advantageous effects
The nonlinear components of the input signals generated in the input buffer are transmitted to the common mode buffer through the current replication circuit, and the nonlinear components are respectively connected to the upper polar plate and the lower polar plate of the sampling capacitor, so that the nonlinearity of part of the input signals can be eliminated; the invention does not connect compensation capacitor on the input signal path, thus avoiding attenuation of input bandwidth caused by the compensation capacitor, and does not use the compensation capacitor, thus avoiding circuit area cost caused by the current compensation path.
The foregoing description is only an overview of the technical solutions of the present invention, to the extent that it can be implemented according to the content of the specification by those skilled in the art, and to make the above-mentioned and other objects, features and advantages of the present invention more obvious, the following description is given by way of example of the present invention.
Drawings
Various other advantages and benefits of the present invention will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. It is evident that the figures described below are only some embodiments of the invention, from which other figures can be obtained without inventive effort for a person skilled in the art. Also, like reference numerals are used to designate like parts throughout the figures.
In the drawings:
FIG. 1 is a block diagram of a prior art PIPELINED ADC;
FIG. 2 is a block diagram of a prior art SAR ADC architecture;
FIG. 3 is a block diagram of a prior art PIPELINED SAR ADC;
FIG. 4 is a diagram of an input buffer configuration based on compensation capacitance;
FIG. 5 is a schematic diagram of a nonlinear compensation circuit of an input buffer of an analog-to-digital converter according to the present invention;
FIG. 6 is a timing diagram of a non-linear compensation circuit of an analog-to-digital converter input buffer according to the present invention;
FIG. 7 is a schematic diagram of FFT results outputted by a nonlinear compensation circuit employing an analog-to-digital converter input buffer according to the present invention;
FIG. 8 is a schematic diagram of FFT results output by a comparative normal input buffer;
FIG. 9 is a diagram showing the SFDR comparison of the present invention with a conventional input buffer output at different input frequencies.
The invention is further explained below with reference to the drawings and examples.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to fig. 1 to 9. While specific embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
It should be noted that certain terms are used throughout the description and claims to refer to particular components. Those of skill in the art will understand that a person may refer to the same component by different names. The description and claims do not identify differences in terms of components, but rather differences in terms of the functionality of the components. As used throughout the specification and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. The description hereinafter sets forth a preferred embodiment for practicing the invention, but is not intended to limit the scope of the invention, as the description proceeds with reference to the general principles of the description. The scope of the invention is defined by the appended claims.
For the purpose of facilitating an understanding of the embodiments of the invention, reference will now be made to the drawings of several embodiments illustrated in the drawings, and the accompanying drawings are not to be taken as limiting the embodiments of the invention.
As shown in fig. 5 to 6, the non-linearity compensation circuit of the analog-to-digital converter input buffer includes,
The input buffer is used for buffering an input signal of an input signal source outside the analog-to-digital converter so as to isolate the input signal source from the sampling switch, is of a source follower structure, and is short-circuited with a gate end and a drain end of a top transistor so as to generate current which fluctuates along with the input signal and serve as input current of the current replication circuit;
a common mode buffer for buffering common mode voltage of the analog-to-digital converter, the common mode buffer being of a source follower structure;
the input end of the current copying circuit is connected with the gate end and the drain end of the top end transistor of the input buffer, and the output end of the current copying circuit is connected with the gate end of the top end transistor of the common mode buffer, so that the top end transistor of the input buffer and the top end transistor of the common mode buffer form a current mirror;
The sampling circuit is composed of a sampling switch and a sampling capacitor, wherein an upper polar plate of the sampling capacitor is connected to the output of the input buffer through the sampling switch, a lower polar plate of the sampling capacitor is connected to the output of the common mode buffer, and after the sampling switch is disconnected, the upper polar plate of the sampling capacitor is connected to a reference voltage, and the sampling capacitor keeps the pressure difference between an input signal and a common mode signal and is fed into the comparator.
The invention uses a common mode buffer in a high-speed high-precision ADC as a compensation circuit to copy the current of an input buffer to the common mode buffer, wherein the output of the input buffer is connected with an upper polar plate of a sampling capacitor of the ADC, the output of the common mode buffer is connected with a lower polar plate of the sampling capacitor, and a current mirror structure is formed by a current source of the input buffer and a current source of the common mode buffer so as to ensure that the upper polar plate and the lower polar plate of the sampling capacitor generate consistent nonlinear fluctuation when a sampling switch is switched, thereby compensating the nonlinearity of the input buffer to a great extent and remarkably improving the linearity of the input buffer of the high-speed high-precision ADC.
In a preferred embodiment of the nonlinear compensation circuit of the input buffer of the analog-to-digital converter, the output of the input buffer is connected to the upper plate of the sampling capacitor C 1N、C1P、C2N、C2P through the sampling switch S 1、S2、S6、S7 to sample the input signal.
In a preferred embodiment of the nonlinear compensation circuit of the input buffer of the analog-to-digital converter, the output of the common-mode buffer is connected to the lower plate of the sampling capacitor through a sampling switch S 3、S8 to sample the common-mode voltage.
In a preferred embodiment of the nonlinear compensation circuit of the analog-to-digital converter input buffer, the current replica circuit is a set of current mirrors.
In a preferred embodiment of the nonlinear compensation circuit of the input buffer of the analog-to-digital converter, the sampling switch is a gate voltage bootstrap switch, the sampling capacitor is in a split capacitor structure, the two original sampling capacitors are split into four sampling capacitors C 1N、C1P、C2N、C2P with equal capacitance values, the capacitance value of the sampling capacitors is half of the capacitance value of the original sampling capacitors, and the total capacitance values are kept consistent.
In the preferred embodiment of the nonlinear compensation circuit of the input buffer of the analog-to-digital converter, the sampling circuit is divided into a sampling stage and a conversion stage, when the sampling stage is in, the clock signals phi s and phi p are high level, the clock signal phi c is low level, the upper polar plate of the sampling capacitor C 1N、C1P、C2N、C2P is connected to the output of the input buffer through the switch S 1、S2、S6、S7, and the lower polar plate is connected to the output of the common mode buffer through the sampling switch S 3、S8.
In the preferred embodiment of the nonlinear compensation circuit of the input buffer of the analog-to-digital converter, when the sampling circuit is in the comparison stage, the clock signals Φ s and Φ p are low level, the clock signal Φ c is high level, the upper polar plate of the sampling capacitor C 1N、C1P、C2N、C2P is connected to the positive and negative reference levels REFP and REFN, the lower polar plate of the sampling capacitor is connected to the comparator of the analog-to-digital converter, and the input signal on the sampling capacitor is quantized to obtain the corresponding digital code.
In the preferred embodiment of the nonlinear compensation circuit of the input buffer of the analog-to-digital converter, the analog-to-digital converter is a pipeline successive approximation analog-to-digital converter, and after the analog-to-digital converter quantizes the input, the pipeline successive approximation analog-to-digital converter enables the upper polar plate of the sampling capacitor to be continuously switched, the input of the comparator is the lower polar plate of the sampling capacitor, the comparator returns to the common mode level, and then the sampling stage of the next period is entered to repeat the operation.
In the preferred embodiment of the nonlinear compensation circuit of the input buffer of the analog-to-digital converter, the input of the comparator of the pipeline successive approximation analog-to-digital converter is the difference between the upper polar plate and the lower polar plate of the sampling capacitor, and the difference is the difference between the output of the input buffer and the output of the common mode buffer.
In a preferred embodiment of the nonlinear compensation circuit of the input buffer of the analog-to-digital converter, the output of the input buffer comprises an input signal and a nonlinear component of the input signal, the output of the common mode buffer comprises a common mode signal and a nonlinear component of the input signal, the voltage difference between the upper polar plate and the lower polar plate of the sampling capacitor is carried out to obtain the input signal, and the nonlinear calibration of the input buffer is completed.
For better understanding, as shown in fig. 5 to 6, the nonlinear compensation circuit of the analog-to-digital converter input buffer includes:
An input buffer (differential) for buffering the input (output of the signal source) outside the ADC chip, realizing the isolation between the input signal source and the sampling switch, improving the driving capability of the input signal, and shorting the gate terminal and the drain terminal of the top transistor to generate a current fluctuating with the input signal;
The common mode buffer is used for buffering the common mode voltage (reference output) of the ADC, improving the capacity of the common mode voltage to drive a larger sampling capacitor, and the common mode buffer is also in a source follower structure and is used for connecting the gate end of the top transistor to the output of the current replication circuit;
the input end of the current copying circuit is connected with the gate end and the drain end of the top current source of the input buffer, and the output of the current copying circuit is connected to the gate end of the top current source of the common mode buffer, so that the top current source of the input buffer and the top current source of the common mode buffer form a current mirror to form the current copying circuit;
the sampling circuit consists of a sampling switch and a sampling capacitor, wherein an upper polar plate of the capacitor is connected to the output of the input buffer through the switch, and a lower polar plate of the capacitor is connected to the output of the common mode buffer. After the switch is opened, the upper plate of the capacitor is connected to the reference voltage and the sampling capacitor will maintain the voltage difference between the input signal and the common mode signal and feed the comparator. The output of the input buffer (differential) is respectively connected to the upper polar plate of the sampling capacitor C 1N、C1P、C2N、C2P through the sampling switch S 1、S2、S6、S7, so as to realize the sampling of the input signal. The output of the common mode buffer is connected to the lower polar plate of the sampling capacitor through a switch S 3、S8, so that the sampling of the common mode is realized. The current replica circuit is a set of current mirrors with inputs derived from the top current source of the input buffer (differential) and outputs connected to the top current source of the common mode buffer.
In one embodiment, the sampling circuit includes a sampling capacitor and a sampling switch, wherein the sampling switch is mostly a gate voltage bootstrap switch. The sampling capacitor adopts a split capacitor structure, namely the original two sampling capacitors (differential) are split into four C 1N、C1P、C2N、C2P with equal capacitance values, the capacitance value is half of the capacitance value of the original sampling capacitor, and the total capacitance value is kept consistent. The sampling circuit works in a sampling stage and a conversion stage. when in the sampling phase, the clock signals Φ s and Φ p are high, the clock signal Φ c is low, the upper plate of the sampling capacitor C 1N、C1P、C2N、C2P is connected to the output of the input buffer (differential) through the switch S 1、S2、S6、S7, and the lower plate is connected to the output of the common mode buffer through the switch S 3、S8. When in the comparison stage, the clock signals phi s and phi p are low level, the clock signal phi c is high level, the upper electrode plate of the sampling capacitor C 1N、C1P、C2N、C2P is connected to the positive and negative reference level REFP, and REFN, and meanwhile, the lower polar plate of the sampling capacitor can be connected to the comparator of the ADC, so that the input signal on the sampling capacitor is quantized to obtain a corresponding digital code. Taking a pipelined successive approximation ADC as an example here. After the ADC quantizes the input, the pipeline successive approximation ADC can continuously switch the upper polar plate of the sampling capacitor, so that the input of the comparator, namely the lower polar plate of the sampling capacitor, returns to the common mode level. And then, the sampling stage of the next period is entered, the operation is repeated, and the quantized input of the pipeline successive approximation ADC is the difference between the upper polar plate and the lower polar plate of the sampling capacitor, namely the difference between the output of the input buffer and the output of the common mode buffer. The output of the common mode buffer comprises a common mode signal and a part of nonlinear components of the input signal, and when the voltages of the upper polar plate and the lower polar plate of the sampling capacitor are differentiated, a relatively pure input signal can be obtained, so that nonlinear compensation of the input buffer is completed.
To further understand the present invention, in one embodiment, a non-linearity compensation circuit of an analog-to-digital converter input buffer includes an input buffer (differential), a common mode buffer, a current replica circuit, and a sampling circuit. Wherein the current replica circuit is composed of a top current source of the input buffer (differential) and a top current source of the common mode buffer.
In one embodiment, the plates of the sampling capacitor C 1N、C1P、C2N、C2P are respectively connected to the output of the input buffer and the output of the common mode buffer, and at the same time, the top current source of the common mode buffer and the top current source of the input buffer form a current mirror structure, the current flowing in the common mode buffer contains nonlinear current components of the input buffer fluctuating along with the input signal, and then the current components are connected to the sampling capacitor through the main input tube of the common mode buffer, so that the current information is converted into voltage information and stored on the sampling capacitor C 1N、C1P、C2N、C2P. At this time, the voltage information of the upper polar plate of the sampling capacitor also contains nonlinear components brought by the input buffer, and the nonlinear components of the input buffer exist in the upper polar plate and the lower polar plate of the sampling capacitor, so that the nonlinear components of the input buffer can be mutually offset, a purer input signal is obtained, and the nonlinear compensation of the input buffer is realized.
In one embodiment, as shown in fig. 5, the nonlinear compensation circuit of the analog-to-digital converter input buffer includes an input buffer (differential), a common mode buffer, a current mirror, and a sampling circuit. Wherein the current mirror consists of the top current source of the input buffer (differential) and the top current source of the common mode buffer.
In one embodiment, as shown in fig. 5, an input buffer (differential) is formed by transistors M 1、M7、M9、M4、M8、M13, where M 7、M8 is the main input pair, transistor M 2、M5、M10、M3、M6、M12 is the common mode buffer, and M 5、M6 is the main input. Wherein M 1(M4) and M 3(M2) of the input buffer constitute a current mirror, and the current flowing in the input buffer is duplicated through the current mirror structure, thereby generating the same nonlinear component, and counteracting the nonlinearity of the input buffer. The sampling circuit is composed of a switch S 1、S2、S3、S6、S7、S8 and a capacitor C 1N、C1P、C2N、C2P.
In one embodiment, the high-speed high-precision ADC input buffer operation timing for non-linearity compensation using the current replica architecture of the present invention is shown in fig. 6. Each cycle is divided into a sampling phase phi s and a transition phase phi c.
In one embodiment, assuming that the input buffer is operating in the sampling phase, i.e., the clock signal phi s、φp is high and the clock signal phi c is low, the switch S 1、S2、S3、S6、S7、S8 is turned on and the upper plate of C 1N、C1P、C2N、C2P is connected to the output of the input buffer and the lower plate is connected to the output of the common mode buffer. Assuming that the input signal is V IN、VIP and the output signal is V TOPN,VTOPP at this time, the current flowing in the input buffer (differential) is I IP、IIN, then the relationship is:
wherein V th、μn、Cox and W/L are respectively the threshold voltage, electron mobility, gate oxide capacitance and width-to-length ratio of the transistor.
The current flowing in the input buffer mainly comprises two parts of current, one part is bias current I b of the buffer itself, and the other part is current I cp、Icn flowing through the sampling capacitor when the circuit belongs to the sampling stage, and the main source is nonlinear. The relation is as follows:
The input of the common mode buffer is V CM, the output is V CMOUTP、VCMOUTN, the current flowing in the common mode buffer is I CMP、ICMN, and the relation is that:
Because the current flowing in the common mode buffer in the circuit is sourced from the top current mirror structure, the frequency of the current is consistent with the frequency of the input signal and is in a higher frequency, and the area of the transistor in the current replication path is larger, so that larger parasitic capacitance is caused, and the common mode buffer current has a certain phase lag compared with the input current. To overcome the bias caused by the current phase shift, we can differentially cross the current of the common mode buffer, and then the common mode buffer current I CMP、ICMN is related to the current I IP、IIN of the input buffer as follows:
in addition, in the sampling phase, the current I cp、Icn flowing through the sampling capacitor is desirably set to the value:
When the input signal is a sinusoidal signal, the amplitude is assumed to be a, and then the relationship between the current and the voltage is:
the current relationship of the input buffer at this time is:
at the end of the sampling phase, the voltage difference stored on the capacitor is the difference between the output V TOPN(VTOPP of the input buffer) and the output V CMOUTN(VCMOUTP of the common mode buffer), the voltage value is:
substitution equations (4), (7) are available when the phase shift in the current mirror satisfies the following condition:
the differential pressure across the capacitor is:
At this time, the voltage difference between the upper and lower plates of the capacitor is the difference between the input signal and the common mode, and the nonlinearity of the input buffer can be completely eliminated. However, in practical circuit implementation, since the phase shift of the current mirror replica circuit varies with frequency, the nonlinearity of the input signal cannot be completely eliminated, but the nonlinearity of the input signal can be improved greatly.
After the sampling is finished, the conversion stage is started, namely the clock signal phi s、φp is low level, when the clock signal phi c is high level, the switch S 4、S5、S9、S10 is conducted, the upper polar plate of the C 1N、C1P、C2N、C2P is connected with the positive and negative reference voltages REFP and REFN, at the moment, the upper polar plate of the capacitor can be connected to the comparator for comparison, the input signal is quantized, and after the pipeline successive approximation ADC conversion is finished, the sampling stage of the next period is started, and the above operation is repeated.
When the replica circuit structure of the present invention is used to perform nonlinear compensation on the input buffer of the high-speed and high-precision ADC, it is assumed that the parasitic inductance of the package bondwire line is 2nH, the input signal frequency is 748Mhz, the input swing is 1.6Vpp, the total sampling capacitance (single-ended) is 280FF, the sampling frequency is 2Ghz, that is, the sampling time is 250ps, at this time, the total current of the input buffer and the common mode buffer is 9.7mA, and the difference between the output of the input buffer and the output of the common mode buffer is subjected to Fast Fourier Transform (FFT) to obtain a power spectrum density diagram, as shown in fig. 7. It can be seen that the linearity index, i.e. Spurious Free Dynamic Range (SFDR), of the output signal is 82.38dB.
In order to compare the performance of the invention with that of a common input buffer, a common input buffer circuit is designed as a comparison circuit under the same input condition and comprises the same circuit area, and the structure of the common input buffer circuit is a source follower structure. At this time, the normal input buffer power supply current is about 14mA. When the output of the input buffer is subjected to a Fast Fourier Transform (FFT), a power spectral density map is obtained, as shown in fig. 8. It can be seen that the linearity index of the output signal, that is, the Spurious Free Dynamic Range (SFDR), is 61.37dB, in order to further illustrate the universality of the calibration method of the present invention, the difference between the output of the input buffer and the output of the common mode buffer is subjected to fast fourier transform at different input frequencies at the sampling frequency of 2Ghz, and the SFDR of the output is compared with that of the common input buffer, as shown in fig. 9, the calibration method can still improve the linearity of the input buffer at different input frequencies.
In summary, the nonlinear compensation circuit of the input buffer of the analog-to-digital converter provided by the invention effectively improves the nonlinearity of the input buffer without increasing the power consumption and the area cost of the input buffer, thereby improving the performance of the ADC.
Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above-described specific embodiments and application fields, and the above-described specific embodiments are merely illustrative, and not restrictive. Those skilled in the art, having the benefit of this disclosure, may effect numerous forms of the invention without departing from the scope of the invention as claimed.

Claims (7)

1.一种模数转换器输入缓冲器的非线性补偿电路，其特征在于：其包括，1. A nonlinear compensation circuit for an analog-to-digital converter input buffer, characterized in that it comprises: 输入缓冲器，其缓冲模数转换器外的输入信号源的输入信号以隔离所述输入信号源与采样开关，输入缓冲器为源随器结构，其顶端晶体管的栅端与漏端短接产生随所述输入信号波动的电流以作为电流复制电路的输入电流；An input buffer, which buffers an input signal of an input signal source outside the analog-to-digital converter to isolate the input signal source from the sampling switch, and the input buffer is a source follower structure, and the gate terminal and the drain terminal of the top transistor of the input buffer are short-circuited to generate a current that fluctuates with the input signal as an input current of the current replication circuit; 共模缓冲器，其缓冲模数转换器的共模电压，共模缓冲器为源随器结构；A common mode buffer, which buffers the common mode voltage of the analog-to-digital converter, and the common mode buffer is a source follower structure; 电流复制电路，其输入端连接所述输入缓冲器的顶端晶体管的栅端与漏端，输出端连接所述共模缓冲器的顶端晶体管的栅端，使得输入缓冲器的顶端晶体管与共模缓冲器的顶端晶体管组成电流镜；A current replicating circuit, wherein the input end is connected to the gate end and the drain end of the top transistor of the input buffer, and the output end is connected to the gate end of the top transistor of the common mode buffer, so that the top transistor of the input buffer and the top transistor of the common mode buffer form a current mirror; 采样电路，由采样开关与采样电容组成，采样电容的上极板通过采样开关连接至输入缓冲器的输出，将采样电容的下极板连接至共模缓冲器的输出，在采样开关断开之后，将采样电容的上极板连接至参考电压，采样电容保持输入信号与共模信号的压差，并送进比较器，所述采样开关为栅压自举开关，采样电容为分裂电容结构，两个原采样电容分裂为四个容值相等的采样电容C1N、C1P、C2N、C2P，其容值为原采样电容容值的一半，总容值保持一致，采样电路工作分为采样阶段和转换阶段，Φs、Φp、Φc均为时钟信号，当处于采样阶段时，Φs与Φp为高电平，Φc为低电平，采样电容C1N、C1P、C2N、C2P上极板通过开关S1、S2、S6、S7连接至输入缓冲器的输出，下极板通过采样开关S3、S8连接到共模缓冲器的输出，采样电路处于比较阶段时, 时钟信号Φs与Φp为低电平，时钟信号Φc为高电平，采样电容C1N、C1P、C2N、C2P的上极板连接至正负参考电平REFP、REFN，采样电容的下极板连接至模数转换器的比较器，对采样电容上的输入信号进行量化，得到对应的数字码。The sampling circuit is composed of a sampling switch and a sampling capacitor. The upper plate of the sampling capacitor is connected to the output of the input buffer through the sampling switch, and the lower plate of the sampling capacitor is connected to the output of the common-mode buffer. After the sampling switch is disconnected, the upper plate of the sampling capacitor is connected to the reference voltage. The sampling capacitor maintains the voltage difference between the input signal and the common-mode signal and sends it to the comparator. The sampling switch is a gate voltage bootstrap switch. The sampling capacitor is a split capacitor structure. Two original sampling capacitors are split into four sampling capacitors C1N , C1P , C2N , and C2P with equal capacitance. The capacitance is half of the capacitance of the original sampling capacitor, and the total capacitance is consistent. The sampling circuit is divided into a sampling stage and a conversion stage. Φs , Φp , and Φc are all clock signals. When in the sampling stage, Φs and Φp are high level, Φc is low level, and the upper plates of the sampling capacitors C1N , C1P , C2N , and C2P are switched through switches S1 , S2 , S6 , and S 7 is connected to the output of the input buffer, and the lower plate is connected to the output of the common-mode buffer through sampling switches S 3 and S 8. When the sampling circuit is in the comparison stage, the clock signals Φ s and Φ p are low level, the clock signal Φ c is high level, the upper plates of the sampling capacitors C 1N , C 1P , C 2N , and C 2P are connected to the positive and negative reference levels REFP and REFN, and the lower plates of the sampling capacitors are connected to the comparator of the analog-to-digital converter. The input signal on the sampling capacitor is quantized to obtain the corresponding digital code. 2.根据权利要求1所述的模数转换器输入缓冲器的非线性补偿电路，其特征在于：输入缓冲器的输出通过采样开关S1、S2、S6、S7分别连接接到采样电容C1N、C1P、C2N、C2P的上极板采样所述输入信号。2. The nonlinear compensation circuit of the analog-to-digital converter input buffer according to claim 1, characterized in that the output of the input buffer is connected to the upper plates of sampling capacitors C 1N , C 1P , C 2N , and C 2P respectively through sampling switches S 1 , S 2 , S 6 , and S 7 to sample the input signal. 3.根据权利要求1所述的模数转换器输入缓冲器的非线性补偿电路，其特征在于：所述共模缓冲器的输出通过采样开关S3、S8连接到采样电容的下极板采样共模电压。3. The nonlinear compensation circuit of the analog-to-digital converter input buffer according to claim 1, characterized in that the output of the common-mode buffer is connected to the lower plate of the sampling capacitor through sampling switches S3 and S8 to sample the common-mode voltage. 4.根据权利要求1所述的模数转换器输入缓冲器的非线性补偿电路，其特征在于：所述电流复制电路为一组电流镜。4 . The nonlinear compensation circuit of the analog-to-digital converter input buffer according to claim 1 , wherein the current replication circuit is a set of current mirrors. 5.根据权利要求1所述的模数转换器输入缓冲器的非线性补偿电路，其特征在于：模数转换器为流水线逐次逼近模数转换器，当模数转换器对输入量化完成之后，流水线逐次逼近模数转换器使得采样电容的上极板不断切换，比较器的输入即为采样电容的下极板，回到共模电平，之后进入下一个周期的采样阶段重复操作。5. The nonlinear compensation circuit of the analog-to-digital converter input buffer according to claim 1 is characterized in that: the analog-to-digital converter is a pipeline successive approximation analog-to-digital converter. After the analog-to-digital converter completes input quantization, the pipeline successive approximation analog-to-digital converter causes the upper plate of the sampling capacitor to switch continuously, and the input of the comparator is the lower plate of the sampling capacitor, which returns to the common mode level, and then enters the sampling stage of the next cycle to repeat the operation. 6.根据权利要求5所述的模数转换器输入缓冲器的非线性补偿电路，其特征在于：流水线逐次逼近模数转换器的比较器的输入为采样电容上下极板的压差，其为输入缓冲器的输出、共模缓冲器的输出之差。6. The nonlinear compensation circuit of the analog-to-digital converter input buffer according to claim 5 is characterized in that the input of the comparator of the pipeline successive approximation analog-to-digital converter is the voltage difference between the upper and lower plates of the sampling capacitor, which is the difference between the output of the input buffer and the output of the common-mode buffer. 7.根据权利要求6所述的模数转换器输入缓冲器的非线性补偿电路，其特征在于：输入缓冲器的输出包括输入信号以及输入信号的非线性分量，共模缓冲器的输出包括共模信号以及输入信号的非线性分量，对采样电容上下极板电压求差得到输入信号，完成对输入缓冲器的非线性校准。7. The nonlinear compensation circuit of the analog-to-digital converter input buffer according to claim 6 is characterized in that: the output of the input buffer includes the input signal and the nonlinear component of the input signal, the output of the common-mode buffer includes the common-mode signal and the nonlinear component of the input signal, and the input signal is obtained by subtracting the voltages of the upper and lower plates of the sampling capacitor to complete the nonlinear calibration of the input buffer.
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